Datasheet

i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018
128 NXP Semiconductors
Electrical Characteristics
4.12.20.2 SSI Receiver Timing with Internal Clock
Figure 91 depicts the SSI receiver internal clock timing and Table 83 lists the timing parameters for the
receiver timing with the internal clock.
Figure 91. SSI Receiver Internal Clock Timing Diagram
Table 83. SSI Receiver Timing with Internal Clock
ID Parameter Min Max Unit
Internal Clock Operation
SS1 AUDx_TXC/AUDx_RXC clock period 81.4 — ns
SS2 AUDx_TXC/AUDx_RXC clock high period 36.0 — ns
SS3 AUDx_TXC/AUDx_RXC clock rise time — 6.0 ns
SS4 AUDx_TXC/AUDx_RXC clock low period 36.0 — ns
SS5 AUDx_TXC/AUDx_RXC clock fall time — 6.0 ns
SS7 AUDx_RXC high to AUDx_TXFS (bl) high — 15.0 ns
SS9 AUDx_RXC high to AUDx_TXFS (bl) low — 15.0 ns
SS11 AUDx_RXC high to AUDx_TXFS (wl) high — 15.0 ns
SS13 AUDx_RXC high to AUDx_TXFS (wl) low — 15.0 ns
SS20 AUDx_RXD setup time before AUDx_RXC low 10.0 — ns
SS21 AUDx_RXD hold time after AUDx_RXC low 0.0 — ns
SS50
SS48
SS1
SS4SS2
SS51
SS20
SS21
SS49
SS7
SS9
SS11
SS13
SS47
SS3
SS5
AUDx_TXC
(Output)
AUDx_TXFS (bl)
(Output)
AUDx_TXFS (wl)
(Output)
AUDx_RXD
(Input)
AUDx_RXC
(Output)