Datasheet

Architectural Overview
i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018
NXP Semiconductors 9
2 Architectural Overview
The following subsections provide an architectural overview of the i.MX 6DualPlus/6QuadPlus
processor system.
2.1 Block Diagram
Figure 2 shows the functional modules in the i.MX 6DualPlus/6QuadPlus processor system.
Figure 2. i.MX 6DualPlus/6QuadPlus Automotive Grade System Block Diagram
NOTE
The numbers in brackets indicate number of module instances. For example,
PWM (4) indicates four separate PWM peripherals.
Smart DMA
(SDMA)
Shared Peripherals
AP Peripherals
ARM Cortex A9
SSI (3)
eCSPI (5)
MPCore Platform
Timers/Control
GPT
PWM (4)
EPIT (2)
GPIO
WDOG (2)
I
2
C (3)
IOMUXC
OCOTP
AUDMUX
KPP
Boot
ROM
CSU
Fuse Box
Debug
DAP
TPIU
CAAM
(16KB Ram)
Security
USB OTG +
3 HS Ports
CTIs
Internal
Host PHY2
OTG PHY1
ESAI
External
Memory
RAM
(512KB)
LDB
1/2 LCD
Displays
Domain (AP)
SJC
1MB L2 cache
SCU, Timer
WLAN
USB OTG
JTAG
(IEEE1149.6)
Bluetooth
MMC/SD
eMMC/eSD
SATA II
3.0Gbps
GPS
Audio,
Power
Mgmnt.
SPBA
CAN (2)
Digital
Audio
5xFast-UART
SPDIF Rx/Tx
Video
Proc. Unit
(VPU + Cache)
3D Graphics
Proc. Unit
(GPU3D)
AXI and AHB Switch Fabric
1/2 LVDS
(WUXGA+)
Battery Ctrl
Device
NOR Flash
PSRAM
LPDDR2 (400 MHz)
DDR3 (532 MHz)
1-Gbps ENET
MLB 150
4x Camera
Parallel/MIPI
(96KB)
Clock and Reset
PLL (8)
CCM
GPC
SRC
XTALOSC
OSC32K
PTM’s CTI’s
HDMI 1.4
Display
GPMI
HSI/MIPI
MIPI
Display
DSI/MIPIHDMI
2xHSIC
PHY
PCIe Bus
ASRC
SNVS
(SRTC)
uSDHC (4)
Modem IC
2D Graphics
Proc. Unit
(GPU2D)
MMC/SD
SDXC
Raw/ONFI 2.2
Nand-Flash
MMDC
EIM
Keypad
A9-Core
L1 I/D Cache
Timer, Wdog
4x
Crystals
& Clock sources
ImageProcessing
Subsystem
2x IPUv3H
Temp Monitor
MLB/Most
OpenVG 1.1
Proc.
Unit
(GPU VG)
Mbps
10/100/1000
Ethernet
Network
(dev/host)
Interface
2xCAN
Interface
GPSGPS
CSI2/MIPI
Application Processor
Power Management Unit
(PMU) LDOs
PRG PRE