Datasheet

NXP Semiconductors
UM11183
KITFS85SKTEVM evaluation board
UM11183 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved.
User manual Rev. 3 — 6 December 2019
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Figure 10 shows the sequence to be followed to enter in Debug mode. The voltage
sequence on the kit is done using switches installed on the board, while the OTP
registers configuration is managed by the FlexGUI GUI. This is described in detail in the
following sections.
a
a
a
-
0
3
1
9
6
6
V
DBG
DBG
VSUP1/2
WAKE1
SPI/I2C
REGx
> V
SUP_UVH
> WAKE12
VIH
SPI/I2C OTP pgm
OFF PWR UP ON
SPI/I2C
Figure 10. Debug mode entry
Figure 11 shows the hardware kit implementation.
aaa-032762
SW1
SW2
VSUP1/2
FS8500
Debug
ref
OTP level
(DBG = 8 V)
2
1
3
VSUP
DBG_OTP
(8 V)
DBG VDDI2C
USB
VBAT
to KL25
DC/DC
P5V_USB
DBG_BAT
WAKE1
SW3
J17
Figure 11. OTP hardware implementation
4.3 Kit featured components
Figure 12 identifies important components on the board and Table 2 provides additional
details on these components.