Reference guide

Errata and Added Information to
MC68LC302 Low Power Integrated Multiprotocol
Processor Reference Manual Rev 1
MC68LC302
SEMICONDUCTOR PRODUCT INFORMATION
February 21, 1997
Section 2– Configuration, Clocking, Low Power Modes, and
Internal Memory Map
1. SCCE2 Register
In section 2-24, in Table 2-6, the SCCE2 register should be 8 bits wide, not 16 bits as shown.
Section 3 - Sytstem Integration Block
1. Periodic Interrupt Timer equation
In section 3.7.4.2, in the periodic interrupt timer period equation, the "+1" should be carried
through the equations.
Section 5 - Signal Description
1. Bus Request Signal description
In section 5.8, the Bus Request signal is shown incorrectly in figure 5-7 an d the description
below the figure is incorrect. The pin is shown as bidirectional, but should be an out put only.
The description shoud read, “This signal is an open-drain output request signal from the
IDMA and SDMA when the internal EC000 core is disabled.”
2. Port A / Bootstrap Mode description
In section 5.14 in the “NOTE” section, “To enable Boot from SCC2” should be replaced with
“To enable Boot from SCC1.” The Bootstrap mode is only available on SCC1.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

Summary of content (3 pages)