Reference guide

Cluster (Dashboard) Using S12HZ256 as a Single-Chip Solution Designer Reference Manual, Rev. 0
Freescale Semiconductor 9
Chapter 2
Benefits and Features of the 9S12HZ256 Controller
2.1 Introduction
As shown in this chapter, the S12HZ family of devices offers an excellent complement of peripherals and
a broad range of memory and packages.
2.2 Basic Features
Some of the S12HZ family benefits are shown below. Features have been broken down by type for your
convenience.
HCS12 Core:
• 16-bit HCS12 CPU
– Upward compatible with M68HC11 instruction set
– Interrupt stacking and programmer’s model identical to M68HC11
–20-bit ALU
– Instruction queue
– Enhanced indexed addressing
• Multiplexed external bus interface (MEBI)
• Module mapping control (MMC)
• Interrupt control (INT)
• Debugger and breakpoints (DBG)
• Background debug mode (BDM)
Memory:
• 256K, 128K, 64K Flash EEPROM
• 2K, 1K byte EEPROM
• 12K, 6K, 4K byte RAM
CRG:
• Low current oscillator
• Phase locked loop (PLL)
• Reset, clocks
• Computer operating properly (COP) watchdog
• Real time interrupt
• Clock monitor