Datasheet
UBA20260 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 10 October 2011 14 of 30
NXP Semiconductors
UBA20260
600 V driver IC for step dimmable CFLs
As the internal step reference voltages are independent from the mains voltage, the lamp
current output is kept constant. Making the lamp current output not susceptible to line
voltage fluctuations. The MDL level sets the minimum lamp current level and is adjusted
using the MDL pin. An accurate minimum dimming voltage level is set using an internal
reference current and an external resistor R
MDL
. The internal reference current is derived
from the internal band gap reference circuit and resistor R
ext(RREF)
. The other two step
dimming levels are set at a fixed voltage offset referenced to the adjusted MDL level. This
means that these levels shift by the same voltage as the MDL shifts. When the MDL level
is at the default level, the light output in DIM_2, DIM_3 and MDL modes is approximately
66 %, 33 % and 5 % from nominal.
7.5 Protection functions and Power-down mode
7.5.1 Coil saturation protection
CSP is integrated into the IC to allow the use of small CFL lamps and use of small coils.
Saturation of these coils is detected and excessive overcurrent due to saturation is
prevented. CSP is only enabled during the ignition state. A cycle-by-cycle control
mechanism is used to limit voltages and currents in the resonant circuit when there is no
or delayed ignition. It prevents coil saturation, limits high peak currents and the dissipation
in the half-bridge power transistors.
Coil saturation is detected by monitoring the voltage across the R
SLS
resistor. A trigger is
generated when this voltage exceeds the V
th(sat)SLS
level. When saturation is detected, a
fixed current I
o(sat)CF
is injected into the C
CF
capacitor to shorten the half-bridge
Fig 11. Voltage on pin CSI as function of dim step
0
001aam770
1.2
1.0
0.8
0.6
0.2
V
i(CSI)
= V
MDL
V
clamp(CSI)
Internal clamp
V
DD
off-on toggle
∆V
dim2(CSI)
V
DD
off-on toggle
(1) = V
DD
off-on toggle
∆V
dim3(CSI)
V
i(CSI)
V
RMS
0.4
DIM_2
DIM_1
100 %
DIM_3
MDL
(1)
(1)