Datasheet

UBA20260 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 10 October 2011 6 of 30
NXP Semiconductors
UBA20260
600 V driver IC for step dimmable CFLs
7.2 Lamp start-up cycle
7.2.1 Reset state
The UBA20260 is in the reset state when the supply voltage on the V
DD
pin is below the
V
DD(rst)
level. In the reset state, part of the internal supply is turned off and all registers,
counters and timers are undefined. The hold state latch is reset and both the external high
and low side power transistors (Q1/Q2) are non-conductive.
During power-up, the low voltage supply capacitor on the V
DD
pin is charged through the
external start-up resistor. The start-up state is entered when the voltage on the V
DD
pin is
above the V
DD(rst)
level. The UBA20260 enters the reset state when the supply voltage on
the V
DD
pin drops below V
DD(rst)
.
7.2.2 Start-up state
The start-up state is entered by charging the low voltage supply capacitor on the V
DD
pin
through the external start-up resistor. At start-up, the High-Side (HS) transistor is
non-conductive and the Low-Side (LS) transistor is conductive to enable charging of the
bootstrap capacitor. This capacitor supplies the HS driver and Level shifter circuit
connected between the FS and HBO pin. A DC reset circuit is integrated into the HS
driver. This circuit ensures that below the FS pin lockout voltage, the output voltage
V
GHS
 V
HBO
is zero.
When the start-up state is entered, the circuit only starts oscillating at f
bridge(max)
when the
low voltage supply (V
DD
) reaches the V
DD(start)
value. The circuit always starts oscillating
at f
bridge(max)
. The circuit enters the preheat state as soon as the capacitor connected to
the CP pin is charged above the V
th(CP)max
voltage level. To keep oscillating, V
DD
must be
above V
DD(stop)
and below the V
DD(clamp)
upper limit.
During the start-up state, the voltage on the CF pin is zero and on the CB pin is close to
zero. The voltage on the CP pin rises just above V
th(CP)max
during the start-up state as
shown in Figure 9
.
7.2.3 Preheat state
After starting at f
bridge(max)
, the frequency decreases by charging capacitor C
CI
using an
output current circuit. The preheat current sensor circuit controls the current output circuit,
until the momentary value of the voltage across sense resistor R
SLS
reaches the fixed
preheat voltage level (SLS pin). At this level, the current of the preheat current sensor
reaches the charge and discharge balanced state on capacitor C
CI
to set the half-bridge
frequency.
The preheat time consists of eight saw-tooth pulses at the CP pin. The preheat time
begins as soon as the capacitor on the CP pin is charged above V
th(CP)max
value. During
the preheat time, the current feedback sensor circuit (input CSI pin) is disabled.
To increase noise immunity, an internal filter of 30 ns is included at the SLS pin.
If the level on the V
DD
pin drops below V
DD(stop)
during preheat, the preheat state is
immediately stopped and the circuit enters the hold state. The hold state delays a new
preheat cycle by a fixed delay time. A fixed voltage drop on the preheat capacitor C
CP
and
the fixed discharge current on the CP pin are used to set the delay time.