Datasheet

UBA2071_A_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 23 June 2008 16 of 35
NXP Semiconductors
UBA2071; UBA2071A
Half bridge control IC for CCFL backlighting
PWM lamp-on situation is reached again through a reverse sequence of events, starting
the half bridge actions, increasing the voltage on CSWP, increasing the lamp current back
to the controlled value. Switch S1 is closed (conducting) again when the voltage on the
CSWP pin has reached the voltage on the CVFB pin again.
The IC waits until the CSWP sweep-up
6
has reached the current/voltage control level at
the CVFB pin before sweeping down. This prevents the lamps from going out completely
when deep dimming on CSWP pin is combined with a large value capacitor.
After the switching frequency has reached f
sw(max)
, both GL and GH are made low, so both
half bridge powers will be non-conducting, see Figure 12. This guarantees zero lamp
current during the PWM-off period
7
, while the CSWP frequency sweep acts as soft stop
and soft restart, of which the softness can be set by the value of the capacitor connected
to the CSWP pin.
Three pins are available to configure the internal PWM generator: the CPWM pin, PWMA
pin, and the PWMD pin. The two possible PWM configurations are shown in Figure 13.In
the analog or master mode the internal PWM generator is active and generating the PWM
signal. This signal is put on the PWMD pin, which is automatically configured as an
output. The minimum duty cycle of the internal PWM generator is limited to δ
PWM(min)
.
6. CSWP sweep-up is frequency sweep-down.
7. Until the ringing of voltage on the half bridge point has died away, some (capacitive) current may still cause a light glow at the hot
side of the lamps. Therefore it is advised to maximize the attenuation of the ringing circuit (made up by the transformer inductance
and the ∆V/∆t limiting capacitor).
Fig 12. PWM dim cycle waveforms
t
V
CSWP
max
reg
5 V
V
DD
V
DD
0
t
V
PWMD
0
t
V
GH
− V
SH
0
t
V
GL
0
014aaa107