Datasheet

UBA2071_A_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 23 June 2008 17 of 35
NXP Semiconductors
UBA2071; UBA2071A
Half bridge control IC for CCFL backlighting
When the CPWM pin is connected to ground the IC is put in digital or slave mode and the
PWMD pin is an input. The internal PWM generator is not used. The IC uses the PWM
signal provided on the PWMD pin.
PWM dimming of multiple ICs can be synchronized by configuring one IC as master and
the others as slaves and connecting all PWMD pins together.
The PWMD input/output is active low. A voltage below V
th(L)(PWMD)
on the pin will turn the
lamps on, while a voltage above V
th(H)(PWMD)
will turn the lamps off.
PWM dimming is only enabled in normal mode, when no fault condition exists. The only
exception is when an external detected fault condition is entered via the NONFAULT pin,
then PWM dimming remains active, see Figure 15.
8.12 The fault timer
The fault timer provides a delay in between the detection of a fault and the shutdown of
the IC (enter STOP state). Its time is controlled by a capacitor at the CT pin.
Any fault condition will start the timer. When the timer is activated, the capacitor at the
CT pin will be alternatively charged and discharged, see Figure 14. After the fault output
delay time, t
d(o)fault)
, the NONFAULT pin is activated (pulled low). This is to signal to any
external circuit that a fault has been detected and the IC will stop if that fault continues.
After the fault time-out period t
to(fault)
is reached the IC will enter STOP state.
Fig 13. PWM dimming configurations
C1
R
PWMA
PWMA
analog in
PWM out
CPWM 9
PWMD
V
PWMA(ref)
14
13
PWM intern
UBA2071
A: analog or master mode
PWM in
UBA2071
B: digital or slave mode
PWM intern
014aaa108
PWMA
CPWM 9
PWMD
14
13