User's Manual

5.4 BADR3
BADR3 is an 8-bit data bus for reading, writing and control of the individual 82C55
chips and the 82C54. Refer to Table 5-2 for register offsets.
Table 5-2. BADR3 Registers
Interrupt Control 2Interrupt Control 2BADR3 + 15h
Interrupt Control 1Interrupt Control 1BADR3 + 14h
Counter ConfigureCounter ConfigurationBADR3 + 13h
N/AN/ABADR3 + 12h
Counter 2Counter 2BADR3 + 11h
Counter 1Counter 1BADR3 + 10h
Group 3 ConfigureGroup 3 ConfigureBADR3 + F
Group 3 Port C DataGroup 3 Port C DataBADR3 + E
Group 3 Port B DataGroup 3 Port B DataBADR3 + D
Group 3 Port A DataGroup 3 Port A DataBADR3 + C
Group 2 ConfigureGroup 2 ConfigureBADR3 + B
Group 2 Port C DataGroup 2 Port C DataBADR3 + A
Group 2 Port B DataGroup 2 Port B DataBADR3 + 9
Group 2 Port A DataGroup 2 Port A DataBADR3 + 8
Group 1 ConfigureGroup 1 ConfigureBADR3 + 7
Group 1 Port C DataGroup 1 Port C DataBADR3 + 6
Group 1 Port B DataGroup 1 Port B DataBADR3 + 5
Group 1 Port A DataGroup 1 Port A DataBADR3 + 4
Group 0 ConfigureGroup 0 ConfigureBADR3 + 3
Group 0 Port DataGroup 0 Port C DataBADR3 + 2
Group 0 Port B DataGroup 0 Port B DataBADR3 + 1
Group 0 Port A DataGroup 0 Port A DataBADR3 + 0
WRITE FUNCTION
READ FUNCTIONREGISTER
The 82C55 may be programmed to operate in Input/Ouput (mode 0), Strobed
Input/Ouput (mode 1) or Bi-Directional Bus (mode 2). The following information
describes mode 0 operation. Users needing information regarding other modes of
operation should refer to an Intel or Intersil 82C55 data sheet.
Upon power-up, an 82C55 is reset and defaults to the input mode. No further
programming is needed to use the 24 lines of an 82C55 as TTL inputs.
5.4.1 Group 0 8255 Configuration & Data
GROUP 0, PORT A DATA
BADR3 + 0
READ/WRITE
D0D1D2D3D4D5D6D7
01234567
11