DAQP-208/208H/308 Type II PCMCIA Data Acquisition Adapters Users Manual INTERFACE CARDS FOR PERSONAL COMPUTERS OMEGA ENGINEERING, INC. One Omega Drive P.O. Box 4047 Stamford, CT 06907-4047 Tel: (203) 359-1660 Fax: (203) 359-7700 Toll free: 1-800-826-6342 E-mail: das@omega.com www.dasieee.
WARRANTY/DISCLAIMER OMEGA ENGINEERING, INC., warrants this unit to be free of defects in materials and workmanship for a period of 13 months from the date of purchase. OMEGA warranty adds an additional one (1) month grace period to the normal one (1) year product warranty to cover shipping and handling time. This ensures that OMEGA’s customers receive maximum coverage on each product. If the unit should malfunction, it must be returned to the factory for evaluation.
http://www.omega.com info@omega.com Servicing North America : USA: ISO 9001 Certified One Omega Drive, Box 4047 Stamford, CT 06907-0047 Tel: (203) 359-1660 E-mail: info@omega.com Canada: 976 Bergar Laval (Quebec) H7L 5A1 Tel: (514) 856-6928 E-mail: info@omega.
United Kingdom: ISO 9002 Certified One Omega Drive, River Bend Technology Drive Northbank, Irlam, Manchester M44 5EX, England Tel: 44 (161) 777-6611 FAX: 44 (161) 777-6622 Toll Free in England: 0800-488-488 E-mail: info@omega.co.uk It is the policy of OMEGA to comply with all worldwide safety and EMC/EMI regulations that apply. OMEGA is constantly pursuing certification of it’s products to the European New Approach Directives. OMEGA will add the CE mark to every appropriate device upon certification.
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Table of Contents 1. Introduction ....................................................... 8 2. Hardware Configuration and Initial Setup 2.1 2.2 2.3 2.4 ................. 9 Software Installation: Windows 95/98/2000 ® . . . . . . . . . . . . . . . . . . . . 9 2.1.1 Windows 2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.2 Windows 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.
5.2 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.1 Data FIFO Register (base + 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Scan List Queue Register (base + 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Status Register (base + 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.4 Digital I/O Register . . . . . . . . . . . . . . . . . . .
List of Figures and Tables Figure 3-1. DAQP Series Card Output Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-2. CP-DAQPA/UIO-37 D37 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-3. UIO-37 Terminal Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-4. DAQP Card with Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1. Introduction DAQP series cards are PCMCIA type II data acquisition adapters with 4 differential or 8 single-ended analog input channels. The number of input channels can be expanded to 128 when used with input expansion cards. DAQP series products include the DAQP-208, the DAQP-208H and the DAQP-308.
2. Hardware Configuration and Initial Setup 2.1 Software Installation: Windows 95/98/2000 ® An “INF” file (daqpcard.inf) is included on the root directory of the DaqSuite CD to allow easy configuration in the Windows environment. Windows uses the “INF” file to determine the system resources required by the DAQP card, searches for available resources to fill the requirements and then updates the Windows hardware registry with entries to allocate the resources.
2.1.2 Windows 98 1. Insert the DAQP card into any available PC Card socket. The first time a new PC Card type is installed the “Add New Hardware Wizard” window will open. Click Next to continue. 2. The Add New Hardware Wizard provides several options to configure the DAQP card. Select the recommended option radio button: “Search for the best driver for your device”. Click Next to continue. 3. An Install from Disk dialog box will open.
2.1.4 Viewing Resources with Device Manager Follow the instructions provided here to view resources used by the DAQP card using the “Device Manager” utility in Windows. 1. Double click the My Computer icon located on the Windows desktop and then double click the Control Panel icon. Double click the System icon to open the System Properties window. 2. Click the “Device Manager” tab located at the top of the dialog box.
To remove the DAQP card from your Windows NT 4.0 system, run the associated driver support uninstallation program using the Add/Remove Programs icon located in the Control Panel folder. (This will remove all registry entries applicable to your hardware). When the uninstallation is complete, shut down your computer and remove the hardware. To verify these actions, reboot and follow steps 1 and 2 above to ensure the “DAQPDRV” listing no longer appears under the “Device” category.
2.3 Data Acquisition Software and Drivers Data acquisition software and driver support installations are available from the DaqSuite CD demo main menu. 1. Quatech’s DaqEZ? - This software package was specifically designed to support all Quatech’s data acquisition adapter functions and is included free of charge with your hardware.
2.4 Software Installation: Windows 3.x and MS-DOS® Two software configuration programs are provided with the DAQP card: a Client Driver named DAQPA_CL.SYS and a card Enabler named DAQPA_EN.EXE. Either one of these programs may be used to configure the card but only one may be used at a time. Table 2-1 below highlights the differences between the Client Driver and the Enabler programs.
2.4.1 Client Driver for MS-DOS For systems using MS-DOS and PCMCIA Card and Socket Services software, a Client Driver named “DAQPA_CL.SYS” is provided to configure the DAQP series cards. PCMCIA Card and Socket Services software is not provided with your DAQP card, but is available from your vendor. Some versions of Card and Socket Services dated before 1993 do not support general purpose I/O cards.
2.4.1.1 Client Driver Command Line Options The DAQP series Client Driver accepts up to eight command line arguments from the user to determine the configuration of the DAQP card. If any arguments are provided, the Client Driver will attempt to configure any DAQP card with the options specified in the order they are entered on the command line. Each argument must be enclosed in parenthesis and must be separated from other arguments by a space in the command line.
Example 3 DEVICE = C:\DAQPA_CL.SYS (s0,b300,i5) Example 3 is also a single command line argument. The client Driver will attempt to configure the DAQP card inserted in socket 0 at base address 300H and IRQ level 5. If either address 300H or IRQ level 5 is unavailable, the card will NOT be configured. In addition, the Client Driver will NOT configure any DAQP card inserted into any socket except socket 0. Example 4 DEVICE = C:\DAQPA_CL.
2.4.1.3 Common Problems Generic Client Drivers Many Card and Socket Services packages include a generic client driver (or SuperClient) which configures standard I/O devices. If one of these generic client drivers is installed, it may configure the DAQP card and cause the DAQP series Client Driver to fail installation.
2.4.2 Enabler for MS-DOS For systems that are not operating PCMCIA Card and Socket Services software, the DAQP series card includes an Enabler program to enable and configure the DAQP card. This Enabler, DAQPA_EN.EXE, will operate in any DOS system using an Intel 82365SL or PCIC compatible PCMCIA host adapter. In order to use the DAQP series Enabler for DOS, the system must NOT be configured with Card and Socket Services software.
6. Reboot the system and note the message displayed when the Enabler is loaded. If the Enabler reports the desired card configuration, the installation process is complete.
2.4.2.1 Enabler Command Line Options To configure a DAQP series card, the Enabler requires one command line argument from the user to determine the configuration. This argument must be enclosed in parenthesis. Within the argument, a comma (no space) must be used to separate the parameters from each other if there are two or more parameters. The following parameters may be specified in the command line argument: s socket Specifies the PCMCIA socket number to configure. “Socket” must be in the range 0 - 15.
Example 4 DEVICE = C:\DAQPA_EN.EXE (s0,b300,i5,wCC) Here the Enabler will configure the DAQP card in socket 0 with a base address at 300H and IRQ level 5 using a configuration memory window at CC000H. Example 5 DEVICE = C:\DAQPA_EN.EXE (s0,r) DEVICE = C:\DAQPA_EN.EXE (s0,r,b300,i5) These two command line arguments are equivalent because of the “r” option. The Enabler will release the configuration used by the DAQP card in socket 0 using a configuration memory window at D0000H. Example 6 DEVICE = C:\DAQPA_E
3. Field Wiring The DAQP card is fitted in with a 32-pin 0.8 mm shielded connector. See Figure 3-1 for pin assignments. 33 30 25 20 15 10 5 1 Reserved Ch 0 Ch 0 (-) / Ch 4 Ch 1 Ch 1 (-) / Ch 5 Ch 2 Ch 2 (-) / Ch 6 Ch 3 Ch 3 (-) / Ch 7 GND DA0 DA1 +5V GND ExtClock ExtGate ExtOut GND FullPower SSH (Synch. Sample Hold) DI 0 / External Trigger DI 1 / GS 0 (Ext. Gain Sel. DI 2 / External Clock DI 3 / GS 1 (Ext. Gain Sel. DO 0 / CS0 (Ext. Chn. Sel. 0) DO 1 / CS1 (Ext. Chn. Sel. 1) DO 2 / CS2 (Ext. Chn.
3.1 CP-DAQPA Cable Assembly The cable assembly included with your DAQP card, part number CP-DAQPA, converts the card’s 32 pin I/O connector to a standard D37 connector. Figure 3-2 illustrates the D37 connector pin assignments for the CP-DAQPA and the optional screw terminal block UIO-37.
Table 3-1 lists cable mapping for the CP-DAQPA Hirose-32 to D37 connectors. Table 3-1.
3.2 UIO-37 Screw Terminal Block For applications requiring discrete wiring connections, the UIO-37 terminal block shown in Figure 3-3 provides a simple way of connecting signals to the DAQP card. The D37 connector is available in either male or female and has two rows of screw terminals. The first row is numbered from pin 1 to pin 19 and the second row from pin 20 to pin 37. Wire gage 16 through 28 is recommended for screw terminal connections. Figure 3-4 illustrates the DAQP card with accessories.
4. Theory of Operation The DAQP card consists of 4 differential or 8 single-ended analog input channels each with a bipolar input range of ±10v, ±5v, ±2.5v or ±1.25v (programmable gain of 1, 2, 4 or 8). The A/D converter, either 12 -bit or 16-bit, can be operated at a top speed of 100,000 samples per second (10 µs per sample). The A/D converter uses left-justified 2's complement coding. For the 16-bit version, the output ranges from -32768 to 32767.
4.2 Analog Input Multiplexer Differential or single-ended configuration is determined by bit 6 of the high byte in the scan list register. ‘1’ selects differential input, while a ‘0’ selects single-ended input. Expansion cards will only support single-ended channels. It is strongly recommended that single-ended or differential selection be uniform for all internal channels (e.g., all 4 channels as differential or all 8 channels as single-ended).
4.4 Scan List Register One entry to the scan list register contains a 16-bit word or two 8-bit bytes. It specifies the internal channel and gain selection in the high byte or MSB, and the external channel and gain selection in the low byte or LSB, in addition to other control and configuration settings. The external selections are used for expansion card channels (up to 128), while the internal selections are for channels on board the DAQP card.
4.5 Trigger Circuit The DAQP card can be triggered by software, an external TTL signal, the analog input passing through the preset threshold or the pacer clock. For the TTL or analog trigger, an active trigger edge can be selected for either the low-to-high or high-to-low transition. In one-shot trigger mode, one trigger (either internal or external), will start one and only one scan of all channels specified in the scan list.
4.6 A/D Converter and Data FIFO The DAQP card always assumes a bipolar input range of ±10V if the gain is one. The output data format will always be in 2's complement (and left justified for 12-bit versions). The data acquisition time of the A/D converter is 2 µs while it’s conversion time is no more than 8 µs. The output of the A/D converter is fed into a data FIFO providing data buffering of up to 512 samples (2048 with 2K option installed).
4.7 Interrupt and Status The DAQP card has three interrupt sources, the end-of-scan (EOS) interrupt, the FIFO threshold interrupt and the timer interrupt. The control register (base + 2, write only) has two bits to enable or disable the EOS and FIFO interrupts independently. However, it is strongly recommended that the two interrupts be used exclusively. Bit 5 of the auxiliary control register (base + 15, write only) enables or disables the timer interrupt.
4.9 A/D State Machine The DAQP card has an internal state machine that controls A/D operation, (see Figure 4-1). The state machine defaults to S0 after power up or reset. The normal state flow would be first S0 to S3, initiated by a scan list (queue) flush command (RSTQ). Then the queue must be programmed by writing into the queue (base + 1). With the queue being programmed, the next step is moving the state machine from S3 back to S0.
4.10 D/A Circuit The DAQP series PC card is equipped with two D/A channels. The 12-bit D/A converter is a serial converter supporting synchronous update and is configured for a bipolar output range from -5V to +5V. The 12-bit output data format is always in 2’s complement (right justified), with the upper 4 bits indicating the output channel number (binary ‘0000’ for channel 0 and ‘0001’ for channel 1).
bit 3 of the command register at base + 7). The integrity of the latched count is guaranteed by the logic design. The timer port is allocated at base + 10 (low byte) and base + 11 (high byte). The 16 bit reload register is accessed when writing to the port, while the read-latch register is accessed when reading the port. The up-counter cannot be accessed directly. Bit 4 of the auxiliary control register selects the timer clock source.
5. I/O Registers 5.1 PCMCIA Interface The information in this section is provided for those who need low level PCMCIA interface details for the DAQP card. The client driver or enabler that comes with the DAQP card will be sufficient for most applications. The DAQP card performs data acquisition for all host computers equipped with a version 2.10 compliant PCMCIA interface. The DAQP card has a form factor of type II (5 mm thick). The card is highly flexible with respect to addressing and interrupt level use.
5.1.1 Configuration and Option Register (COR) Bits 7 and 6 of the Configuration Option Register are defined by the PCMCIA standard as the SRESET and the LevlREQ Bits. A “1” written into the SRESET bit puts the card in reset state, while a “0” moves it out of reset state. In reset state, it behaves as if a hardware reset is received from the host. The LevlREQ bit controls the type of interrupt signal generated by the DAQP card.
5.2 Address Map The DAQP card uses eight consecutive I/O locations within the system I/O address space. The base address of the adapter is determined during hardware configuration. The eight I/O locations are used by the DAQP card as summarized in the following table. Table 5-4.
5.2.1 Data FIFO Register (base + 0) The data FIFO register is considered as the access port to the data FIFO, which holds up to 2048 data words from the A/D conversion results. The port is also used for programming the data FIFO thresholds, as explained later in this section. Note: Although the data FIFO register is 8 bits wide, it is strongly recommended that the register be accessed as a 16 bit word to guarantee integrity.
almost empty thresholds (in bytes). The first word specifies the almost empty threshold, (not used, can be set to anything), while the second word determines the almost full threshold.
The threshold should be set to a value from 1 to FIFO size minus 1. (Default is set to 7 at reset or power up). Refer to Table 5-7 for FIFO threshold settings. Table 5-7. Data FIFO Threshold Setting Threshold Defaul t Threshold Range Suggested Value Almost Empty 7 Irrelevant Irrelevant Almost Full 7 1...4095 2048 Mode 1 is FIFO test mode, in which data bytes will be written into the data FIFO and read back from it.
5.2.1.3 FIFO Flags When reading the register under mode 1 or 3, the first available data byte from the data FIFO will be returned if it is not empty, otherwise the returned byte is not defined. The FIFO full flag will be cleared after the data FIFO register is read provided there are no more data bytes written into the FIFO by the A/D converter under mode 1 or 3. The same will happen to the FIFO almost full flag if the data bytes available in the FIFO are less than the almost full threshold.
5.2.2.1 Scan List Queue Programming The scan list queue must be programmed when the A/D circuit card is idle. Each queue entry contains two bytes as described above and the integrity of the entry must be guaranteed. (The scan list queue is write only). The queue should be flushed before writing into it. Refer to the Auxiliary Control Register section for information on scan list queue reset. The first entry of the queue should have bit 7 (LSB) set to “1” as the first channel mark.
5.2.2.2 Channel Configuration Bits 5 and 4 (LSB) in a queue entry specify the gain of the external expansion card for the external channel selected by bits 0-3 of the same byte. Each expansion card has up to 16 channels (0, 1, 2, ..., 15). Each channel may have a gain of 1, 2, 4 or 8 (low gain voltage input card) or 1, 10, 100 or 1000 (high gain voltage input card). If there is no expansion card for the internal channel specified then the external channel and gain selection in the LSB will be ignored.
5.2.2.5 Expansion Mode Bit 5 must be set to “1” if there is an expansion card(s) connected to the DAQP card. All of the digital output lines (bits 0-3) will be used for external channel selection and two of the four digital input lines (bit 1 and 3) will be used for external gain selection. 5.2.2.6 Interrupt Enable Bits 4 and 3 are used for interrupt enable control. The end-of-scan (EOS) interrupt will be enabled (disabled) by setting bit 4 to “1” (“0”).
5.2.2.9 Analog Trigger Threshold The analog trigger threshold can only be set by the output of D/A channel 1, with an equivalent range from -10V to +10V (full A/D converter input range). The threshold level is set at the A/D converter input (after the programmable gain amplifier), not the one at the input connector (before the PGA).
5.2.3 Status Register (base + 2) The status register is read only and shares the same offset as the control register. It reports data FIFO flag, A/D interrupt and A/D conversion status. Table 5-13 lists the status register bit definition. Table 5-13.
5.2.4 Digital I/O Register 5.2.4.1 Digital Output The four digital output lines share the same pins on the interface connector as the four external channel selection bits. When using an expansion card(s), bit 5 of the control register (base + 2) should be set to “1” so that the four digital output lines will be driven by the external channel selection bits from the scan FIFO.
5.2.5 Pacer Clock (base + 4, + 5, + 6) The pacer clock is actually a 24-bit auto re-load frequency divider. It contains a 24 bit divisor register, a 24 bit counter, an internal clock pre-scaler and a clock source multiplexer. Figure 5-1 shows the pacer clock block diagram. 10 MHz Divide by 2 Divide by 10 Divide by 100 24 bit Counter Pacer Clock Output 24 bit Register External Clock Input Figure 5-1.
5.2.6 Command Register (base + 7) The command register is used for sending control commands to the DAQP card including arm/trigger (or start A/D), scan list queue and data FIFO flush, stop A/D and timer/counter latch commands. It also sets the data program/access mode for the data FIFO. The command bits (bit 3 to 7) are actually ‘monostable’ or self-clearing after the specified command function is completed and do not require clearing.
5.2.6.3 Flush Data FIFO Command The data FIFO should be flushed before data acquisition is initiated by the trigger/arm command, but not until after the scan list has been configured. The flush command may also be followed by FIFO threshold programming. After the FIFO is flushed, the FIFO empty flag will be set to “1” and the almost full and full flags reset to “0”. Anytime the data FIFO is flushed, the default threshold setting will be restored (7 bytes to full) by the hardware.
After the thresholds are programmed, set the access control bit to “1” by writing a byte of 01H into the auxiliary control register. This will make the following read/write operation access the data bytes in the FIFO instead of it’s thresholds. It is recommended that the access control bit be set to “1” when sending other commands (flush scan list, stop A/D, or trig/arm) to the DAQP card by writing into the auxiliary control register.
5.2.7.2 D/A Port Interface The data link between the D/A data port and the D/A converter is a serial link. The port interface contains a 16 bit buffer register and a 16 bit shift register. On the other side of the link, there are input and output registers in each D/A channel of the D/A converter. The actual analog output voltage will be determined by the code value loaded into the output register. A data word written into the D/A port will first be latched into the 16 bit buffer register.
5.2.8 Timer/Counter Port (base + 10, base + 11) The timer/counter port can be accessed as either a 16 bit word at base + 8, or two consecutive bytes at base + 8 (low byte) and base + 9 (high byte). The port contains a 16 bit reload register, a 16 bit up-counter and a 16 bit read latch register and the associated control logic. The reload register is write only. It holds the initial value (or the reload value) for the up-counter.
5.2.8.2 Timer/Counter Clock Source Bit 2 of the auxiliary control register (base + 15, write) selects the timer/counter clock source. The source can be either the internal 1 MHz clock (bit 2 is “0”) or the external clock (bit 2 is “1”). Because of the pin confinement, the timer/counter external clock input is shared with the A/D external clock input, which is also digital input bit 2. The external clock should have a minimum pulse width of 100 ns and a maximum frequency of 5 MHz. 5.2.8.
5.2.9 Auxiliary Control Register (base + 15) This register configures the operation of A/D, D/A and the timer counter. It is 8-bit wide and write only. Bit 7 picks between TTL and analog trigger source. Bit 6 sets the pre-trigger option. Bit 5 is for the timer/counter interrupt control. Bits 3 and 4 determine the timer/counter operation modes while bit 2 selects the timer/counter clock source. Bits 1 and 0 specify the D/A update modes. Table 5-21.
Table 5-22.
6. Specifications A/D Converter Acquisition + Conversion Monotonicity Integral linearity error Differential linearity error Full scale error Aperture delay Analog Input Number of input channels Input range Programmable gain Maximum over-voltage Input impedance 12-Bit Version 2 ms + 8 ms No missing codes ± 1 LSB ± 1 LSB ± 0.5 % 40 ns 16-Bit Version 2 ms + 8 ms No missing codes ± 3 LSB +3/-2 LSB ± 0.5 % 40 ns 4 differential / 8 single-ended, expandable to 128 ±10, ±5, ±2.5, ±1.
Analog Output Number of output channels Output Settling Time Output range Output Current DC Output impedance 2 (single-ended only) 10 ms ±5V (bipolar only) ±2 mA 0.
DAQP-208/208H/308 Users Manual Version 2.30 April 12, 2000 Part No.
