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FIFO Flags

When reading the register under mode 1 or 3, the first available data byte from the data FIFO

will be returned if it is not empty, otherwise the returned byte is not defined. The FIFO full

flag will be cleared after the data FIFO register is read provided there are no more data bytes

written into the FIFO by the A/D converter under mode 1 or 3. The same will happen to the

FIFO almost full flag if the data bytes available in the FIFO are less than the almost full

threshold. The FIFO empty flag will be set immediately after the last byte is read from the

FIFO. FIFO size is measured in bytes and is 4096. Table 5-8 lists the FIFO flag status.

Table 5-8. Data FIFO Flag Status

TrueTrueFalseFIFO size (4096)

False

True

False

Threshold to (FIFO size - 1)

FalseFalseFalse1 to (Threshold - 1)

False

True

Full

Almost Full

Empty

Data bytes in FIFO

5.2.2 Scan List Queue Register (base + 1)

The Scan List Queue Register is considered the access port to the scan list queue which can

hold up to 2048 entries (each has two bytes). Each entry specifies an analog input channel and

it’s associated gain as well as other settings.

Note: Although the scan list queue register is 8 bits wide, it is required that the

significant byte) should always be accessed first, followed by the high byte (MSB or the most

significant byte). The bit definition is explained in Table 5-9.

Table 5-9. Scan List Queue Entry Bit Definition

0000..1111 : channel 0..7

External channel selection

LSB

3-0

00/01/10/11 : 1/2/4/8External gain selectionLSB5-4

for expansion cards (SSH)ReservedLSB6

Set to ‘1’ for the 1st entry in the

list

Starting channel mark

LSB

0000..1111 : channel 0..7

Internal channel selection

MSB

10-8

don’t care

Not in use

MSB

00/01/10/11 : 1/2/4/8Internal gain selectionMSB13-12

1/0 : differential/single-endedAnalog input modeMSB14

as 0

Reserved

MSB

ExplanationDefinitionByteBit

DAQP-208/208H/308 Users Manual 43