Cat.No.
C200HX/C200HG/C200HE Programmable Controllers Operation Manual Revised June 2000
Notice: OMRON products are manufactured for use according to proper procedures by a qualified operator and only for the purposes described in this manual. The following conventions are used to indicate and classify precautions in this manual. Always heed the information provided with them. Failure to heed precautions can result in injury to people or damage to property. DANGER Indicates an imminently hazardous situation which, if not avoided, will result in death or serious injury.
TABLE OF CONTENTS PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Safety Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TABLE OF CONTENTS 4-8 4-9 4-10 4-11 4-12 4-13 Controlling Bit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Work Bits (Internal Relays) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TABLE OF CONTENTS SECTION 8 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-2 8-3 8-4 8-5 8-6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Link Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RS-232C Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About this Manual: This manual describes the operation of the C200HX/HG/HE Programmable Controllers, and it includes the sections described below. Installation information is provided in the C200HX/HG/HE Programmable Controller Installation Guide. A table of other manuals that can be used in conjunction with this manual is provided in Section 1 Introduction.
PRECAUTIONS This section provides general precautions for using the Programmable Controller (PC) and related devices. The information contained in this section is important for the safe and reliable application of the PC. You must read this section and understand the information contained before attempting to set up or operate a PC system. 1 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Precautions . . . . .
Safety Precautions 1 3 Intended Audience This manual is intended for the following personnel, who must also have knowledge of electrical systems (an electrical engineer or the equivalent). • Personnel in charge of installing FA systems. • Personnel in charge of designing FA systems. • Personnel in charge of managing FA systems and facilities. 2 General Precautions The user must operate the product according to the performance specifications described in the operation manuals.
Application Precautions 5 such problems, external safety measures must be provided to ensure safety in the system. • When the 24-VDC output (service power supply to the PC) is overloaded or short-circuited, the voltage may drop and result in the outputs being turned OFF. As a countermeasure for such problems, external safety measures must be provided to ensure safety in the system. 4 ! Caution Execute online edit only after confirming that no adverse effects will be caused by extending the cycle time.
Application Precautions 5 • Connecting or disconnecting any cables or wiring. ! Caution Failure to abide by the following precautions could lead to faulty operation of the PC or the system or could damage the PC or PC Units. Always heed these precautions. • Use the Units only with the power supplies and voltages specified in the operation manuals. Other power supplies and voltages may damage the Units. • Take measures to stabilize the power supply to conform to the rated supply if it is not stable.
Conformance to EC Directives 6 6 Conformance to EC Directives Observe the following precautions when installing the C200HX/HG/HE PCs that conform to the EC Directives. Provide reinforced insulation or double insulation for the DC power source connected to the DC I/O Unit and for the Power Supply Unit. Use a separate power source for the DC I/O Unit from the external power supply for the Relay Output Unit.
SECTION 1 Introduction This section gives a brief overview of the history of Programmable Controllers and explains terms commonly used in ladderdiagram programming. It also provides an overview of the process of programming and operating a PC and explains basic terminology used with OMRON PCs.
Section 1-2 The Origins of PC Logic 1-1 Overview A PC (Programmable Controller) is basically a CPU (Central Processing Unit) containing a program and connected to input and output (I/O) devices. The program controls the PC so that when an input signal from an input device turns ON, the appropriate response is made. The response normally involves turning ON an output signal to some sort of output device.
Section 1-3 PC Terminology Actually there is not a total equivalence between these terms. The term condition is only used to describe ladder diagram programs in general and is specifically equivalent to one of a certain set of basic instructions. The terms input and output are not used in programming per se, except in reference to I/O bits that are assigned to input and output signals coming into and leaving the PC.
Section 1-5 Overview of PC Operation 1-4 OMRON Product Terminology OMRON products are divided into several functional groups that have generic names. Appendix A Standard Models list products according to these groups. The term Unit is used to refer to all of the OMRON PC products. Although a Unit is any one of the building blocks that goes together to form a C200HX/HG/HE PC, its meaning is generally, but not always, limited in context to refer to the Units that are mounted to a Rack.
Section 1-6 Peripheral Devices 7. Wire the PC to the controlled system. This step can actually be started as soon as step 3 has been completed. Refer to the C200HX/HG/HE PC Installation Guide and to Operation Manuals and System Manuals for details on individual Units. 8. Test the program in an actual control situation and carry out fine tuning as required. (Section 7 Program Monitoring and Execution and Section 9 Troubleshooting) 9.
Section 1-7 Available Manuals PC programs can be written on-screen in ladder-diagram form as well as in mnemonic form. As the program is written, it is displayed on a display, making confirmation and modification quick and easy. Syntax checks may also be performed on the programs before they are downloaded to the PC. The SSS comes on 3.5” disks. A computer running the SSS is connected to the C200HX/HG/HE PC via the Peripheral Port on the CPU Unit using the CQM1-CIF02 or CV500-CIF01 cable.
Section 1-8 C200HX/HG/HE Features Name Cat. No. Contents PID Control Unit Operation Manual W241 Information on PID Control Unit Cam Positioner Unit Operation Manual W224 Information on Cam Positioner Unit 1-8 C200HX/HG/HE Features The C200HX/HG/HE CPU Units have a number of new features, but C200H and C200HS programs can be used in the new CPU Units.
Section 1-8 C200HX/HG/HE Features Function Capability C200HX/HG/HE CPU Unit functions RS-232C port Available in the C200HX/HG/HE-CPU4 -E/6 -E Clock function SYSMAC NET Link and SYSMAC LINK functions Available in all except the C200HE-CPU11-E Communications Boards can be installed in all PCs except the C200HE-CPU11-E. (Board model numbers: C200HW-COM01/04-E) Communications Boards can be installed in all PCs except the C200HE-CPU11-E.
C200HX/HG/HE Features Section 1-8 • If the C200H program accesses the C200H’s error log in DM 0969 to DM 0999, the addresses of the words being accessed must be changed to DM 6000 to DM 6030, which is the error log area for the C200HX/HG/HE. • Any programs that rely on the execution cycle time (i.e., on the time required to execute any one part of all of the program) must be adjusted when used on the C200HX/HG/HE, which provides a much faster cycle time. Using Internal Memory 1, 2, 3...
C200HX/HG/HE Features Section 1-8 2. Go offline if the SSS is not already offline. 3. Change the PC setting for the SSS to the C200HX/HG/HE. 4. If you want to transfer I/O comments together with the program to the C200HX/HG/HE, allocate UM area for I/O comments. 5. Allocate expansion DM words DM 7000 to DM 7999 in the UM area using the UM allocation operation from the SSS. 6. Copy DM 1000 through DM 1999 to DM 7000 through DM 7999. 7.
SECTION 2 Hardware Considerations This section provides information on hardware aspects of the C200HX/HG/HE that are relevant to programming and software operation. These include CPU Unit Components, the basic PC configuration, CPU Unit capabilities, and Memory Cassettes. This information is covered in detail in the C200HX/HG/HE Installation Guide. 2-1 2-2 2-3 2-4 2-5 2-6 CPU Unit Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 2-1 CPU Unit Components 2-1 CPU Unit Components The following diagram shows the main CPU Unit components. Indicators Memory Cassette DIP switch Communications Board (The C200HW-COM06-E is mounted to this CPU Unit.) Peripheral port RS-232C port Memory Cassette Peripheral Port RS-232C Port Communications Board 6 5 4 3 2 1 DIP Switch The CPU Unit has a compartment to connect the Memory Cassette to the CPU Unit.
Section 2-1 CPU Unit Components 2-1-1 CPU Unit Indicators CPU Unit indicators provide visual information on the general operation of the PC. Although not substitutes for proper error programming using the flags and other error indicators provided in the data areas of memory, these indicators provide ready confirmation of proper operation. Indicator Meaning RUN (green) Lit when the PC is operating normally. ERR (red) Flashes if the PC detects any non-fatal error in operation.
Section 2-1 CPU Unit Components IBM PC/AT with SSS An IBM PC/AT or compatible computer with SYSMAC Support Software can be connected as shown in the diagram.
Section 2-3 CPU Unit Capabilities 2-2 PC Configuration The basic PC configuration consists of two types of Rack: a CPU Rack and Expansion I/O Racks. The Expansion I/O Racks are not a required part of the basic system. They are used to increase the number of I/O points. An illustration of these Racks is provided in 3-3 IR Area. A third type of Rack, called a Slave Rack, can be used when the PC is provided with a Remote I/O System.
Section 2-4 Memory Cassettes 2-4 Memory Cassettes The C200HX/HG/HE comes equipped with a built-in RAM for the user’s program, so a normal program be created even without installing a Memory Cassette. An optional Memory Cassette can be used to store the program, PC Setup, I/O comments, DM area and other data area contents. Refer to the C200HX/ HG/HE Installation Guide for details on installing Memory Cassettes.
Section 2-4 Memory Cassettes 2-4-1 Hardware and Software Settings The hardware and software settings related to Memory Cassette operations are described below. Switch Settings Switch 1 on the Memory Cassette is turned OFF when the Memory Cassette is shipped. Check the setting on switch 1 before installation. Memory Cassette EEPROM EPROM Switch 1 setting ON OFF ON OFF SR Area Flags and Control Bits Function The data in the Memory Cassette is write-protected.
Section 2-4 Memory Cassettes Comparing UM Data on a Memory Cassette 1, 2, 3... Use the following procedure to the UM data on an Memory Cassette to the UM data in the PC. 1. Switch the C200HX/HG/HE to PROGRAM mode. 2. Use a host computer running SSS or a Programming Console to turn ON SR 27002 (the Compare UM to Cassette Bit). The data will be compared between the PC and the Memory Cassette. SR 27002 will be turned OFF automatically after the data comparison has been completed. 3.
Section 2-4 Memory Cassettes 2. Turn ON the C200HX/HG/HE and switch it to PROGRAM mode. 3. Use a host computer running SSS or a Programming Console to turn ON SR 27300 (the Save IOM to Cassette Bit). The data will be written from the PC to the Memory Cassette. SR 27300 will be turned OFF automatically after the data transfer has been completed. 4. If you want to write-protect the data on the Memory Cassette, turn OFF the PC and set switch 1 of the Memory Cassette to ON.
Section 2-5 CPU Unit DIP Switch 2-5 CPU Unit DIP Switch The 6 pins on the DIP switch control 6 of the CPU Unit’s operating parameters. Pin 1 Item Memory protect Setting ON OFF ON 2 Automatic transfer of Memory Cassette contents 3 Message language OFF ON OFF 4 Expansion instruction setting ON 5 Communications parameters OFF ON Function The UM area1 cannot be overwritten from a Peripheral Device. The UM area1 can be overwritten from a Peripheral Device.
Section 2-6 Operating without a Backup Battery 2-6 Operating without a Backup Battery An EEPROM or EPROM Memory Cassette can be used together with various memory settings to enable operation without a backup battery. The following conditions must be met. 1, 2, 3... 1. The user program must be written to an EPROM or EEPROM Memory Cassette. 2. The clock cannot be used. (A battery is required to run the internal clock.) 3. The PC Setup must be set to not detect low battery voltage. 4.
Section 2-6 Operating without a Backup Battery EPROM Memory Cassette 1, 2, 3... 1. Allocate UM area using the SYSMAC Support Software (SSS) if you want to use Expansion DM for Special I/O Units or if you want to store I/O comments in the PC. 2. Write and transfer the user program, including a line using the Always OFF Flag (SR 25314) to ensure that the Output OFF Bit (SR 25215) remains OFF. 25314 (Always OFF Flag) 25215 3.
SECTION 3 Memory Areas Various types of data are required to achieve effective and correct control. To facilitate managing this data, the PC is provided with various memory areas for data, each of which performs a different function. The areas generally accessible by the user for use in programming are classified as data areas. The other memory area is the UM Area, where the user’s program is actually stored.
Section 3-1 Introduction 3-1 Introduction 3-1-1 Data Area Overview Details, including the name, size, and range of each area are summarized in the following table. Data and memory areas are normally referred to by their acronyms, e.g., the IR Area, the SR Area, etc.
Section 3-2 Data Area Structure some flags can be turned ON and OFF by the user, most flags are read only; they cannot be controlled directly. Control bits are bits turned ON and OFF by the user to control specific aspects of operation. Any bit given a name using the word bit rather than the word flag is a control bit, e.g., Restart bits are control bits. 3-1-2 IR/SR Area Overview When designating a data area, the acronym for the area is always required for any area except the IR and SR areas.
Section 3-2 Data Area Structure An actual data location within any data area but the TC area is designated by its address. The address designates the bit or word within the area where the desired data is located. The TC area consists of TC numbers, each of which is used for a specific timer or counter defined in the program. Refer to 3-8 TC Area for more details on TC numbers and to 5-14 Timer and Counter Instructions for information on their application. The rest of the data areas (i.e.
Section 3-2 Data Area Structure When inputting data into data areas, it must be input in the proper form for the intended purpose. This is no problem when designating individual bits, which are merely turned ON (equivalent to a binary value of 1) or OFF (a binary value of 0). When inputting word data, however, it is important to input it either as decimal or as hexadecimal, depending on what is called for by the instruction it is to be used for.
Section 3-2 Data Area Structure Signed Binary Signed binary data can have either a positive and negative value. The sign is indicated by the status of bit 15. If bit 15 is OFF, the number is positive and if bit 15 is ON, the number is negative. Positive signed binary values range from 0 ($0000) to 32,767 ($7FFF), and negative signed binary values range from –32,768 ($8000) to –1 ($FFFF).
Section 3-3 IR (Internal Relay) Area 1. First take the absolute value (12345) and convert to unsigned binary: Bit number Contents 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 1 2. Next take the complement: Bit number Contents 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 1 1 0 0 1 1 1 1 1 1 0 0 0 1 1 0 3.
Section 3-3 IR (Internal Relay) Area instructions that control bit status, e.g., the OUTPUT, DIFFERENTIATION UP, and KEEP instructions. Output Bit Usage Output bits are used to output program execution results and can be used in any order in programming. Because outputs are refreshed only once during each cycle (i.e., once each time the program is executed), any output bit can be used in only one instruction that controls its status, including OUT, KEEP(11), DIFU(13), DIFD(14) and SFT(10).
Section 3-3 IR (Internal Relay) Area Unit number A B C D E F I/O words IR 400 to IR 409 IR 410 to IR 419 IR 420 to IR 429 IR 430 to IR 439 IR 440 to IR 449 IR 450 to IR 459 PC Restrictions Not available in C200HE-CPU -E and C200HG/HX-CPU3 -E/4 -E PCs. Note I/O words that aren’t allocated to Special I/O Units can be used as work words. Up to five Slave Racks may be used, whether one or two Masters are used.
IR (Internal Relay) Area Section 3-3 Allocation for Group-2 High-density I/O Units and B7 Interface Units Group-2 High-density I/O Units and B7A Interface Units are allocated words between IR 030 and IR 049 according to I/O number settings made on them and do not use the words allocated to the slots in which they are mounted. For 32-point Units, each Unit is allocated two words; for 64-point Units, each Unit is allocated four words. The words allocated for each I/O number are in the following tables.
Section 3-4 SR (Special Relay) Area 3-4 SR (Special Relay) Area The SR area contains flags and control bits used for monitoring PC operation, accessing clock pulses, and signalling errors. SR area word addresses range from 236 through 299; bit addresses, from 23600 through 29915. The SR areas is divided into two sections. The first section ends at SR 255 and the second section begins at SR 256. When an SR area word is used as an operand in an instruction, the operand mustn’t cross over this boundary.
SR (Special Relay) Area Word(s) 252 Bit(s) 00 01 02 03 04 253 254 34 05 06 07 08 09 10 11 12 13 14 15 00 to 07 08 09 10 11 12 13 14 15 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Section 3-4 Function SEND(90)/RECV(98) Error Flag for operating level 0 of SYSMAC LINK or SYSMAC NET Link System or CMCR(––) Error Flag for PC Card SEND(90)/RECV(98) Enable Flag for operating level 0 of SYSMAC LINK or SYSMAC NET Link System or CMCR(––) Enable Flag for PC Card Operating Level 0 Data Link Operating Flag SE
Section 3-4 SR (Special Relay) Area Word(s) 255 256 to 261 262 263 Bit(s) 00 01 02 03 04 05 06 07 08 to 15 00 to 15 00 to 15 00 to 15 264 00 to 03 Function 0.1-second clock pulse bit 0.2-second clock pulse bit 1.0-second clock pulse bit Instruction Execution Error (ER) Flag These flags are turned OFF when the END(01) instruction is executed, so their status can’t be Carry (CY) Flag monitored from a Programming Console.
Section 3-4 SR (Special Relay) Area Word(s) 270 Bit(s) 00 Save UM to Cassette Bit 01 Load UM from Cassette Bit 02 03 Compare UM to Cassette Bit Comparison Results 0: Contents identical; 1: Contents differ or comparison not possible Reserved by system (not accessible by user) Transfer Error Flag: Transferring Data will not be transferred from UM to the Memory SYSMAC NET data link table on UM Cassette if an error occurs (except for Board during active data link. Checksum Error).
Section 3-4 SR (Special Relay) Area Word(s) 274 Bit(s) 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Function These flags will turn ON during restart processing. These flags will not turn ON for Units on Slave Racks.
Section 3-4 SR (Special Relay) Area 3-4-1 SYSMAC NET/SYSMAC LINK System Loop Status SR 236 provides the local node loop status for SYSMAC NET Systems, as shown below.
Section 3-4 SR (Special Relay) Area Data Link Status Flags SR 238 to SR 245 contain the data link status for SYSMAC LINK/SYSMAC NET Systems. The data structure depends on the system used to create the data link.
Section 3-4 SR (Special Relay) Area 3-4-3 Link System Flags and Control Bits Use of the following SR bits depends on the configuration of any Link Systems to which your PC belongs. These flags and control bits are used when Link Units, such as PC Link Units, Remote I/O Units, or Host Link Units, are mounted to the PC Racks or to the CPU Unit. For additional information, consult the System Manual for the particular Units involved.
Section 3-4 SR (Special Relay) Area Multilevel PC Link Systems Flag type Run flags Bit no.
SR (Special Relay) Area Section 3-4 Maintaining Status during Startup The status of SR 25211 and thus the status of force-set and force-reset bits can be maintained when power is turned OFF and ON by enabling the Forced Status Hold Bit in the PC Setup. If the Forced Status Hold Bit is enabled, the status of SR 25211 will be preserved when power is turned OFF and ON.
Section 3-4 SR (Special Relay) Area This bit can be programmed to activate an external warning for a low battery voltage. The operation of the battery alarm can be disabled in the PC Setup if desired. Refer to 3-6-4 PC Setup for details. 3-4-9 Cycle Time Error Flag SR bit 25309 turns ON if the cycle time exceeds 100 ms. The ALM/ERR indicator on the front of the CPU Unit will also flash. Program execution will not stop, however, unless the maximum time limit set for the watchdog timer is exceeded.
Section 3-4 SR (Special Relay) Area 3-4-13 Step Flag SR bit 25407 turns ON for one cycle when step execution is started with the STEP(08) instruction. 3-4-14 Group-2 Error Flag SR bit 25414 turns ON for any of the following errors for Group-2 High-density I/O Units and B7A Interface Units: the same I/O number set twice, the same words allocated to more than one Unit, refresh errors.
Section 3-4 SR (Special Relay) Area Negative Flag, N SR bit 25402 turns ON when the result of a calculation is negative. Overflow Flag, OF SR bit 25404 turns ON when the result of a binary addition or subtraction exceeds 7FFF or 7FFFFFFF. Underflow Flag, UF SR bit 25405 turns ON when the result of a signed binary addition or subtraction exceeds 8000 or 80000000.
Section 3-4 SR (Special Relay) Area Host Link Level 0 Send Ready Flag SR bit 26705 turns ON when the PC is ready to transmit to the Host Link Unit. Host Link Level 1 Send Ready Flag SR bit 26713 turns ON when the PC is ready to transmit to the Host Link. 3-4-20 Peripheral Port Communications Areas Peripheral Port Error Code Error code SR bits 26408 to 26411 are set when there is a peripheral port error in the General I/O Mode.
Section 3-4 SR (Special Relay) Area Memory Cassette Flag SR bit 26915 turns ON when a Memory Cassette is mounted. Save UM to Cassette Flag SR bit 27000 turns ON when UM data is read to a Memory Cassette in Program Mode. Bit will automatically turn OFF. An error will be produced if turned ON in any other mode. Load UM from Cassette Flag SR bit 27001 turns ON when data is loaded into UM from a Memory Cassette in Program Mode. Bit will automatically turn OFF.
Section 3-5 AR (Auxiliary Relay) Area Memory Error Flag: Autoboot Error SR bit 27215 turns ON when an autoboot error occurs. 3-4-25 Data Save Flags Data transferred to Memory Cassette when Bit is turned ON in PROGRAM mode. Bit will automatically turn OFF. An error will be produced if turned ON in any other mode. Save IOM to Cassette Bit SR bit 27300 turns ON when IOM is saved to a Memory Cassette. Load IOM from Cassette Bit SR bit 27301 turns ON when loading to IOM from a Memory Cassette.
Section 3-5 AR (Auxiliary Relay) Area uses, such as transmission counters, flags, and control bits, and words AR 00 through AR 07 and AR 23 through AR 27 cannot be used for any other purpose. Words and bits from AR 08 to AR 17 are available as work words and work bits if not used for the following assigned purposes.
Section 3-5 AR (Auxiliary Relay) Area Word(s) 19 Bit(s) Function 21 00 to 07 08 to 15 00 to 07 08 to 15 00 to 07 22 08 to 12 13 14 15 00 to 15 Hours: 00 to 23 (24-hour system) Day of Month: 01 to 31 (adjusted by month and for leap year) Month: 1 to 12 Year: 00 to 99 (Rightmost two digits of year) Day of Week: 00 to 06 (00: Sunday; 01: Monday; 02: Tuesday; 03: Wednesday; 04: Thursday; 05: Friday; 06: Saturday) Not used.
Section 3-5 AR (Auxiliary Relay) Area 3-5-2 Slave Rack Error Flags AR bits 0200 to AR 0204 correspond to the unit numbers of Remote I/O Slave Units #0 to #4. These flags will turn ON if the same number is allocated to more then one Slave or if a transmission error occurs when starting the System. Refer to SR 251 for errors that occur after the System has started normally.
Section 3-5 AR (Auxiliary Relay) Area 3-5-5 SYSMAC LINK System Data Link Settings AR 0700 to AR 0703 and AR 0704 to AR 0707 are used to designate word allocations for operating levels 0 and 1 of the SYSMAC LINK System. Allocation can be set to occur either according to settings from the SSS or automatically in the LR and/or DM areas. If automatic allocation is designated, the number of words to be allocated to each node is also designated. These settings are shown below.
Section 3-5 AR (Auxiliary Relay) Area 3-5-8 SYSMAC LINK/SYSMAC NET Link System Service Time AR 16 provides the time allocated to servicing operating level 0 of the SYSMAC LINK System and/or SYSMAC NET Link System during each cycle when a SYSMAC LINK Unit and/or SYSMAC NET Link Unit is mounted to a Rack.
Section 3-5 AR (Auxiliary Relay) Area 3-5-10 TERMINAL Mode Key Bits If the Programming Console is mounted to the PC and is in TERMINAL mode, any inputs on keys 0 through 9 (including characters A through F, i.e., keys 0 through 5 with SHIFT) will turn on a corresponding bit in AR 22. TERMINAL mode is entered by a Programming Console operation.
Section 3-5 AR (Auxiliary Relay) Area 3-5-13 Cycle Time Flag AR 2405 turns ON when the cycle time set with SCAN(18) is shorter than the actual cycle time. AR 2405 is refreshed every cycle while the PC is in RUN or MONITOR mode. 3-5-14 Link Unit Mounted Flags The following flags indicate when the specified Link Units are mounted to the Racks. (Refer to 3-5-15 CPU Unit-mounting Device Mounted Flag for CPU Unitmounting Host Link Units.) These flags are refreshed every cycle.
Section 3-6 DM (Data Memory) Area 3-6 DM (Data Memory) Area The DM area is divided into various parts as described in the following table. A portion of UM (up to 3,000 words in 1,000-word increments) can be allocated as Expansion DM. Addresses DM 0000 to DM 0999 DM 1000 to DM 2599 DM 2600 to DM 5999 DM 6000 to DM 6030 DM 6100 to DM 6143 DM 6144 to DM 6599 DM 6600 to DM 6655 DM 7000 to DM 9999 Note User read/write Read/Write Read only Usage Normal DM. Special I/O Unit Area1 Normal DM.
Section 3-6 DM (Data Memory) Area be used as the operand in the instruction, and the content of DM 0324 will be moved to LR 00. MOV(21) DM 0100 LR 00 Indirect address Word DM 0099 DM 0100 DM 0101 Content 4C59 0324 F35A DM 0324 DM 0325 DM 0326 5555 2506 D541 Indicates DM 0324 5555 moved to LR 00. 3-6-1 Expansion DM Area The expansion DM area is designed to provide memory space for storing operating parameters and other operating data for Link Units and Special I/O Units.
Section 3-6 DM (Data Memory) Area 3-6-2 Special I/O Unit Data Special I/O Units are allocated 1000 or 1600 words in the DM Area depending on the value set in word DM 6602 of the PC Setup. The DM 6602 setting determines whether the Special I/O Unit Data area is setup for 10 or 16 Units and whether the data is stored in read/write DM (DM 1000 to DM 2599) or read-only DM (DM 7000 to DM 8599). Refer to Appendix E for details.
Section 3-6 DM (Data Memory) Area Although each of them contains a different record, the structure of each record is the same: the first word contains the error code; the second and third words, the day and time. The error code will be either one generated by the system or by FAL(06)/FALS(07); the time and date will be the date and time from AR 18 and AR 19 (Calender/date Area). Also recorded with the error code is an indication of whether the error is fatal (08) or non-fatal (00).
Section 3-6 DM (Data Memory) Area The Error History Area can be reset by turning ON and then OFF AR 0714 (Error History Reset Bit). When this is done, the Record Pointer will be reset to 0000, the Error History Area will be reset (i.e., cleared), and any further error codes will be recorded from the beginning of the Error History Area. AR 0715 (Error History Enable Bit) must be ON to reset the Error History Area.
Section 3-6 DM (Data Memory) Area Word(s) DM 6602 Bit(s) 00 to 07 08 to 15 Function Not used. 00: C200H-compatible RAM Mode (Default) Use DM 1000 through DM 2599 for the initial data area for the Special I/O Unit Area. • Data in the Special I/O Unit Area can be read/written. Default --DM 1000 to DM 2599 • The data cannot be converted to ROM. 01: C200H-compatible ROM Mode 1 Transfer the contents of DM 7000 through DM 7999 to DM 1000 through DM 1999 at startup and use DM 1000 through DM 1999.
DM (Data Memory) Area Word(s) DM 6614 Bit(s) 00 to 07 08 to 15 Function Servicing time for Communications Board port A (effective when bits 08 to 15 are set to 01) 00 to 99 (BCD): Percentage of cycle time used to service port A. Section 3-6 Default No setting (0000) Minimum: 0.26 ms; maximum 58.254 ms Communications Board port A servicing setting enable 00: Do not set service time (Fixed at 5%, 0.26 ms min.) 01: Use time in 00 to 07.
Section 3-6 DM (Data Memory) Area Word(s) DM 6621 Bit(s) 00 to 07 08 to 15 Function Default Reserved Special I/O Unit refresh (PC Link Units included) 00: Enable refresh for all Special I/O Units 01: Disable refresh for all Special I/O Units (but, not valid on Slave Racks) --Enable A setting of 1 (Disable) is not valid for Special I/O Units mounted in Slave Racks.
Section 3-6 DM (Data Memory) Area Word(s) DM 6648 Bit(s) 00 to 07 08 to 11 12 to 15 DM 6649 00 to 07 08 to 15 Function Node number (Host Link) 00 to 31 (BCD) Start code enable (RS-232C) 0: Disable; 1: Set End code enable (RS-232C) 0: Disable (number of bytes received) 1: Set (specified end code) 2: CR, LF Start code (RS-232C) 00 to FF (binary) 12 to 15 of DM 6648 set to 0: Number of bytes received 00: Default setting (256 bytes) 01 to FF: 1 to 255 bytes Default 0 Disabled Disabled Not used (0000) 12
Section 3-6 DM (Data Memory) Area Word(s) DM 6654 Bit(s) 00 to 07 08 to 15 Function Default 0000 Start code (RS-232C) 00 to FF (binary) 12 to 15 of DM 6653 set to 0: Number of bytes received 00: Default setting (256 bytes) 01 to FF: 1 to 255 bytes 12 to 15 of DM 6653 set to 1: End code (RS-232C) 00 to FF (binary) Error Settings (DM 6655) The following settings are accessed continually while the PC is ON.
Section 3-6 DM (Data Memory) Area Word(s) DM 6551 Bit(s) 00 to 07 08 to 15 DM 6552 00 to 15 DM 6553 00 to 07 08 to 11 12 to 15 DM 6554 00 to 07 08 to 15 Function Baud rate 00: 1.2K, 01: 2.4K, 02: 4.8K, 03: 9.6K, 04: 19.
Section 3-6 DM (Data Memory) Area Word(s) DM 6556 Bit(s) 00 to 07 08 to 15 DM 6557 00 to 15 DM 6558 00 to 07 08 to 11 12 to 15 DM 6559 00 to 07 08 to 15 Function Baud rate 00: 1.2K, 01: 2.4K, 02: 4.8K, 03: 9.6K, 04: 19.
Section 3-8 TC (Timer/Counter) Area Setting Mode Function 11 C200H-compatible The contents of DM 7000 through DM 8599 are transferred to DM 1000 through DM 2599 ROM Mode 2 at startup and DM 1000 through DM 2599 are used for the Special I/O Unit Area. • The UM Area Allocation operation must be performed beforehand. • ROM conversion is possible indirectly by converting DM 7000 through DM 8599 to ROM. 12 DM Linear Mode 2 DM 7000 through DM 8599 are used for the Special I/O Unit Area.
Section 3-9 LR Area Once defined, a TC number can be designated as an operand in one or more of certain set of instructions other than those listed above. When defined as a timer, a TC number designated as an operand takes a TIM prefix. The TIM prefix is used regardless of the timer instruction that was used to define the timer. Once defined as a counter, the TC number designated as an operand takes a CNT prefix.
Section 3-10 UM Area 3-10 UM Area With the C200HX/HG/HE PCs, the UM area contains the ladder program. Part of the UM area can be allocated for use as expansion DM or the I/O comment area. The usable size of the UM area ranges from 3.2 KW in the C200HE-CPU11-E to 31.2 KW in the C200HX-CPU 4-E. A Programming Console or SYSMAC Support Software (SSS) can be used to allocate expansion DM, but the I/O comment area can be allocated with SSS only.
Section 3-12 EM (Extended Data Memory) Area 3-11 TR (Temporary Relay) Area The TR area provides eight bits that are used only with the LD and OUT instructions to enable certain types of branching ladder diagram programming. The use of TR bits is described in Section 4 Writing and Inputting the Program. TR addresses range from TR 0 though TR 7. Each of these bits can be used as many times as required and in any order required as long as the same LR bit is not used twice in the same instruction block.
Section 3-12 EM (Extended Data Memory) Area access words in EM bank 1 and not the DM area. In this case, the second operand in the MOV(21) instruction transfers #1234 to a word in the EM bank. (For example, #1234 will be moved to EM 0100 if DM 0000 contains 0100.) Later in the program, the destination for indirect addressing ( DM) is switched back to the DM area by executing IEMS(––) with an operand of 000. IEMS #E0B1 MOV #1234 ∗D0000 IEMS 000 Note 1.
SECTION 4 Writing and Inputting the Program This section explains the basic steps and concepts involved in writing a basic ladder diagram program, inputting the program into memory, and executing it. It introduces the instructions that are used to build the basic structure of the ladder diagram and control its execution. The entire set of instructions used in programming is described in Section 5 Instruction Set. 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 Basic Procedure . . . . . . . .
Section 4-2 Instruction Terminology 4-1 Basic Procedure There are several basic steps involved in writing a program. Sheets that can be copied to aid in programming are provided in Appendix F Word Assignment Recording Sheets and Appendix G Program Coding Sheet. 1, 2, 3... 4-2 1. Obtain a list of all I/O devices and the I/O points that have been assigned to them and prepare a table that shows the I/O bit allocated to each I/O device. 2.
Section 4-4 Basic Ladder Diagrams 4-3 Program Capacity The maximum user program size varies with the amount of UM allocated to expansion DM and the I/O Comment Area. Approximately 10.1 KW are available for the ladder program when 3 KW are allocated to expansion DM and 2 KW are allocated to I/O comments as shown below. Refer to the 3-10 UM Area for further information on UM allocation.
Section 4-4 Basic Ladder Diagrams 4-4-1 Basic Terms Normally Open and Normally Closed Conditions Each condition in a ladder diagram is either ON or OFF depending on the status of the operand bit that has been assigned to it. A normally open condition is ON if the operand bit is ON; OFF if the operand bit is OFF. A normally closed condition is ON if the operand bit is OFF; OFF if the operand bit is ON.
Section 4-4 Basic Ladder Diagrams Program Memory addresses start at 00000 and run until the capacity of Program Memory has been exhausted. The first word at each address defines the instruction. Any definers used by the instruction are also contained in the first word. Also, if an instruction requires only a single bit operand (with no definer), the bit operand is also programmed on the same line as the instruction.
Section 4-4 Basic Ladder Diagrams LOAD and LOAD NOT The first condition that starts any logic block within a ladder diagram corresponds to a LOAD or LOAD NOT instruction. Each of these instruction requires one line of mnemonic code. “Instruction” is used as a dummy instruction in the following examples and could be any of the right-hand instructions described later in this manual. 00000 A LOAD instruction.
Section 4-4 Basic Ladder Diagrams OR and OR NOT When two or more conditions lie on separate instruction lines which run in parallel and then join together, the first condition corresponds to a LOAD or LOAD NOT instruction; the other conditions correspond to OR or OR NOT instructions. The following example shows three conditions which correspond (in order from the top) to a LOAD NOT, an OR NOT, and an OR instruction. Again, each of these instructions requires one line of mnemonic code.
Section 4-4 Basic Ladder Diagrams 4-4-4 OUTPUT and OUTPUT NOT The simplest way to output the results of combining execution conditions is to output it directly with the OUTPUT and OUTPUT NOT. These instructions are used to control the status of the designated operand bit according to the execution condition. With the OUTPUT instruction, the operand bit will be turned ON as long as the execution condition is ON and will be turned OFF as long as the execution condition is OFF.
Section 4-4 Basic Ladder Diagrams Now you have all of the instructions required to write simple input-output programs. Before we finish with ladder diagram basic and go onto inputting the program into the PC, let’s look at logic block instruction (AND LOAD and OR LOAD), which are sometimes necessary even with simple diagrams. 4-4-6 Logic Block Instructions Logic block instructions do not correspond to specific conditions on the ladder diagram; rather, they describe relationships between logic blocks.
Section 4-4 Basic Ladder Diagrams Analyzing the above ladder diagram in terms of mnemonic instructions, the condition for IR 00000 is a LOAD instruction and the condition below it is an OR instruction between the status of IR 00000 and that of IR 00001. The condition at IR 00002 is another LOAD instruction and the condition below is an OR NOT instruction, i.e., an OR between the status of IR 00002 and the inverse of the status of IR 00003.
Section 4-4 Basic Ladder Diagrams The following diagram requires AND LOAD to be converted to mnemonic code because three pairs of parallel conditions lie in series. The two options for coding the programs are also shown.
Section 4-4 Basic Ladder Diagrams Combining AND LOAD and OR LOAD Both of the coding methods described above can also be used when using AND LOAD and OR LOAD, as long as the number of blocks being combined does not exceed eight. The following diagram contains only two logic blocks as shown. It is not necessary to further separate block b components, because it can be coded directly using only AND and OR.
Section 4-4 Basic Ladder Diagrams Complicated Diagrams When determining what logic block instructions will be required to code a diagram, it is sometimes necessary to break the diagram into large blocks and then continue breaking the large blocks down until logic blocks that can be coded without logic block instructions have been formed. These blocks are then coded, combining the small blocks first, and then combining the larger blocks. Either AND LOAD or OR LOAD is used to combine the blocks, i.e.
Section 4-4 Basic Ladder Diagrams The following diagram requires an OR LOAD followed by an AND LOAD to code the top of the three blocks, and then two more OR LOADs to complete the mnemonic code.
Section 4-4 Basic Ladder Diagrams Again, this diagram can be redrawn as follows to simplify program structure and coding and to save memory space.
Section 4-5 The Programming Console 4-4-7 Coding Multiple Right-hand Instructions If there is more than one right-hand instruction executed with the same execution condition, they are coded consecutively following the last condition on the instruction line. In the following example, the last instruction line contains one more condition that corresponds to an AND with IR 00004.
The Programming Console Section 4-5 Yellow: Operation Keys The yellow keys are used for writing and correcting programs. Detailed explanations of their functions are given later in this section. Gray: Instruction and Data Area Keys Except for the SHIFT key on the upper right, the gray keys are used to input instructions and designate data area prefixes when inputting or changing a program.
Section 4-5 The Programming Console The gray keys other than the SHIFT key have either the mnemonic name of the instruction or the abbreviation of the data area written on them. The functions of these keys are described below. Pressed before the function code when inputting an instruction via its function code. Pressed to enter SFT (the Shift Register instruction).
Section 4-6 Preparation for Operation 4-5-2 PC Modes The Programming Console is equipped with a switch to control the PC mode. To select one of the three operating modes—RUN, MONITOR, or PROGRAM— use the mode switch. The mode that you select will determine PC operation as well as the procedures that are possible from the Programming Console. RUN mode is the mode used for normal program execution.
Section 4-6 Preparation for Operation 4. Confirm that the CPU Unit’s POWER LED is lit and the following display appears on the Programming Console screen. (If the PC mode is not displayed, turn OFF and restart the power supply. If the ALM/ERR LED is lit or flashing or an error message is displayed, clear the error that has occurred.) PASSWORD! 5. Enter the password. See 4-6-1 Entering the Password for details. 6. Clear memory. Skip this step if the program does not need to be cleared.
Section 4-6 Preparation for Operation 4-6-3 Clearing Memory Using the Memory Clear operation it is possible to clear all or part of the UM area (RAM or EEPROM), and the IR, HR, AR, DM, EM and TC areas. Unless otherwise specified, the clear operation will clear all of the above memory areas. The UM area will not be cleared if the write-protect switch (pin 1 of the CPU Unit’s DIP switch) is set to ON.
Section 4-6 Preparation for Operation The following procedure is used to clear memory completely. MEMORY ERR I/O VER ERR Continue pressing the CLR key once for each error message until “00000” appears on the display 00000 00000 00000MEMORY CLR? HR CNT DM EM~ 00000MEM ALLCLR? All clear 00000MEM ALLCLR END Partial Clear It is possible to retain the data in specified areas or part of the ladder program.
Section 4-6 Preparation for Operation To leave the TC area uncleared and retain Program Memory addresses 00000 through 00122, input as follows: 00000 00000 00000 00000MEMORY CLR? HR CNT DM EM~ 00000MEMORY CLR? HR DM EM~ 00123MEMORY CLR? HR DM EM~ 00000MEMORY CLR END HR DM EM Clearing Selected EM Banks When a partial memory clear operation is being performed, specific banks can be selected for clearing rather than selecting the entire EM area.
Section 4-6 Preparation for Operation Memory Clear The memory clear operation clears all memory areas except the I/O comments and UM Allocation information. The Programming Console will display the following screens: 00000 00000 00000 00000MEMORY CLR? HR CNT DM EM~ 00000MEMORY CLR END Note When the write-protect switch (pin 1 of the CPU Unit’s DIP switch) is set to ON the UM area (from DM 6144 through the ladder program) will not be cleared.
Section 4-6 Preparation for Operation Initial I/O Table Registration 00000 00000 FUN (??) 00000IOTBL ?Ć?U= ? 00000IOTBL WRIT ???? 00000IOTBL WRIT 9713 00000IOTBL OK WRIT Register I/O table 4-6-5 Clearing Error Messages After the I/O table has been registered, any error messages recorded in memory should be cleared. It is assumed here that the causes of any of the errors for which error messages appear have already been taken care of.
Section 4-6 Preparation for Operation Example 00000 00000 FUN (??) 00000IOTBL ?Ć?U= ? 00000IOTBL OK CHK 00000IOTBL CHK 0Ć1U=O*** I*** (No errors) (A verification error occurred) Actual I/O words Registered I/O table words I/O slot number Rack number Meaning of Displays The following display indicates a C500, C1000H, or C2000H and C200H, C200HS, or C200HX/HG/HE have the same unit number on a Remote I/O Slave Rack.
Section 4-6 Preparation for Operation 4-6-7 Reading the I/O Table The I/O Table Read operation is used to access the I/O table that is currently registered in the CPU Unit memory. This operation can be performed in any PC mode. Key Sequence [0 to 3] [0 to 9] Rack number Unit number Press the EXT key to select Remote I/O Slave Racks or Optical I/O Units.
Section 4-6 Preparation for Operation Meaning of Displays I/O Unit Designations for Displays (see I/O Units Mounted in Remote Slave Racks, page 101) C500, 1000H/C2000H I/O Units No. of points Input Unit Output Unit O * * * 32 I * * * I I * * 64 I I I I O O O O 16 O O * * C200H, C200HS I/O Units No.
Section 4-6 Preparation for Operation Remote I/O Slave Racks 00000IOTBL READ R**Ć*U=**** *** I/O word number I/O type: I, O i, o (see tables on previous page) Unit number (0 to 9) Remote I/O Slave Unit number (0 to 4) Remote I/O Master Unit number (0 or 1) Indicates a Remote I/O Rack Group-2 HIgh-density I/O Units 00000IOTBL READ *Ć*U=#*** 2: 4: 2 words (32 points) 4 words (64 points) I: Input Unit O: Output Unit Unit number (0 to F) Indicates Group-2 HIgh-density I/O Unit Optical I/O Units and Remot
Section 4-6 Preparation for Operation Key Sequence Example 00000 00000 FUN (??) 00000IOTBL ?Ć?U= 00000IOTBL WRIT ???? 00000IOTBL CANC ???? 00000IOTBL CANC 9713 00000IOTBL OK CANC 4-6-9 SYSMAC NET Link Table Transfer The SYSMAC NET Link Table Transfer operation transfers a copy of the SYSMAC NET Link Data Link table to the UM Area program memory. This allows the user program and SYSMAC NET Link table to be written into EPROM together.
Section 4-6 Preparation for Operation Key Sequence Example 00000 00000 FUN(??) 00000LINK TBL~UM (SYSMACĆNET)???? 00000LINK TBL~UM (SYSMACĆNET)9713 00000LINK TBL~UM OK The following indicates that the I/O table cannot be transferred.
Inputting, Modifying, and Checking the Program 4-7 Section 4-7 Inputting, Modifying, and Checking the Program Once a program is written in mnemonic code, it can be input directly into the PC from a Programming Console. Mnemonic code is keyed into Program Memory addresses from the Programming Console. Checking the program involves a syntax check to see that the program has been written according to syntax rules.
Section 4-7 Inputting, Modifying, and Checking the Program Example If the following mnemonic code has already been input into Program Memory, the key inputs below would produce the displays shown.
Section 4-7 Inputting, Modifying, and Checking the Program Inputting SV for Counters and Timers The SV (set value) for a timer or counter is generally entered as a constant, although inputting the address of a word that holds the SV is also possible. When inputting an SV as a constant, CONT/# is not required; just input the numeric value and press WRITE. To designate a word, press CLR and then input the word address as described above.
Section 4-7 Inputting, Modifying, and Checking the Program Example The following program can be entered using the key inputs shown below. Displays will appear as indicated.
Section 4-7 Inputting, Modifying, and Checking the Program Error Messages The following error messages may appear when inputting a program. Correct the error as indicated and continue with the input operation. The asterisks in the displays shown below will be replaced with numeric data, normally an address, in the actual display. Message ****REPL ROM ****PROG OVER ****ADDR OVER ****SETDATA ERR ****I/O NO. ERR Cause and correction An attempt was made to write to write-protected RAM or EEPROM.
Inputting, Modifying, and Checking the Program Section 4-7 Many of the following errors are for instructions that have not yet been described yet. Refer to 4-8 Controlling Bit Status or to Section 5 Instruction Set for details on these. Type Type A Message ????? NO END INSTR CIRCUIT ERR LOCN ERR DUPL SBN UNDEFD JME UNDEFD OPERAND ERR STEP ERR Type B IL-ILC ERR JMP-JME ERR SBN-RET ERR Type C JMP UNDEFD SBS UNDEFD COIL DUPL Meaning and appropriate response The program has been lost.
Section 4-7 Inputting, Modifying, and Checking the Program Example The following example shows some of the displays that can appear as a result of a program check. 00000 00000PROG CHK CHKLVL (0Ć2)? 00064PROG CHK Display #1 Halts program check 00699CHK ABORTD Display #2 Check continues until END(01) 02000PROG CHK END (01)(02.
Inputting, Modifying, and Checking the Program Section 4-7 4-7-5 Program Searches The program can be searched for occurrences of any designated instruction or data area address used in an instruction. Searches can be performed from any currently displayed address or from a cleared display. To designate a bit address, press SHIFT, press CONT/#, then input the address, including any data area designation required, and press SRCH.
Section 4-7 Inputting, Modifying, and Checking the Program Example: Instruction Search 00000 00000 LD 00000 00200SRCH LD 00000 00202SRCH LD 00000 02000SRCH END (01)(02.7KW) 00000 00100 00100 TIM 001 00203SRCH TIM 001 00203 TIM DATA #0123 Example: Bit Search 00000 00000CNT CONT 00005 00200CONT SRCH LD 00005 00203CONT SRCH AND 00005 02000 END (01)(02.
Section 4-7 Inputting, Modifying, and Checking the Program To delete an instruction, display the instruction word of the instruction to be deleted and then press DEL and the up key. All the words for the designated instruction will be deleted. ! Caution Be careful not to inadvertently delete instructions; there is no way to recover them without re-inputting them completely.
Section 4-7 Inputting, Modifying, and Checking the Program Inserting an Instruction 00000 00000 OUT 00000 00000 OUT 00201 00207SRCH OUT 00201 00206READ AND NOT 00104 00206 AND 00000 00206 AND 00105 Find the address prior to the insertion point Program After Insertion Address Instruction 00000 00001 00002 00003 00004 00005 00006 00007 00008 00009 LD AND LD AND NOT OR LD AND AND AND NOT OUT END(01) Operands 00100 00101 00201 00102 –– 00103 00105 00104 00201 –– 00206INSERT? AND 00105 00207IN
Section 4-7 Inputting, Modifying, and Checking the Program 4-7-7 Branching Instruction Lines When an instruction line branches into two or more lines, it is sometimes necessary to use either interlocks or TR bits to maintain the execution condition that existed at a branching point. This is because instruction lines are executed across to a right-hand instruction before returning to the branching point to execute instructions on a branch line.
Section 4-7 Inputting, Modifying, and Checking the Program The previous diagram B can be written as shown below to ensure correct execution. In mnemonic code, the execution condition is stored at the branching point using the TR bit as the operand of the OUTPUT instruction.
Section 4-7 Inputting, Modifying, and Checking the Program When drawing a ladder diagram, be careful not to use TR bits unless necessary. Often the number of instructions required for a program can be reduced and ease of understanding a program increased by redrawing a diagram that would otherwise required TR bits. In both of the following pairs of diagrams, the bottom versions require fewer instructions and do not require TR bits.
Section 4-7 Inputting, Modifying, and Checking the Program When an INTERLOCK instruction is placed before a section of a ladder program, the execution condition for the INTERLOCK instruction will control the execution of all instruction up to the next INTERLOCK CLEAR instruction.
Section 4-7 Inputting, Modifying, and Checking the Program If IR 00000 in the above diagram is OFF (i.e., if the execution condition for the first INTERLOCK instruction is OFF), instructions 1 through 4 would be executed with OFF execution conditions and execution would move to the instruction following the INTERLOCK CLEAR instruction.
Section 4-8 Controlling Bit Status The other type of jump is created with a jump number of 00. As many jumps as desired can be created using jump number 00 and JUMP instructions using 00 can be used consecutively without a JUMP END using 00 between them. It is even possible for all JUMP 00 instructions to move program execution to the same JUMP END 00, i.e., only one JUMP END 00 instruction is required for all JUMP 00 instruction in the program.
Section 4-8 Controlling Bit Status 4-8-1 DIFFERENTIATE UP and DIFFERENTIATE DOWN DIFFERENTIATE UP and DIFFERENTIATE DOWN instructions are used to turn the operand bit ON for one cycle at a time. The DIFFERENTIATE UP instruction turns ON the operand bit for one cycle after the execution condition for it goes from OFF to ON; the DIFFERENTIATE DOWN instruction turns ON the operand bit for one cycle after the execution condition for it goes from ON to OFF.
Section 4-9 Work Bits (Internal Relays) To create a self-maintaining bit, the operand bit of an OUTPUT instruction is used as a condition for the same OUTPUT instruction in an OR setup so that the operand bit of the OUTPUT instruction will remain ON or OFF until changes occur in other bits. At least one other condition is used just before the OUTPUT instruction to function as a reset. Without this reset, there would be no way to control the operand bit of the OUTPUT instruction.
Section 4-9 Work Bits (Internal Relays) Reducing Complex Conditions 00000 Work bits can be used to simplify programming when a certain combination of conditions is repeatedly used in combination with other conditions. In the following example, IR 00000, IR 00001, IR 00002, and IR 00003 are combined in a logic block that stores the resulting execution condition as the status of IR 24600.
Section 4-10 Programming Precautions This action is easily programmed by using IR 22500 as a work bit as the operand of the DIFFERENTIATE UP instruction (DIFU(13)). When IR 00000 turns ON, IR 22500 will be turned ON for one cycle and then be turned OFF the next cycle by DIFU(13). Assuming the other conditions controlling IR 00100 are not keeping it ON, the work bit IR 22500 will turn IR 00100 ON for one cycle only.
Section 4-10 Programming Precautions Except for instructions for which conditions are not allowed (e.g., INTERLOCK CLEAR and JUMP END, see below), every instruction line must also have at least one condition on it to determine the execution condition for the instruction at the right. Again, diagram A , below, must be drawn as diagram B. If an instruction must be continuously executed (e.g.
Section 4-12 Special I/O Unit Interface Programs 4-11 Program Execution When program execution is started, the CPU Unit cycles the program from top to bottom, checking all conditions and executing all instructions accordingly as it moves down the bus bar. It is important that instructions be placed in the proper order so that, for example, the desired data is moved to a word before that word is used as the operand for an instruction.
Section 4-12 Special I/O Unit Interface Programs 4-12-2 Special I/O Unit Error Processing Program Use a program like the one shown below to restart a Special I/O Unit in which an error has occurred. This example program restarts Unit 1. AR 0001 (Unit #0 Error Flag) AR0001 DIFU(13) AR0101 SR 27401 (Unit #1 Restart Flag) 27401 Restart Disables calculations during Initialization.
Section 4-12 Special I/O Unit Interface Programs 5. Perform the Expansion Instruction Function Code Assignment operation to assign a function code to XDMR(––). 6. Input the program. Example Program (Special I/O Unit 2) The following program changes the Special I/O Unit Area settings for Unit 2, restarts the Unit, and disables calculations using data from Unit 2 while the Unit is initializing. End of process 1.
Section 4-12 Special I/O Unit Interface Programs 4-12-5 Reducing the Cycle Time Unit 3 Unit 2 Unit 1 Unit 0 When a Special I/O Unit is mounted in a C200HX/HG/HE PC, END refreshing is performed automatically each cycle without making any special settings. When several Special I/O Units are being used, the cycle time might become too long because of the time required for this automatic I/O refreshing.
Section 4-13 Analog Timer Unit Programming The following program example is relevant for Special I/O Units mounted to the CPU Rack or Expansion I/O Racks only, because END refreshing is always performed on Special I/O Units mounted to Slave Racks regardless of the PC Setup settings. 30000 30001 30002 30003 30000 30000 30001 30002 30003 30001 30000 30001 30002 30003 30002 30000 30001 30002 30003 30003 30001 30002 30003 30000 30000 IORF(97) 100 Refreshes Unit 0.
Section 4-13 Analog Timer Unit Programming Refer to the Analog Timer Unit’s Operation Manual for details on switching between internal and external timer SV settings, connecting a variable resistor, and switch settings. Timer Start Input Timer Set Bits (Bits 00 to 03 of n) Bits 08 to 11 of n Time-up Output Completion Flags Timer Start Input Time-up Output Timer interval 4-13-2 Bit Allocation and DIP Switch Settings The following table shows the use of the word (n) allocated to the Analog Timer Unit.
Section 4-13 Analog Timer Unit Programming 4-13-3 Example Program Unit Configuration The following table shows the word allocations for the Units in this example. Item IR word allocated to the Analog Timer Unit IR word allocated to the Input Unit IR word allocated to the Output Unit Word IR 002 IR 000 IR 005 The Analog Timer Unit’s SV settings and external variable resistor control connections are shown below. Timer 0 1 2 3 132 Set value 0.6 s 3s 20 s 8 minutes Range 0.
Section 4-13 Analog Timer Unit Programming Unit Settings and Wiring The following diagram shows the switch settings and wiring connections required to achieve the Unit configuration shown above. The settings on these two variable resistor controls are valid because timers 0 and 1 are set for internal SV settings. Use the screwdriver included with the Unit to set the variable resistor.
Section 4-13 Analog Timer Unit Programming Ladder Program The following diagram shows the example ladder program. 1, 2, 3... 1. Output IR 00500 will go ON about 0.6 s (T0) after input IR 00002 goes ON. 2. Output IR 00501 will go ON about 3 s (T1) after input IR 00003 goes ON. 3. Output IR 00502 will go ON about 20 s (T2) after input IR 00004 goes ON and IR 00503 will go ON about 8 minutes (T3) after input IR 00004 goes ON. 4. Timers 2 and 3 are stopped by input IR 00005.
SECTION 5 Instruction Set The C200HX/HG/HE PCs have large programming instruction sets that allow for easy programming of complicated control processes. This section explains instructions individually and provides the ladder diagram symbol, data areas, and flags used with each. The C200HX/HG/HS PCs can process more than 100 instructions that require function codes, but only 100 function codes (00 to 99) are available.
5-17 5-18 5-19 5-20 136 5-16-3 BLOCK SET – BSET(71) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16-4 BLOCK TRANSFER – XFER(70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16-5 DATA EXCHANGE – XCHG(73) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16-6 SINGLE WORD DISTRIBUTE – DIST(80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-21 Special Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21-1 FIND MAXIMUM – MAX(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21-2 FIND MINIMUM – MIN(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21-3 AVERAGE VALUE – AVG(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Areas, Definer Values, and Flags 5-1 Section 5-3 Notation In the remainder of this manual, all instructions will be referred to by their mnemonics. For example, the Output instruction will be called OUT; the AND Load instruction, AND LD. If you’re not sure of the instruction a mnemonic is used for, refer to Appendix B Programming Instructions. If an instruction is assigned a function code, it will be given in parentheses after the mnemonic.
Section 5-3 Data Areas, Definer Values, and Flags ! Caution The IR and SR areas are considered as separate data areas. If an operand has access to one area, it doesn’t necessarily mean that the same operand will have access to the other area. The border between the IR and SR areas can, however, be crossed for a single operand, i.e., the last bit in the IR area may be specified for an operand that requires more than one word as long as the SR area is also allowed for that operand.
Section 5-4 Differentiated Instructions 5-4 Differentiated Instructions Most instructions are provided in both differentiated and non-differentiated forms. Differentiated instructions are distinguished by an @ in front of the instruction mnemonic. A non-differentiated instruction is executed each time it is cycled as long as its execution condition is ON. A differentiated instruction is executed only once after its execution condition goes from OFF to ON.
Section 5-5 Expansion Instructions 5-5 Expansion Instructions The C200HX/HG/HE PCs have more instructions that require function codes (121) than function codes (100), so some instructions do not have fixed function codes. These instructions, called expansion instructions, are listed in the following table. Default function codes are given for the instructions that have them.
Section 5-6 Coding Right-hand Instructions Code 5-6 Mnemonic Name Page --- (@)MIN FIND MINIMUM 258 --- MTR MATRIX INPUT 348 --- (@)NEG 2’S COMPLEMENT 226 --- (@)NEGL DOUBLE 2’S COMPLEMENT 227 --- PID PID CONTROL 266 --- (@)PMCR PROTOCOL MACRO 335 --- (@)RXD RECEIVE 329 --- (@)SBBL DOUBLE BINARY SUBTRACT 251 --- (@)SCL SCALING 222 --- (@)SRCH DATA SEARCH 314 --- (@)STUP CHANGE RS-232C SETUP 333 --- (@)SUM SUM CALCULATE 261 --- (@)TKY TEN KEY INPUT 346
Section 5-6 Coding Right-hand Instructions The following diagram and corresponding mnemonic code illustrates the points described above.
Section 5-6 Coding Right-hand Instructions Multiple Instruction Lines 00000 If a right-hand instruction requires multiple instruction lines (such as KEEP(11)), all of the lines for the instruction are entered before the right-hand instruction. Each of the lines for the instruction is coded, starting with LD or LD NOT, to form ‘logic blocks’ that are combined by the right-hand instruction. An example of this for SFT(10) is shown below.
Section 5-7 Instruction Set Lists 5-7 Instruction Set Lists This section provides tables of the instructions available in the C200HX/HG/HE. The first table can be used to find instructions by function code. The second table can be used to find instruction by mnemonic. In both tables, the @ symbol indicates instructions with differentiated variations. Note Refer to 5-5 Expansion Instructions for a list of the expansion instructions.
Section 5-7 Instruction Set Lists Mnemonic Code Words Name Page ASFT(@) 17 4 ASYNCHRONOUS SHIFT REGISTER 178 ASL (@) 25 2 ARITHMETIC SHIFT LEFT 175 ASR (@) 26 2 ARITHMETIC SHIFT RIGHT 175 AVG (@) –– 4 AVERAGE VALUE 259 BCD (@) 24 3 BINARY TO BCD 205 BCDL (@) 59 3 DOUBLE BINARY-TO-DOUBLE BCD 206 BCMP (@) 68 4 BLOCK COMPARE 197 BCNT (@) 67 4 BIT COUNTER 308 BIN (@) 23 3 BCD-TO-BINARY 204 BINL (@) 58 3 DOUBLE BCD-TO-DOUBLE BINARY 205 BSET (@) 71 4 BLOC
Section 5-7 Instruction Set Lists Mnemonic Code Words Name Page IORD (@) –– 4 SPECIAL I/O UNIT READ 350 IORF (@) 97 3 I/O REFRESH 306 IOWR (@) –– 4 SPECIAL I/O UNIT WRITE 351 JME 05 2 JUMP END 157 JMP 04 2 JUMP 157 KEEP 11 2 KEEP 154 LD None 1 LOAD 149 LD NOT None 1 LOAD NOT 149 LINE (@) 63 4 COLUMN TO LINE 224 LMSG (@) 47 4 32-CHARACTER MESSAGE 304 MAX (@) –– 4 FIND MAXIMUM 257 MBS (@) –– 4 SIGNED BINARY MULTIPLY 253 MBSL (@) –– 4 DOUBLE
Section 5-7 Instruction Set Lists Mnemonic Code Words Name Page SCAN (@) 18 4 CYCLE TIME 301 SCL (@) –– 4 SCALING 222 SDEC (@) 78 4 7-SEGMENT DECODER 215 SEC (@) 65 4 HOURS TO SECONDS 207 SEND (@) 90 4 NETWORK SEND 318 SET None 2 SET 153 SFT 10 3 SHIFT REGISTER 171 SFTR (@) 84 4 REVERSIBLE SHIFT REGISTER 173 SLD (@) 74 3 ONE DIGIT SHIFT LEFT 177 SNXT 09 2 STEP START 291 SRCH (@) –– 4 DATA SEARCH 314 SRD (@) 75 3 ONE DIGIT SHIFT RIGHT 177 STC
Section 5-8 Ladder Diagram Instructions 5-8 Ladder Diagram Instructions Ladder Diagram instructions include Ladder instructions and Logic Block instructions and correspond to the conditions on the ladder diagram. Logic block instructions are used to relate more complex parts.
Section 5-9 Bit Control Instructions 5-8-2 AND LOAD and OR LOAD AND LOAD – AND LD Ladder Symbol 00000 00002 00001 00003 OR LOAD – OR LD 00000 00001 00002 00003 Ladder Symbol Description When instructions are combined into blocks that cannot be logically combined using only OR and AND operations, AND LD and OR LD are used.
Section 5-9 Bit Control Instructions OUT turns ON the designated bit for an ON execution condition, and turns OFF the designated bit for an OFF execution condition. With a TR bit, OUT appears at a branching point rather than at the end of an instruction line. Refer to 4-7-7 Branching Instruction Lines for details. OUT NOT turns ON the designated bit for a OFF execution condition, and turns OFF the designated bit for an ON execution condition.
Section 5-9 Bit Control Instructions Precautions DIFU(13) and DIFD(14) operation can be uncertain when the instructions are programmed between IL and ILC, between JMP and JME, or in subroutines. Refer to 5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03), 5-11 JUMP and JUMP END – JMP(04) and JME(05), and 5-23 Subroutines and Interrupt Control for details.
Section 5-9 Bit Control Instructions 5-9-3 SET and RESET – SET and RSET Ladder Symbols Operand Data Areas B: Bit SET B IR, SR, AR, HR, LR B: Bit RSET B IR, SR, AR, HR, LR Description SET turns the operand bit ON when the execution condition is ON, and does not affect the status of the operand bit when the execution condition is OFF. RSET turns the operand bit OFF when the execution condition is ON, and does not affect the status of the operand bit when the execution condition is OFF.
Section 5-9 Bit Control Instructions 5-9-4 KEEP – KEEP(11) Ladder Symbol Operand Data Areas S B: Bit KEEP(11) B IR, AR, HR, LR R Limitations Any output bit can generally be used in only one instruction that controls its status. Refer to 3-3 IR Area for details. Description KEEP(11) is used to maintain the status of the designated bit based on two execution conditions. These execution conditions are labeled S and R. S is the set input; R, the reset input.
Section 5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) the input device) can cause the designated bit of KEEP(11) to be reset. This situation is shown below. Input Unit A S KEEP(11) NEVER B A R Bits used in KEEP are not reset in interlocks. Refer to the 5-10 INTERLOCK – and INTERLOCK CLEAR IL(02) and ILC(03) for details. Example If a HR bit or an AR bit is used, bit status will be retained even during a power interruption.
Section 5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) Instruction Treatment OUT and OUT NOT Designated bit turned OFF. SET and RSET Bit status maintained. TIM and TIMH(15) Reset. TTIM(87) PV maintained. CNT, CNTR(12) PV maintained. KEEP(11) Bit status maintained. DIFU(13) and DIFD(14) Not executed (see the following DIFU(13) and DIFD(14) in Interlocks). Not executed. All others IL(02) and ILC(03) do not necessarily have to be used in pairs.
Section 5-11 JUMP and JUMP END – JMP(04) and JME(05) Example The following diagram shows IL(02) being used twice with one ILC(03). Address 00000 IL(02) 00001 TIM TIM511 511 #0015 001.
Section 5-14 Timer and Counter Instructions If the jump number for JMP(04) is 00, the CPU Unit will look for the next JME(05) with a jump number of 00. To do so, it must search through the program, causing a longer cycle time (when the execution condition is OFF) than for other jumps. The status of timers, counters, bits used in OUT, bits used in OUT NOT, and all other status controlled by the instructions between JMP(04) 00 and JMP(05) 00 will not be changed.
Section 5-14 Timer and Counter Instructions Any one TC number cannot be defined twice, i.e., once it has been used as the definer in any of the timer or counter instructions, it cannot be used again. Once defined, TC numbers can be used as many times as required as operands in instructions other than timer and counter instructions. TC numbers run from 000 through 511. No prefix is required when using a TC number as a definer in a timer or counter instruction.
Section 5-14 Timer and Counter Instructions If the execution condition remains ON long enough for TIM to time down to zero, the Completion Flag for the TC number used will turn ON and will remain ON until TIM is reset (i.e., until its execution condition is goes OFF). The following figure illustrates the relationship between the execution condition for TIM and the Completion Flag assigned to it.
Section 5-14 Timer and Counter Instructions ON. When the SV in 005 has expired, 00201 is turned OFF. This bit will also be turned OFF when TIM 001 is reset, regardless of whether or not SV has expired. 00000 Address TIM 000 #0150 015.
Section 5-14 Timer and Counter Instructions 002; 00000 in an inverse condition is necessary to reset TIM 002 when 00000 goes ON and 00500 is necessary to activate TIM 002 (when 00000 is OFF). 00000 Address TIM 001 #0050 Instruction 005.0 s 00000 00001 LD TIM 003.0 s 00002 00003 00004 LD AND NOT TIM 00005 00006 00007 LD LD KEEP(11) 00500 00000 # TIM 002 #0030 TIM 001 S KEEP(11) 00500 TIM 002 Operands R # TIM TIM 00500 00000 001 0050 00500 00000 002 0030 001 002 00000 00500 5.
Section 5-14 Timer and Counter Instructions The following one-shot timer may be used to save memory. 00000 Address TIM 001 #0015 00100 001.5 s TIM 001 Instruction 00000 00001 00002 LD OR TIM 00003 00004 AND NOT OUT 00100 Example 5: Flicker Bits Operands 00000 00100 001 0015 001 00100 # TIM Bits can be programmed to turn ON and OFF at regular intervals while a designated execution condition is ON by using TIM twice. One TIM functions to turn ON and OFF a specified bit, i.e.
Section 5-14 Timer and Counter Instructions 5-14-2 HIGH-SPEED TIMER – TIMH(15) Definer Values N: TC number Ladder Symbol TIMH(15) N # (000 through 511, although 000 through 015 preferred) SV Operand Data Areas SV: Set value (word, BCD) IR, AR, DM, HR, LR, # Limitations SV is between 00.00 and 99.99. (Although 00.00 and 00.01 may be set, 00.00 will disable the timer, i.e., turn ON the Completion Flag immediately, and 00.01 is not reliably cycled.) The decimal point is not entered.
Section 5-14 Timer and Counter Instructions 5-14-3 TOTALIZING TIMER – TTIM(87) Definer Values Ladder Symbol N: TC number # (000 through 511) TTIM(87) N SV RB Operand Data Areas SV: Set value (word, BCD) IR, AR, DM, HR, LR RB: Reset bit IR, SR, AR, HR, LR Limitations SV is between 0000 and 9999 (000.0 and 999.9 s) and must be in BCD. The decimal point is not entered. Each TC number can be used as the definer in only one TIMER or COUNTER instruction.
Section 5-14 Timer and Counter Instructions Example The following figure illustrates the relationship between the execution conditions for a totalizing timer with a set value of 2 s, its PV, and the Completion Flag.
Section 5-14 Timer and Counter Instructions Changes in execution conditions, the Completion Flag, and the PV are illustrated below. PV line height is meant only to indicate changes in the PV. Execution condition on count pulse (CP) ON Execution condition on reset (R) ON OFF OFF ON Completion Flag OFF SV SV PV 0002 SV – 1 0001 SV – 2 0000 Precautions Program execution will continue even if a non-BCD SV is used, but the SV will not be correct.
Section 5-14 Timer and Counter Instructions The previously-shown CNT can be modified to restart from SV each time power is turned ON to the PC. This is done by using the First Cycle Flag in the SR area (25315) to reset CNT as shown below.
Section 5-14 Timer and Counter Instructions tween when the Completion Flag for TIM 001 goes ON and TIM 001 is reset by its Completion Flag). TIM 001 is also reset by the Completion Flag for CNT 002 so that the extended timer would not start again until CNT 002 was reset by 00001, which serves as the reset for the entire extended timer. Because in this example the SV for TIM 001 is 5.0 seconds and the SV for CNT 002 is 100, the Completion Flag for CNT 002 turns ON when 5 seconds x 100 times, i.e.
Section 5-14 Timer and Counter Instructions Limitations Each TC number can be used as the definer in only one TIMER or COUNTER instruction. Description The CNTR(12) is a reversible, up/down circular counter, i.e., it is used to count between zero and SV according to changes in two execution conditions, those in the increment input (II) and those in the decrement input (DI).
Section 5-15 Data Shifting 5-15 Data Shifting All of the instructions described in this section are used to shift data, but in differing amounts and directions. The first shift instruction, SFT(10), shifts an execution condition into a shift register; the rest of the instructions shift data that is already in memory.
Section 5-15 Data Shifting Example 1: Basic Application The following example uses the 1-second clock pulse bit (25502) so that the execution condition produced by 00005 is shifted into a 3-word register between IR 010 and IR 012 every second.
Section 5-15 Data Shifting The program is set up so that a rotary encoder (00000) controls execution of SFT(10) through a DIFU(13), the rotary encoder is set up to turn ON and OFF each time a product passes the first sensor. Another sensor (00002) is used to detect faulty products in the shoot so that the pusher output and HR 0003 of the shift register can be reset as required.
Section 5-15 Data Shifting Description SFTR(84) is used to create a single- or multiple-word shift register that can shift data to either the right or the left. To create a single-word register, designate the same word for St and E. The control word provides the shift direction, the status to be put into the register, the shift pulse, and the reset input. The control word is allocated as follows: 15 14 13 12 Not used.
Section 5-15 Data Shifting 5-15-3 ARITHMETIC SHIFT LEFT – ASL(25) Ladder Symbols Description Operand Data Areas ASL(25) @ASL(25) Wd Wd Wd: Shift word IR, SR, AR, DM, HR, LR When the execution condition is OFF, ASL(25) is not executed. When the execution condition is ON, ASL(25) shifts a 0 into bit 00 of Wd, shifts the bits of Wd one bit to the left, and shifts the status of bit 15 into CY.
Section 5-15 Data Shifting 5-15-5 ROTATE LEFT – ROL(27) Ladder Symbols Description Operand Data Areas ROL(27) @ROL(27) Wd Wd Wd: Rotate word IR, SR, AR, DM, HR, LR When the execution condition is OFF, ROL(27) is not executed. When the execution condition is ON, ROL(27) shifts all Wd bits one bit to the left, shifting CY into bit 00 of Wd and shifting bit 15 of Wd into CY.
Section 5-15 Data Shifting 5-15-7 ONE DIGIT SHIFT LEFT – SLD(74) Ladder Symbols Operand Data Areas St: Starting word SLD(74) @SLD(74) St St E E IR, SR, AR, DM, HR, LR E: End word IR, SR, AR, DM, HR, LR Limitations St and E must be in the same data area, and St must be less than or equal to E. Description When the execution condition is OFF, SLD(74) is not executed. When the execution condition is ON, SLD(74) shifts data between St and E (inclusive) by one digit (four bits) to the left.
Section 5-15 Data Shifting Precautions If a power failure occurs during a shift operation across more than 50 words, the shift operation might not be completed. Set the range between E and St to a maximum of 50 words. Flags ER: The St and E words are in different areas, or St is less than E. Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.
Section 5-15 Data Shifting Description When the execution condition is OFF, ASFT(17) does nothing and the program moves to the next instruction. When the execution condition is ON, ASFT(17) is used to create and control a reversible asynchronous word shift register between St and E. This register only shifts words when the next word in the register is zero, e.g., if no words in the register contain zero, nothing is shifted. Also, only one word is shifted for each word in the register that contains zero.
Section 5-16 Data Movement 5-16 Data Movement This section describes the instructions used for moving data between different addresses in data areas. These movements can be programmed to be within the same data area or between different data areas. Data movement is essential for utilizing all of the data areas of the PC. Effective communications in Link Systems also requires data movement. All of these instructions change only the content of the words to which data is being moved, i.e.
Section 5-16 Data Movement Precautions TC numbers cannot be designated as D to change the PV of the timer or counter. However, these can be easily changed using BSET(71). Flags ER: Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.) EQ: ON when all zeros are transferred to D. N: ON when bit 15 of D is set to 1.
Section 5-16 Data Movement Example 00003 The following example shows how to use BSET(71) to change the PV of a timer depending on the status of IR 00003 and IR 00004. When IR 00003 is ON, TIM 010 will operate as a 50-second timer; when IR 00004 is ON, TIM 010 will operate as a 30-second timer.
Section 5-16 Data Movement Flags ER: N is not BCD between 0000 and 2000. S and S+N or D and D+N are not in the same data area. Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.
Data Movement Section 5-16 Stack Operation (C=9000 to 9999) When the execution condition is OFF, DIST(80) is not executed. When the execution condition is ON, DIST(80) operates a stack from DBs to DBs+C–9000. DBs is the stack pointer, so S is copied to the word indicated by DBs and DBs is incremented by 1. The Negative Flag also changes. Digits of C: 3 2 1 0 Specifies the stack length (000 to 999). A value of 9 indicates stack operation. Data can be added to the stack until it is full.
Section 5-16 Data Movement 5-16-7 DATA COLLECT – COLL(81) Operand Data Areas SBs: Source base word Ladder Symbols IR, SR, AR, DM, HR, TC, LR COLL(81) @COLL(81) SBs SBs C C D D C: Offset data (BCD) IR, SR, AR, DM, HR, TC, LR, # D: Destination word IR, SR, AR, DM, HR, TC, LR Limitations C must be a BCD. If C≤6655, SBs must be in the same data area as SBs+C. If the leftmost digit of C is 8 or 9, DBs must be in the same data area as SBs+N (N=the 3 rightmost digits of C).
Section 5-16 Data Movement Example In the following example, the content of C (HR 00) is 9010, and COLL(81) is used to copy the oldest entries from a10-word stack (IR 001 to IR 010) to LR 20.
Section 5-16 Data Movement Example In the following example, the content of C (HR 00) is 8010, and COLL(81) is used to copy the most recent entries from a 10-word stack (IR 001 to IR 010) to LR 20.
Section 5-16 Data Movement Description When the execution condition is OFF, MOVB(82) is not executed. When the execution condition is ON, MOVB(82) copies the specified bit of S to the specified bit in D. The bits in S and D are specified by Bi. The rightmost two digits of Bi designate the source bit; the leftmost two bits designate the destination bit.
Data Movement Section 5-16 Digit Designator The following show examples of the data movements for various values of Di. Di: 0010 Di: 0030 S D S D 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 S D S D 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 Di: 0031 Flags ER: Di: 0023 At least one of the rightmost three digits of Di is not between 0 and 3. Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.
Section 5-16 Data Movement Example In the following example, XFRB(62) is used to transfer 5 bits from IR 020 to LR 21 when IR 00001 is ON. The starting bit in IR 020 is 0, and the starting bit in LR 21 is 4, so IR 02000 to IR 02004 are copied to LR 2104 to LR 2108.
Section 5-16 Data Movement Example The following example copies the contents of the 300 words from DM 0000 through DM 0299 to EM 2000 through EM 2299 in the current EM bank.
Section 5-17 Data Comparison Example The following example copies the contents of the 300 words from DM 0000 through DM 0299 to EM 2000 through EM 2299 in the EM bank 01. (EM bank 00 isn’t used as the source because S isn’t a constant.
Section 5-17 Data Comparison Example The following example shows the comparisons made and the results provided for MCMP(19). Here, the comparison is made during each cycle when 00000 is ON.
Section 5-17 Data Comparison Flags ER: Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.) EQ: ON if Cp1 equals Cp2. LE: ON if Cp1 is less than Cp2. GR: ON if Cp1 is greater than Cp2. Flag Example 1: Saving CMP(20) Results 00000 Address C1 < C2 C1 = C2 C1 > C2 GR 25505 OFF OFF ON EQ 25506 OFF ON OFF LE 25507 ON OFF OFF The following example shows how to save the comparison result immediately.
Section 5-17 Data Comparison The branching structure of this diagram is important in order to ensure that 00200, 00201, and 00202 are controlled properly as the timer counts down. Because all of the comparisons here use to the timer’s PV as reference, the other operand for each CMP(20) must be in 4-digit BCD. 00000 TIM 010 #5000 500.0 s CMP(20) TIM 010 #4000 25507 00200 Output at 100 s. 00200 CMP(20) TIM 010 #3000 25507 00201 Output at 200 s. 00201 CMP(20) TIM 010 #2000 25507 00202 Output at 300 s.
Section 5-17 Data Comparison 5-17-3 DOUBLE COMPARE – CMPL(60) Ladder Symbols Operand Data Areas Cp1: First word of first compare word pair CMPL(60) IR, SR, AR, DM, HR, TC, LR Cp1 Cp2: First word of second compare word pair Cp2 IR, SR, AR, DM, HR, TC, LR 000 (fixed) Limitations Cp1 and Cp1+1 must be in the same data area, as must Cp2 and Cp2+1. Description When the execution condition is OFF, CMPL(60) is not executed.
Section 5-17 Data Comparison Example: Saving CMPL(60) Results 00000 The following example shows how to save the comparison result immediately. If the content of HR 10, HR 09 is greater than that of 011, 010, then 00200 is turned ON; if the two contents are equal, 00201 is turned ON; if content of HR 10, HR 09 is less than that of 011, 010, then 00202 is turned ON. In some applications, only one of the three OUTs would be necessary, making the use of TR 0 unnecessary.
Section 5-17 Data Comparison Description When the execution condition is OFF, BCMP(68) is not executed. When the execution condition is ON, BCMP(68) compares CD to the ranges defined by a block consisting of of CB, CB+1, CB+2, ..., CB+31. Each range is defined by two words, the first one providing the lower limit and the second word providing the upper limit. If CD is found to be within any of these ranges (inclusive of the upper and lower limits), the corresponding bit in R is set.
Section 5-17 Data Comparison Example The following example shows the comparisons made and the results provided for BCMP(68). Here, the comparison is made during each cycle when 00000 is ON. 00000 BCMP(68) Address Instruction 00000 00001 LD BCMP(68) 001 HR 10 Operands 00000 HR 05 HR HR CD 001 001 Lower limits 0210 HR 10 HR 12 HR 14 HR 16 HR 18 HR 20 HR 22 HR 24 HR 26 HR 28 HR 30 HR 32 HR 34 HR 36 HR 38 HR 40 Compare data in IR 001 (which contains 0210) with the given ranges.
Section 5-17 Data Comparison Example The following example shows the comparisons made and the results provided for TCMP(85). Here, the comparison is made during each cycle when 00000 is ON. 00000 TCMP(85) 001 Address Instruction 00000 00001 LD TCMP(85) Operands 00000 HR 10 HR 05 CD: 001 001 Upper limits 0210 HR 10 HR 11 HR 12 HR 13 HR 14 HR 15 HR 16 HR 17 HR 18 HR 19 HR 20 HR 21 HR 22 HR 23 HR 24 HR 25 Compare the data in IR 001 with the given ranges.
Section 5-17 Data Comparison Precautions Placing other instructions between ZCP(88) and the operation which accesses the EQ, LE, and GR flags may change the status of these flags. Be sure to access them before the desired status is changed. Flags ER: Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.) LL is greater than UL. Example: Saving ZCP(88) Results 00000 EQ: ON if LL ≤ CD ≤ UL LE: ON if CD < LL. GR: ON if CD > UL.
Section 5-17 Data Comparison Description When the execution condition is OFF, ZCPL(––) is not executed. When the execution condition is ON, ZCPL(––) compares the 8-digit value in CD, CD+1 to the range defined by lower limit LL+1,LL and upper limit UL+1,UL and outputs the result to the GR, EQ, and LE flags in the SR area. The resulting flag status is shown in the following table.
Section 5-17 Data Comparison Flags ER: Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.) EQ: ON if Cp1 equals Cp2. LE: ON if Cp1 is less than Cp2. GR: ON if Cp1 is greater than Cp2.
Section 5-18 Data Conversion 5-18 Data Conversion The conversion instructions convert word data that is in one format into another format and output the converted data to specified result word(s). Conversions are available to convert between binary (hexadecimal) and BCD, to 7-segment display data, to ASCII, and between multiplexed and non-multiplexed data. All of these instructions change only the content of the words to which converted data is being moved, i.e.
Section 5-18 Data Conversion 5-18-2 DOUBLE BCD-TO-DOUBLE BINARY – BINL(58) Ladder Symbols Operand Data Areas S: First source word (BCD) BINL(58) @BINL(58) S S R R IR, SR, AR, DM, HR, TC, LR R: First result word Description Flags IR, SR, AR, DM, HR, LR When the execution condition is OFF, BINL(58) is not executed. When the execution condition is ON, BINL(58) converts an eight-digit number in S and S+1 into 32-bit binary data, and outputs the converted data to R and R+1.
Section 5-18 Data Conversion Note If the content of S exceeds 270F, the converted result would exceed 9999 and BCD(24) will not be executed. When the instruction is not executed, the content of R remains unchanged. Signed Binary Data BCD(24) cannot be used to convert signed binary data directly to BCD. To convert signed binary data, first determine whether the data is positive or negative. If it is positive, BCD(24) can be used to convert the data to BCD.
Section 5-18 Data Conversion 5-18-5 HOURS-TO-SECONDS – SEC(65) Operand Data Areas S: Beginning source word (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR SEC(65) @SEC(65) S S R R 000 000 R: Beginning result word (BCD) IR, SR, AR, DM, HR, TC, LR 000: Set to 000. --- Limitations S and S+1 must be within the same data area. R and R+1 must be within the same data area. S and S+1 must be BCD and must be in the proper hours/minutes/seconds format.
Section 5-18 Data Conversion 5-18-6 SECONDS-TO-HOURS – HMS(66) Operand Data Areas S: Beginning source word (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR HMS(66) @HMS(66) S S R R 000 000 R: Beginning result word (BCD) IR, SR, AR, DM, HR, TC, LR 000: Set to 000. --- Limitations S and S+1 must be within the same data area. R and R+1 must be within the same data area. S and S+1 must be BCD and must be between 0 and 35,999,999 seconds.
Section 5-18 Data Conversion 5-18-7 4-TO-16/8-TO-256 DECODER – MLPX(76) Operand Data Areas S: Source word Ladder Symbols IR, SR, AR, DM, HR, TC, LR MLPX(76) @MLPX(76) S S C C R R C: Control word Limitations IR, SR, AR, DM, HR, TC, LR, # R: First result word IR, SR, AR, DM, HR, LR When the leftmost digit of C is 0, the rightmost two digits of C must each be between 0 and 3. When the leftmost digit of C is 1, the rightmost two digits of C must each be between 0 and 1.
Section 5-18 Data Conversion Some example C values and the digit-to-word conversions that they produce are shown below. C: 0010 C: 0030 S S 0 R 0 R 1 R+1 1 R+1 2 2 R+2 3 3 R+3 C: 0031 C: 0023 S S 0 R 0 R 1 R+1 1 R+1 2 R+2 2 R+2 3 R+3 3 The following is an example of a one-digit decode operation from digit number 1 of S, i.e., here C would be 0001. Source word C Bit C (i.e., bit number 12) turned ON.
Section 5-18 Data Conversion The 4 possible C values and the conversions that they produce are shown below. (In S, 0 indicates the rightmost byte and 1 indicates the leftmost byte.) C: 1000 C: 1001 S S 0 R to R+15 0 R to R+15 1 R+16 to R+31 1 R+16 to R+31 C: 1010 C: 1011 S S 0 R to R+15 0 R to R+15 1 R+16 to R+31 1 R+16 to R+31 The following is an example of a one-byte decode operation from the rightmost byte of S (C would be 1000 in this case).
Section 5-18 Data Conversion Example: 4-bit to 16-bit Decoding The following program converts three digits of data from LR 20 to bit positions and turns ON the corresponding bits in three consecutive words starting with HR 10.
Section 5-18 Data Conversion 16-bit to 4-bit Encoder DMPX(77) operates as a 16-bit to 4-bit encoder when the leftmost digit of C is 0. When the execution condition is OFF, DMPX(77) is not executed. When the execution condition is ON, DMPX(77) determines the position of the highest ON bit in S, encodes it into single-digit hexadecimal value corresponding to the bit number, then transfers the hexadecimal value to the specified digit in R.
Section 5-18 Data Conversion 256-bit to 8-bit Encoder DMPX(77) operates as a 256-bit to 8-bit encoder when the leftmost digit of C is set to 1. When the execution condition is OFF, DMPX(77) is not executed.
Section 5-18 Data Conversion Example: 16-bit to 4-bit Encoding When 00000 is ON, the following diagram encodes IR words 010 and 011 to the first two digits of HR 20 and then encodes LR 10 and 11 to the last two digits of HR 20. Although the status of each source word bit is not shown, it is assumed that the bit with status 1 (ON) shown is the highest bit that is ON in the word.
Section 5-18 Data Conversion Any or all of the digits in S may be converted in sequence from the designated first digit. The first digit, the number of digits to be converted, and the half of D to receive the first 7-segment display code (rightmost or leftmost 8 bits) are designated in Di. If multiple digits are designated, they will be placed in order starting from the designated half of D, each requiring two digits.
Section 5-18 Data Conversion Example The following example shows the data to produce an 8. The lower case letters show which bits correspond to which segments of the 7-segment display. The table underneath shows the original data and converted code for all hexadecimal digits.
Section 5-18 Data Conversion 5-18-10 ASCII CONVERT – ASC(86) Operand Data Areas S: Source word Ladder Symbols IR, SR, AR, DM, HR, TC, LR ASC(86) @ASC(86) S S Di Di D D Di: Digit designator IR, SR, AR, DM, HR, TC, LR, # D: First destination word IR, SR, AR, DM, HR, LR Limitations Di must be within the values given below All destination words must be in the same data area. Description When the execution condition is OFF, ASC(86) is not executed.
Section 5-18 Data Conversion Some examples of Di values and the 4-bit binary to 8-bit ASCII conversions that they produce are shown below.
Section 5-18 Data Conversion Limitations Di must be within the values given below. All source words must be in the same data area. Bytes in the source words must contain the ASCII code equivalent of hexadecimal values, i.e., 30 to 39 (0 to 9), 41 to 46 (A to F), or 61 to 66 (a to f). Description When the execution condition is OFF, HEX(––) is not executed.
Section 5-18 Data Conversion Some examples of Di values and the 8-bit ASCII to 4-bit hexadecimal conversions that they produce are shown below.
Section 5-18 Data Conversion Flags ER: Incorrect digit designator, or data area for destination exceeded. Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.) In the following example, the 2nd byte of LR 10 and the 1st byte of LR 11 are converted to hexadecimal values and those values are written to the first and second bytes of IR 010.
Section 5-18 Data Conversion The following table shows the functions and ranges of the parameter words: Parameter Function Range Comments P1 BCD point #1 (AY) 0000 to 9999 --- P1+1 Hex. point #1 (AX) 0000 to FFFF Do not set P1+1=P1+3. P1+2 BCD point #2 (BY) 0000 to 9999 --- P1+3 Hex. point #2 (BX) 0000 to FFFF Do not set P1+3=P1+1. The following diagram shows the source word, S, converted to D according to the line defined by points (AY, AX) and (BY, BX).
Section 5-18 Data Conversion 5-18-13 COLUMN TO LINE – LINE(63) Operand Data Areas S: First word of 16 word source set Ladder Symbols IR, SR, AR, DM, HR, TC, LR LINE(63) @LINE(63) S S C C D D C: Column bit designator (BCD) Limitations IR, SR, AR, DM, HR, TC, LR, # D: Destination word IR, SR, AR, DM, HR, TC, LR S and S+15 must be in the same data area. C must be between #0000 and #0015. Description When the execution condition is OFF, LINE(63) is not executed.
Section 5-18 Data Conversion 5-18-14 LINE TO COLUMN – COLM(64) Operand Data Areas S: Source word Ladder Symbols IR, SR, AR, DM, HR, TC, LR COLM(64) @COLM(64) S S D D C C D: First word of the destination set Limitations IR, AR, DM, HR, TC, LR C: Column bit designator (BCD) IR, SR, AR, DM, HR, TC, LR, # D and D+15 must be in the same data area. C must be between #0000 and #0015. Description When the execution condition is OFF, COLM(64) is not executed.
Section 5-18 Data Conversion 5-18-15 2’S COMPLEMENT – NEG(––) Ladder Symbols Operand Data Areas NEG(––) S: Source word S IR, SR, AR, DM, HR, TC, LR, # R R: Result word IR, SR, AR, DM, HR, LR Description Converts the four-digit hexadecimal content of the source word (S) to its 2’s complement and outputs the result to the result word (R). This operation is effectively the same as subtracting S from 0000 and outputting the result to R.
Section 5-18 Data Conversion 5-18-16 DOUBLE 2’S COMPLEMENT – NEGL(––) Ladder Symbols Operand Data Areas NEGL(––) S: First source word S IR, SR, AR, DM, HR, TC, LR R R: First result word --- IR, SR, AR, DM, HR, LR Limitations S and S+1 must be in the same data area, as must R and R+1. Description Converts the eight-digit hexadecimal content of the source words (S and S+1) to its 2’s complement and outputs the result to the result words (R and R+1).
Section 5-19 BCD Calculations 5-19 BCD Calculations The BCD calculation instructions – INC(38), DEC(39), ADD(30), ADDL(54), SUB(31), SUBL(55), MUL(32), MULL(56), DIV(33), DIVL(57), FDIV(79), and ROOT(72) – all perform arithmetic operations on BCD data. For INC(38) and DEC(39) the source and result words are the same. That is, the content of the source word is overwritten with the instruction result. All other instructions change only the content of the words in which results are placed, i.e.
Section 5-19 BCD Calculations 5-19-3 SET CARRY – STC(40) Ladder Symbols STC(40) @STC(40) When the execution condition is OFF, STC(40) is not executed. When the execution condition is ON, STC(40) turns ON CY (SR 25504). Note Refer to Appendix C Error and Arithmetic Flag Operation for a table listing the instructions that affect CY. 5-19-4 CLEAR CARRY – CLC(41) Ladder Symbols CLC(41) @CLC(41) When the execution condition is OFF, CLC(41) is not executed.
Section 5-19 BCD Calculations Example If 00002 is ON, the program represented by the following diagram clears CY with CLC(41), adds the content of LR 25 to a constant (6103), places the result in DM 0100, and then moves either all zeros or 0001 into DM 0101 depending on the status of CY (25504). This ensures that any carry from the last digit is preserved in R+1 so that the entire result can be later handled as eight-digit data.
Section 5-19 BCD Calculations Flags ER: Au and/or Ad is not BCD. Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.) Example CY: ON when there is a carry in the result. EQ: ON when the result is 0. When 00000 is ON, the following program adds two 12-digit numbers, the first contained in LR 20 through LR 22 and the second in DM 0012. The result is placed in LR 10 through HR 13.
Section 5-19 BCD Calculations Flags ER: Mi and/or Su is not BCD. Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.) ! Caution Example CY: ON when the result is negative, i.e., when Mi is less than Su plus CY. EQ: ON when the result is 0. Be sure to clear the carry flag with CLC(41) before executing SUB(31) if its previous status is not required, and check the status of CY after doing a subtraction with SUB(31).
Section 5-19 BCD Calculations Note The actual SUB(31) operation involves subtracting Su and CY from 10,000 plus Mi. For positive results the leftmost digit is truncated. For negative results the 10s complement is obtained. The procedure for establishing the correct answer is given below.
Section 5-19 BCD Calculations Flags ER: Mi, M+1,Su, and Su+1 are not BCD. Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.) CY: ON when the result is negative, i.e., when Mi is less than Su. EQ: ON when the result is 0. The following example works much like that for single-word subtraction.
Section 5-19 BCD Calculations 5-19-9 BCD MULTIPLY – MUL(32) Operand Data Areas Md: Multiplicand (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # MUL(32) @MUL(32) Md Md Mr Mr R R Mr: Multiplier (BCD) IR, SR, AR, DM, HR, TC, LR, # R: First result word IR, SR, AR, DM, HR LR Limitations R and R+1 must be in the same data area. Description When the execution condition is OFF, MUL(32) is not executed.
Section 5-19 BCD Calculations 5-19-10 DOUBLE BCD MULTIPLY – MULL(56) Operand Data Areas Md: First multiplicand word (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR MULL(56) @MULL(56) Md Md Mr Mr R R Mr: First multiplier word (BCD) IR, SR, AR, DM, HR, TC, LR R: First result word IR, SR, AR, DM, HR LR Limitations Md and Md+1 must be in the same data area, as must Mr and Mr+1. R through R+3 must be in the same data area. Description When the execution condition is OFF, MULL(56) is not executed.
Section 5-19 BCD Calculations Flags ER: Dd or Dr is not in BCD or when Dr is #0000. Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.) EQ: Example ON when the result is 0. When IR 00000 is ON with the following program, the content of IR 020 is divided by the content of HR 09 and the result is placed in DM 0017 and DM 0018. Example data and calculations are shown below the program.
Section 5-19 BCD Calculations 5-19-13 FLOATING POINT DIVIDE – FDIV(79) Operand Data Areas Dd: First dividend word (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR FDIV(79) @FDIV(79) Dd Dd Dr Dr R R Dr: First divisor word (BCD) IR, SR, AR, DM, HR, TC, LR R: First result word IR, SR, AR, DM, HR, LR Limitations Dr and Dr+1 cannot contain zero. Dr and Dr+1 must be in the same data area, as must Dd and Dd+1; R and R+1. The dividend and divisor must be between 0.0000001 x 10–7 and 0.9999999 x 107.
BCD Calculations Example Section 5-19 The following example shows how to divide two whole four-digit numbers (i.e., numbers without fractions) so that a floating-point value can be obtained. First the original numbers must be placed in floating-point form. Because the numbers are originally without decimal points, the exponent will be 4 (e.g., 3452 would equal 0.3452 x 104). All of the moves are to place the proper data into consecutive words for the final division, including the exponent and zeros.
Section 5-19 BCD Calculations 00000 @MOV(21) HR 01 #0000 HR 00 0 0 0 0 HR 00 @MOV(21) 0000 #0000 HR 02 @MOV(21) HR 01 4 0 0 0 #4000 HR 00 0 0 0 0 HR 01 @MOV(21) 4000 #4000 HR 03 DM 0000 3 4 5 2 @MOVD(83) DM 0000 #0021 HR 01 4 3 4 5 HR 01 00000 @MOVD(83) 0 HR 00 0 0 0 DM 0000 3 4 5 2 DM 0000 #0300 HR 00 HR 01 4 3 4 5 2 HR 00 0 0 0 HR 01 4 3 4 5 2 HR 00 0 0 0 HR 03 4 0 0 7 9 HR 02 0 0 0 DM 0003 2 4 3 6 9 DM 0002 6 2 0 @MOVD(83) DM 0001 #0021 HR 03 @MOVD(83) DM 0001 #
Section 5-19 BCD Calculations 5-19-14 SQUARE ROOT – ROOT(72) Ladder Symbols Operand Data Areas Sq: First source word (BCD) ROOT(72) @ROOT(72) Sq Sq R R IR, SR, AR, DM, HR, TC, LR R: Result word IR, SR, AR, DM, HR, LR, Limitations Sq and Sq+1 must be in the same data area. Description When the execution condition is OFF, ROOT(72) is not executed. When the execution condition is ON, ROOT(72) computes the square root of the eight-digit content of Sq and Sq+1 and places the result in R.
Section 5-19 BCD Calculations In this example, √6017 = 77.56, and 77.56 is rounded off to 78. 00000 @BSET(71) DM 0101 0 0 0 #0000 0 0 DM 0100 0 0 0 DM 0100 DM 0101 0000 010 6 0 1 @MOV(21) 010 0000 7 DM 0101 DM 0101 6 0 1 7 @ROOT(72) 0 DM 0100 0 0 0 DM 0100 60170000= 77.
Section 5-20 Binary Calculations 5-20 Binary Calculations Binary calculation instructions — ADB(50), SBB(51), MLB(52), DVB(53), ADBL(––), SBBL(––), MBS(––), MBSL(––), DBS(––), and DBSL(––) — perform arithmetic operations on hexadecimal data. Four of these instructions (ADB(50), SBB(51), ADBL(––), and SBBL(––)) can act on both normal and signed data, two (MLB(52) and DVB(53)) act only on normal data, and four (MBS(––), MBSL(––), DBS(––), and DBSL(––)) act only on signed binary data.
Section 5-20 Binary Calculations Example 1: Adding Normal Data The following example shows a four-digit addition with CY used to place either #0000 or #0001 into R+1 to ensure that any carry is preserved.
Section 5-20 Binary Calculations In the case below, 25,321 +(–13,253) = 12,068 (62E9 + CC3B = 2F24). Neither OF nor UF are turned ON. 6 + Au: LR 20 2 E 9 Ad: DM 0010 C C 3 B 2 Ad: DM 0010 F 2 4 Note The status of the CY flag can be ignored when adding signed binary data since it is relevant only in the addition of normal hexadecimal values.
Section 5-20 Binary Calculations Example 1: Normal Data The following example shows a four-digit subtraction with CY used to place either #0000 or #0001 into R+1 to ensure that any carry is preserved.
Section 5-20 Binary Calculations Example 2: Signed Binary Data In the following example, SBB(51) is used to subtract one 16-bit signed binary value from another. (The 2’s complement is used to express negative values). The effective range for 16-bit signed binary values is –32,768 (8000) to +32,767 (7FFF). The overflow flag (OF: SR 25404) is turned ON if the result exceeds +32,767 (7FFF) and the underflow flag (UF: SR 25405) is turned ON if the result falls below –32,768 (8000).
Section 5-20 Binary Calculations 5-20-3 BINARY MULTIPLY – MLB(52) Operand Data Areas Md: Multiplicand word (binary) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # MLB(52) @MLB(52) Md Md Mr Mr R R Mr: Multiplier word (binary) IR, SR, AR, DM, HR, TC, LR, # R: First result word IR, SR, AR, DM, HR LR Limitations R and R+1 must be in the same data area. Description When the execution condition is OFF, MLB(52) is not executed.
Section 5-20 Binary Calculations Precautions DVB(53) cannot be used to divide signed binary data. Use DBS(––) instead. Refer to 5-20-9 SIGNED BINARY DIVIDE – DBS(––) for details. Flags ER: Dr contains 0. Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.) ON when the result is 0. ON when bit 15 of R is set to 1.
Section 5-20 Binary Calculations ADBL(––) can also be used to add signed binary data. The overflow and underflow flags (SR 25404 and SR 25405) indicate whether the result has exceeded the lower or upper limits of the 32-bit signed binary data range. Refer to page 27 for details on signed binary data. Flags Example 1: Normal Data ER: Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.
Section 5-20 Binary Calculations In the case below, 1,799,100,099 + (–282,751,929) = 1,516,348,100 (6B3C167D + EF258C47 = 5A61A2C4). Neither OF nor UF are turned ON.
Section 5-20 Binary Calculations Flags Example 1: Normal Data ER: Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.) CY: ON when the result is negative, i.e., when Mi is less than Su plus CY. EQ: ON when the result is 0. OF: ON when the result exceeds +2,147,483,647 (7FFF FFFF). UF: ON when the result is below –2,147,483,648 (8000 0000). N: ON when bit 15 of R+1 is set to 1.
Section 5-20 Binary Calculations In the case below, 1,799,100,099 – (–282,751,929) = 2,081,851,958 (6B3C 167D – {EF25 8C47 – 1 0000 0000} = 7C16 8A36). Neither OF nor UF are turned ON.
Section 5-20 Binary Calculations Example In the following example, MBS(––) is used to multiply the signed binary contents of IR 001 with the signed binary contents of DM 0020 and output the result to LR 21 and LR 22.
Section 5-20 Binary Calculations Example In the following example, MBSL(––) is used to multiply the signed binary contents of IR 101 and IR 100 with the signed binary contents of DM 0021 and DM 0020 and output the result to LR 24 through LR 21.
Section 5-20 Binary Calculations Example In the following example, DBS(––) is used to divide the signed binary contents of IR 001 with the signed binary contents of DM 0020 and output the result to LR 21 and LR 22.
Section 5-21 Special Math Instructions Example In the following example, DBSL(––) is used to divide the signed binary contents of IR 002 and IR 001 with the signed binary contents of DM 0021 and DM 0020 and output the result to LR 24 through LR 21.
Section 5-21 Special Math Instructions If bit 15 of C is ON and more than one address contains the same maximum value, the position of the lowest of the addresses will be output to D+1. The number of words within the range (N) is contained in the 3 rightmost digits of C, which must be BCD between 001 and 999. When bit 15 of C is OFF, data within the range is treated as normal binary and when it is ON the data is treated as signed binary.
Section 5-21 Special Math Instructions 2. For an address in another data area, the number of addresses from the beginning of the search is written to D+1. For example, if the address containing the minimum value is IR 114 and the first word in the search range is IR 014, then #0100 is written in D+1. If bit 14 of C is ON and more than one address contains the same minimum value, the position of the lowest of the addresses will be output to D+1.
Section 5-21 Special Math Instructions For the first N–1 cycles when the execution condition is ON, AVG(––) writes the value of S to D. Each time that AVG(––) is executed, the previous value of S is stored in words D+2 to D+N+1. The first 2 digits of D+1 are incremented with each execution and act as a pointer to indicate where the previous value is stored. Bit 15 of D+1 remains OFF for the first N–1 cycles. On the Nth cycle, the previous value of S is written to last word in the range D+2 to D+N+1.
Section 5-21 Special Math Instructions Example In the following example, the content of IR 040 is set to #0000 and then incremented by 1 each cycle. For the first two cycles, AVG(––) moves the content of IR 040 to DM 1002 and DM 1003. The contents of DM 1001 will also change (which can be used to confirm that the results of AVG(––) has changed). On the third and later cycles AVG(––) calculates the average value of the contents of DM 1002 to DM 1004 and writes that average value to DM 1000.
Section 5-21 Special Math Instructions Description When the execution condition is OFF, SUM(––) is not executed. When the execution condition is ON, SUM(––) adds either the contents of words R1 to R1+N–1 or the bytes in words R1 to R1+N/2–1 and outputs that value to the destination words (D and D+1). The data can be summed as binary or BCD and will be output in the same form. Binary data can be either signed or unsigned.
Section 5-21 Special Math Instructions Example In the following example, the BCD contents of the 10 words from DM 0000 to DM 0009 are added when IR 00001 is ON and the result is written to DM 0100 and DM 0101.
Section 5-21 Special Math Instructions Examples Sine Function The following example demonstrates the use of the APR(69) sine function to calculate the sine of 30°. The sine function is specified when C is #0000. Address 00000 APR(69) #0000 00000 00001 Instruction 00000 DM 0000 # DM DM DM 0100 Input data, x 0 0 S: DM 0000 101 100 3 0 10–1 0 Cosine Function 10–1 5 D: DM 0100 10–2 10–3 0 0 10–4 0 Result data has four significant digits, fifth and higher digits are ignored.
Section 5-21 Special Math Instructions Enter the coordinates of the m+1 end-points, which define the m line segments, as shown in the following table. Enter all coordinates in BIN form. Always enter the coordinates from the lowest X value (X1) to the highest (Xm). X0 is 0000, and does not have to be entered. Y Word Ym Coordinate C+1 Xm (max.
Section 5-21 Special Math Instructions In this case, the input data word, IR 010, contains #0014, and f(0014) = #0726 is output to R, IR 011. Y $1F20 $0F00 (x,y) $0726 $0402 (0,0) $0005 $0014 $001A X $05F0 5-21-6 PID CONTROL – PID(––) Operand Data Areas Ladder Symbol S: Input word PID(––) IR, SR, AR, DM, HR, LR S C: First parameter word C IR, SR, DM, HR, LR D D: Output word IR, SR, AR, DM, HR, LR Limitations C and C+32 must be within the same data area.
Section 5-21 Special Math Instructions Note 1. The actual integral and derivative times are calculated using the values set in C+2 and C+3 and the time unit set in C+6. 2. Setting the 2-PID parameter (α) to 000 yields 0.65, the normal value. 3. The only CQM1 model that can use PID(––) is the CQM1-CPU4 -EV1.
Section 5-21 Special Math Instructions Parameter Settings Item Set value (SV) Proportional band Integral time (Tik) Contents This is the target value of the process being controlled. This is the parameter for P control expressing the proportional control range/total control range. This is a constant expressing the strength of the integral operation. As this value increases, the integral strength increases. The time unit parameter determines the setting method.
Section 5-21 Special Math Instructions Execution Condition ON The PID operation is executed at the intervals based on the sampling period, according to the PID parameters that have been set. Sampling Period and PID Execution Timing The sampling period is the time interval to retrieve the measurement data for carrying out a PID operation. PID(––), however, is executed according to the CPU Unit’s sampling time, so there may be cases where the sampling period is exceeded.
Section 5-21 Special Math Instructions cording to the time that has passed. The strength of the integral operation is indicated by the integral time, which is the time required for the integral operation amount to reach the same level as the proportional operation amount with respect to the step deviation, as shown in the following illustration. The shorter the integral time, the stronger the correction by the integral operation will be.
Section 5-21 Special Math Instructions PID Operation PID operation combines proportional operation (P), integral operation (I), and derivative operation (D). It produces superior control results even for control objects with dead time. It employs proportional operation to provide smooth control without hunting, integral operation to automatically correct any offset, and derivative operation to speed up the response to disturbances.
Section 5-21 Special Math Instructions • When it is not a problem if a certain amount of time is required for stabilization (settlement time), but it is important not to cause overshooting, then enlarge the proportional band. Control by measured PID SV When P is enlarged • When overshooting is not a problem but it is desirable to quickly stabilize control, then narrow the proportional band. If the proportional band is narrowed too much, however, then hunting may occur.
Section 5-21 Special Math Instructions Example This example shows a PID control program using PID(––). CPU Unit AD001 DA001 #0 #1 Amplifier (See note below.) Fan (Output word IR 111) Temperature sensing element (Output word IR 100) Amplifier (See note below.) Heater (Output word IR110) Note Motors and heaters cannot be directly connected from a Analog Output Unit. An amplifier (i.e., a current amplification circuit) is required. Creating the Program 1, 2, 3...
Section 5-21 Special Math Instructions Program 00000 25315 @MOV(21) #0F00 Target value DM0000 @MOV(21) DM0000 Parameter leading word for first PID(––) instruction HR00 @MOV(21) DM0000 HR40 PID(––) Parameter leading word for second PID(––) instruction PV of temperature sensing element 101 HR00 Heater operation amount 110 PID(––) 101 HR40 Fan operation amount 111 SCL 101 PV of temperature sensing element (binary) Leading word of converted parameter DM0100 DM0200 END 274 Present temperat
Section 5-22 Logic Instructions Note When using PID(––) or SCL(––), make the data settings in advance with a Peripheral Device such as the Programming Console or SSS.
Section 5-22 Logic Instructions Flags ER: Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.) EQ: ON when the result is 0. N: ON when bit 15 of Wd is set to 1.
Section 5-22 Logic Instructions 5-22-3 LOGICAL OR – ORW(35) Operand Data Areas I1: Input 1 Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # Description ORW(35) @ORW(35) I1 I1 I2 I2 R R I2: Input 2 IR, SR, AR, DM, HR, TC, LR, # R: Result word IR, SR, AR, DM, HR, LR When the execution condition is OFF, ORW(35) is not executed. When the execution condition is ON, ORW(35) logically OR’s the contents of I1 and I2 bitby-bit and places the result in R.
Section 5-22 Logic Instructions 5-22-4 EXCLUSIVE OR – XORW(36) Operand Data Areas I1: Input 1 Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # Description XORW(36) @XORW(36) I1 I1 I2 I2 R R I2: Input 2 IR, SR, AR, DM, HR, TC, LR, # R: Result word IR, SR, AR, DM, HR, LR When the execution condition is OFF, XORW(36) is not executed. When the execution condition is ON, XORW(36) exclusively OR’s the contents of I1 and I2 bit-by-bit and places the result in R.
Section 5-23 Subroutines and Interrupt Control 5-22-5 EXCLUSIVE NOR – XNRW(37) Operand Data Areas I1: Input 1 Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # XNRW(37) @XNRW(37) I1 I1 I2 I2 R R I2: Input 2 Description IR, SR, AR, DM, HR, TC, LR, # R: Result word IR, SR, AR, DM, HR, LR When the execution condition is OFF, XNRW(37) is not executed. When the execution condition is ON, XNRW(37) exclusively NOR’s the contents of I1 and I2 bit-by-bit and places the result in R.
Section 5-23 Subroutines and Interrupt Control INT(89) is used to control the interrupt signals received from the Interrupt Input Unit, and also to control the scheduling of the scheduled interrupt. INT(89) provides such functions as masking of interrupts (so that they are recorded but ignored) and clearing of interrupts. Refer to 5-23-2 Interrupts for more details on interrupts.
Section 5-23 Subroutines and Interrupt Control started. The program must be designed to allow for this when required by the application. (See the section on data concurrence for further details.) Input Interrupts Input interrupts are executed when external inputs are received via an Interrupt Input Unit. Up to two Interrupt Input Units can be mounted to the CPU Rack and each Interrupt Input Unit provides 8 inputs numbered IN 0 through IN7.
Section 5-23 Subroutines and Interrupt Control Note Disabling special I/O refreshing in the normal cycle to refresh special I/O in an interrupt subroutine is necessary only in the high-speed mode. Disabling normal cycle refreshing of special I/O during normal interrupt mode will be ignored and the special I/O will be refreshed both in the normal cycle and in the interrupt subroutine.
Section 5-23 Subroutines and Interrupt Control • Use the I/O REFRESH instruction in interrupt subroutines to refresh required I/O from Special I/O Units and mask interrupts in the main program while reading/writing Special I/O Unit words. 5-23-3 SUBROUTINE ENTER – SBS(91) Ladder Symbol Definer Data Areas N: Subroutine number SBS(91) N 000 to 255 Limitations Subroutine numbers 000 through 015 are used with input interrupts and subroutine number 099 is used for the scheduled interrupt.
Section 5-23 Subroutines and Interrupt Control The following diagram illustrates program execution flow for various execution conditions for two SBS(91).
Section 5-23 Subroutines and Interrupt Control All subroutines must be programmed at the end of the main program. When one or more subroutines have been programmed, the main program will be executed up to the first SBN(92) before returning to address 00000 for the next cycle. Subroutines will not be executed unless called by SBS(91). END(01) must be placed at the end of the last subroutine program, i.e., after the last RET(93). It is not required at any other point in the program.
Section 5-23 Subroutines and Interrupt Control In the following example, the contents of DM 0010 through DM 0013 are copied to SR 290 through SR 293, the contents of DM 0020 through DM 0023 are copied to SR 294 through SR 297, and subroutine 010 is called and executed. When the subroutine is completed, the contents of SR 294 through SR 297 are copied back to DM 0020 to DM 0023. Main program MCRO(99) 010 DM 0010 DM 0020 Main program SBN(92) 010 Subroutine RET(93) END(01) Note 1.
Section 5-23 Subroutines and Interrupt Control Example The following examples shows the use of four MCRO(99) instructions that access the same subroutine. The program section on the left shows the same program without the use of MCRO(99).
Section 5-23 Subroutines and Interrupt Control Description INT(89) is used to control interrupts and performs one of 11 functions depending on the values of C and N. As shown in the following tables, six of the functions act on input interrupts, three act on the scheduled interrupt, and the other two mask or unmask all interrupts.
Section 5-23 Subroutines and Interrupt Control Read Interrupt Interval (N=004, C=002) This function is used to write the current setting for the scheduled interrupt interval to word D. Mask/Unmasking All Interrupts (C=100/200) This function is used to mask or unmask all interrupt processing. Masked inputs are recorded, but ignored. The masked inputs will be serviced as soon as they are unmasked.
Section 5-23 Subroutines and Interrupt Control The scheduled interrupt is disabled at the start of operation (the scheduled interrupt interval is 0), so the time to the first interrupt and scheduled interrupt interval must be set using INT(89) with N=004 and C=001/000. In the following diagram, the subroutine would be executed every 20 ms if the scheduled interrupt time unit is set to 10 ms in DM 6622 of the PC Setup. Main program First Cycle Flag Sets the time to first interrupt to 20 ms.
Section 5-24 Step Instructions 5-24 Step Instructions The step instructions STEP(08) and SNXT(09) are used in conjunction to set up breakpoints between sections in a large program so that the sections can be executed as units and reset upon completion. A section of program will usually be defined to correspond to an actual process in the application. (Refer to the application examples later in this section.) A step is like a normal programming code, except that certain instructions (e.g.
Section 5-24 Step Instructions Execution of a step is completed either by execution of the next SNXT(09) or by turning OFF the control bit for the step (see example 3 below). When the step is completed, all of the IR and HR bits in the step are turned OFF. All timers in the step except TTIM(––) are reset to their SVs. TTIM(––), counters, shift registers, bits set or reset with SET or RSET, and bits used in KEEP(11) maintain status. Two simple steps are shown below.
Section 5-24 Step Instructions Flags 25407: Step Start Flag; turns ON for one cycle when STEP(08) is executed and can be used to reset counters in steps as shown below if necessary.
Section 5-24 Step Instructions The following diagram demonstrates the flow of processing and the switches that are used for execution control.
Section 5-24 Step Instructions The program for this process, shown below, utilizes the most basic type of step programming: each step is completed by a unique SNXT(09) that starts the next step. Each step starts when the switch that indicates the previous step has been completed turns ON. 00001 (SW1) SNXT(09) 12800 Process A started. STEP(08) 12800 Process A 00002 (SW2) SNXT(09) 12801 Process A reset. Process B started. STEP(08) 12801 Process B 00003 (SW3) SNXT(09) 12802 Process B reset.
Section 5-24 Step Instructions Example 2: Branching Execution The following process requires that a product is processed in one of two ways, depending on its weight, before it is printed. The printing process is the same regardless of which of the first processes is used. Various sensors are positioned to signal when processes are to start and end.
Section 5-24 Step Instructions The program for this process, shown below, starts with two SNXT(09) instructions that start processes A and B. Because of the way 00001 (SW A1) and 00002 (SB B1) are programmed, only one of these will be executed to start either process A or process B. Both of the steps for these processes end with a SNXT(09) that starts the step for process C. 00001 (SW A1) 00002 (SW B1) SNXT(09) HR 0000 00001 (SW A1) 00002 (SW B1) SNXT(09) HR 0001 STEP(08) HR 0000 Process A started.
Step Instructions Section 5-24 Example 3: Parallel Execution The following process requires that two parts of a product pass simultaneously through two processes each before they are joined together in a fifth process. Various sensors are positioned to signal when processes are to start and end. SW1 Process A SW3 SW5 SW7 Process B Process E Process D Process C SW2 SW4 SW6 The following diagram demonstrates the flow of processing and the switches that are used for execution control.
Section 5-24 Step Instructions 00001 (SW1 and SW2)) SNXT(09) LR 0000 Process A started. Process C started. SNXT(09) LR 0002 STEP(08) LR 0000 Process A 00002 (SW3) SNXT(09) LR 0001 Process A reset. Process B started. STEP(08) LR 0001 Process B LR 0003 LR 0003 Used to turn off process D. 00004 (SW5 and SW6) SNXT(09) LR 0004 Process E started. STEP(08) LR 0002 Process C 00003 (SW4) SNXT(09) LR 0003 Process C reset. Process D started.
Section 5-25 Special Instructions Address Instruction 00000 00001 00002 00003 LD SNXT(09) SNXT(09) STEP(08) Operands 00001 0000 0002 0000 LR LR LR LD SNXT(09) STEP(08) Instruction 00204 STEP(08) 00002 0001 0001 LR LR Operands LR 0002 LR LR 00003 0003 0003 LR 0004 LR 00005 0005 --- Process C 00300 00301 00302 Process A 00100 00101 00102 Address LD SNXT(09) STEP(08) Process D 00400 STEP(08) Process B Process E 00200 00201 00202 00203 LD OUT AND SNXT(09) LR 0003 LR 0003 00004 0004
Section 5-25 Special Instructions FAL(06) produces a non-fatal error and FAL(07) produces a fatal error. When FAL(06) is executed with an ON execution condition, the ALARM/ERROR indicator on the front of the CPU Unit will flash, but PC operation will continue. When FALS(07) is executed with an ON execution condition, the ALARM/ERROR indicator will light and PC operation will stop. The system also generates error codes to the FAL area.
Section 5-25 Special Instructions 5-25-3 TRACE MEMORY SAMPLING – TRSM(45) Data tracing can be used to facilitate debugging programs. To set up and use data tracing it is necessary to have a host computer running SSS; no data tracing is possible from a Programming Console. Data tracing is described in detail in the SSS Operation Manual. This section shows the ladder symbol for TRSM(45) and gives an example program.
Section 5-25 Special Instructions The sampled data is written to trace memory, jumping to the beginning of the memory area once the end has been reached and continuing up to the start marker. This might mean that previously recorded data (i.e., data from this sample that falls before the start marker) is overwritten (this is especially true if the delay is positive). The negative delay cannot be such that the required data was executed before sampling was started.
Section 5-25 Special Instructions In handling indirectly addressed messages (i.e. DM), those with the lowest DM address values have higher priority. Clearing Messages To clear a message, execute FAL(06) 00 or clear it via a Programming Console using the procedure in 4-6-5 Clearing Error Messages. If the message data changes while the message is being displayed, the display will also change. Indirectly addressed DM word is non-existent.
Section 5-25 Special Instructions Description LMSG(47) is used to output a 32-character message to a Programming Console. The message to be output must be in ASCII beginning in word S and ending in S+15, unless a shorter message is desired. A shorter message can be produced by placing a null character (0D) into the string; no characters from the null character on will be output. To output to the Programming Console, it must be set in TERMINAL mode.
Section 5-25 Special Instructions Example In the following example, TERM(48) is used to switch the Programming Console to TERMINAL mode when 00000 is ON. Be sure that pin 6 of the CPU Unit’s DIP switch is OFF.
Section 5-25 Special Instructions It cannot be used for other I/O words, such as I/O Units on Slave Racks or Group-2 High-density I/O Units. St must be less than or equal to E. Description To refresh I/O words allocated to CPU or Expansion I/O Racks (IR 000 to IR 029 or IR 300 to IR 309), simply specify the first (St) and last (E) I/O words to be refreshed. When the execution condition for IORF(97) is ON, all words between St and E will be refreshed.
Section 5-25 Special Instructions Refer to 6-1 Cycle Time for a table showing I/O refresh times for Group-2 High-density I/O Units. Flags ER: St or E is not BCD between #0000 and #000F. St is greater than E.
Section 5-25 Special Instructions The function of bits in C are shown in the following diagram and explained in more detail below. C: 15 14 13 12 11 00 Number of items in range (N, BCD) 001 to 999 words or bytes First byte (when bit 13 is ON) 1 (ON): Rightmost 0 (OFF): Leftmost Calculation units 1 (ON): Bytes 0 (OFF): Words Not used. Set to zero. Number of Items in Range The number of items within the range (N) is contained in the 3 rightmost digits of C, which must be BCD between 001 and 999.
Section 5-25 Special Instructions Example When IR 00000 is ON in the following example, the frame checksum (0008) is calculated for the 8 words from DM 0000 to DM 0007 and the ASCII equivalent (30 30 30 38) is written to DM 0011 and DM 0010.
Section 5-25 Special Instructions When the execution condition is OFF, FPD(––) is not executed. When the execution condition is ON, FPD(––) monitors the time until the logic diagnostics condition goes ON, turning ON the diagnostic output. If this time exceeds T, the following will occur: 1, 2, 3... 1. An FAL(06) error is generated with the FAL number specified in the first two digits of C. If 00 is specified, however, an error will not be generated. 2.
Section 5-25 Special Instructions D+1 contains the bit address code of the input condition, as shown below. The word addresses, bit numbers, and TC numbers are in binary.
Section 5-25 Special Instructions Example In the following example, the FPD(––) is set to display the bit address and message (“ABC”) when a monitoring time of 123.4 s is exceeded.
Section 5-25 Special Instructions 5-25-13 DATA SEARCH – SRCH(––) Ladder Symbols Operand Data Areas N: Number of words SRCH(––) @SRCH(––) N N R1 R1 C C IR, SR, AR, DM, HR, TC, LR, # R1: First word in range IR, SR, AR, DM, HR, TC, LR C: Comparison data, result word IR, SR, AR, DM, HR, LR Limitations N must be BCD between 0001 to 6656. R1 and R1+N–1 must be in the same data area. Description When the execution condition is OFF, SRCH(––) is not executed.
Section 5-25 Special Instructions Example In the following example, the 10 word range from DM 0010 to DM 0019 is searched for addresses that contain the same data as DM 0000 (#FFFF). Since DM 0012 contains the same data, the EQ Flag (SR 25506) is turned ON and #0012 is written to DM 0001.
Section 5-25 Special Instructions Example In the following example, the 100 word range from DM 7000 through DM 7099 is copied to DM 0010 through DM 0109 when IR 00001 is ON.
Section 5-25 Special Instructions Note Input 000 for the second and third operands when using replacement instructions. Flags ER: C is not one of the allowed values. Example In the following example, IEMS(––) changes the destination for DM to EM bank 1 and uses indirect addressing to move #1234 into EM 0001 in EM bank 1.
Section 5-26 Network Instructions 5-26 Network Instructions The network instructions are used for communicating with other PCs, BASIC Units, or host computers linked through the SYSMAC NET Link System, SYSMAC LINK System, Ethernet System, or Controller Link System.
Section 5-26 Network Instructions SYSMAC NET Link Systems The destination port number is always set to 0. Set the destination node number to 0 to send the data to all nodes. Set the network number to 0 to send data to a node on the same Subsystem (i.e., network). Refer to the SYSMAC NET Link System Manual for details. Word C C+1 Bits 00 to 07 Bits 08 to 15 Number of words (0 to 1000 in 4-digit hexadecimal, i.e.
Section 5-26 Network Instructions Controller Link Systems SEND(90) transmits “n” words beginning with S (the beginning source word for data transmission at the source node) to the “n” words beginning with D (the beginning destination word for data reception at destination node N).
Section 5-26 Network Instructions Indirect Destination Beginning Word Designations D is used to specify the destination beginning word as follows when indirect specification is designated: 12 to 15 D 08 to 11 00 to 03 0 D+1 Word no. (4th digit) SYSMAC NET Link Systems 04 to 07 Area type Word no. (3rd digit) Word no. (2nd digit) Word no. (5th digit) Word no. (1st digit) Indirect designations depend on the series of the destination PC. CV-series PCs Addresses in parentheses are for the CV500.
Section 5-26 Network Instructions C-series PCs Designation Area Controller Link Systems IR area Area code 00 Word number 0 to 511 LR area 06 0 to 63 HR area 07 0 to 99 SR area 08 0 to 27 Timer area (PV) 03 0 to 511 DM area 0 to 6655 05 CV-series PCs have a larger area than C200HX/HG/HE PCs, so the beginning words for sending and receiving at destination nodes cannot always be directly specified by means of SEND(192) and RECV(193) operands.
Section 5-26 Network Instructions Examples This example is for a SYSMAC NET Link System. When 00000 is ON, the following program transfers the content of IR 001 through IR 005 to LR 20 through LR 24 on node 10.
Section 5-26 Network Instructions Control Data Ethernet Systems Refer to the PC Card Unit Operation Manual for details. Word C C+1 Bits 00 to 07 Bits 08 to 15 Number of words (0 to 1000 in 4-digit hexadecimal, i.e., 0000hex to 03E8hex) Response time limit (0.1 and 25.4 Bits 08 to 11: seconds in 0.1 s increments in No. of retries (0 to 15 in 2-digit hexadecimal without hexadecimal, decimal point, i.e., 01hex to FFhex) i.e.
Section 5-26 Network Instructions Controller Link Systems RECV(98) receives “m” words beginning with S (the beginning word for data transmission at the destination node, M) to the words from D (the beginning word for data reception at the source node) onwards.
Section 5-26 Network Instructions 2. With the message service, there is no guarantee that a message to a destination node will reach its destination. It is always possible that the message may be lost in transit due to noise or some other condition. When using the message service, it is advisable to prevent this situation from occurring by performing resend processing at the node where instructions are issued.
Section 5-26 Network Instructions 5-26-3 About Network Communications SEND(90) and RECV(98) are based on command/response processing. That is, the transmission is not complete until the sending node receives and acknowledges a response from the destination node. Note that the SEND(90)/RECV(98) Enable Flag is not turned ON until the first END(01) after the transmission is completed. Refer to the SYSMAC NET Link System Manual or SYSMAC LINK System Manual for details about command/response operations.
Section 5-26 Network Instructions SEND(90)/RECV(98) Enable Flag 00000 25204 12802 S KEEP(11) 12801 12800 prevents execution of SEND(90) until RECV(98) (below) has completed. IR 00000 is turned ON to start transmission. 12800 R 12800 @MOV(21) #000A DM 0000 @MOV(21) #0000 DM 0001 @MOV(21) #0003 DM 0002 Data is placed into control data words to specify the 10 words to be transmitted to node 3 in operating level 1 of network 00 (NSB).
Section 5-27 Serial Communications Instructions Address Instruction 00000 00001 00002 00003 00004 00005 00006 LD AND AND NOT LD KEEP(11) LD @MOV(21) 00007 00008 00009 Operands # DM 000A 0000 # DM 0000 0001 # DM 0003 00002 Instruction Operands AND NOT LD KEEP(11) LD AND AND NOT XFER(70) 12800 12803 12802 12802 25204 25203 # DM @MOV(21) 00026 00027 LD @MOV(21) @MOV(21) 00028 0010 000 0002 00029 LD AND OUT LD AND DIFU(13) LD AND 00030 0010 0020 0000 12800 25203 00200 12800 25204 12801
Section 5-27 Serial Communications Instructions Note RXD(––) is required to receive data via the peripheral port or RS-232C port only. Transmission sent from a host computer to a Host Link Unit are processed automatically and do not need to be programmed. ! Caution Control Word The PC will be incapable of receiving more data once 256 bytes have been received if received data is not read using RXD(––).
Section 5-27 Serial Communications Instructions 26406: SR 26406 will be turned ON when data has been received normally at the peripheral port and will be reset when the data is read using RXD(––) is executed. 265: SR 265 contains the number of bytes received at the RS-232C port and is reset to 0000 when RXD(––) is executed. Note Communications flags and counters can be cleared either by specifying 0000 for N or using the Port Reset Bit (SR 25208 for peripheral port and SR 25209 for RS-232C port).
Section 5-27 Serial Communications Instructions Note Data is not output when the CTS and DSR signals are monitored. The specified number of bytes will be read from S through S+(N/2)–1, converted to ASCII, and transmitted through the specified port. The bytes of source data shown below will be transmitted in this order: 12345678... S S+1 S+2 S+3 MSB 1 3 5 7 LSB 2 4 6 8 The following diagram shows the format for host link command (TXD) sent from the PC.
Section 5-27 Serial Communications Instructions When digit 0 of C is 0, the bytes of source data shown above will be transmitted in this order: 12345678... When digit 0 of C is 1, the bytes of source data shown above will be transmitted in this order: 21436587... Note When start and end codes are specified the total data length should be 256 bytes max., including the start and end codes. Flags ER: Another device is not connected to the peripheral port.
Section 5-27 Serial Communications Instructions Application Example S Function Word address Constant (#0000) The contents of S through S+4 are copied to the part of the PC Setup that contains the settings for the port specified by N. The settings for the port specified by N are returned to their default values. This example shows a program that transfers the contents of DM 0100 through DM 0104 to the PC Setup area for Communications Board port A (DM 6555 through DM 6569).
Section 5-27 Serial Communications Instructions 5-27-4 PROTOCOL MACRO – PMCR(––) Operand Data Areas Ladder Symbols C: Control word PMCR(––) @PMCR(––) C C S S D D IR, SR, AR, DM, HR, TC, LR, # S: First output word IR, SR, AR, DM, HR, TC, LR, # D: First input word IR, SR, AR, DM, HR, TC, LR Limitations C must be BCD from #1000 to #2999. DM 6144 through DM 6655 cannot be used for D. Description When the execution condition is OFF, PMCR(––) is not executed.
Section 5-28 Advanced I/O Instructions Example When IR 00000 is ON and SR 28908 (the Communications Board Port A Instruction Execution Flag) is OFF, communications sequence 100 is called in the Communications Board and data is transferred through Communications Board port A. Send data is read from the range of words beginning at DM 0000 (the first output word) and reception data is stored in the range of words beginning at DM 0010 (the first input word).
Section 5-28 Advanced I/O Instructions Do not set C to values other than 000 to 007. Overview When the execution condition is OFF, 7SEG(––) is not executed. When the execution condition is ON, 7SEG(––) reads the source data (either 4 or 8-digit), converts it to 7-segment display data, and outputs that data to the 7-segment display connected to the output indicated by O.
Section 5-28 Advanced I/O Instructions play) will be turned ON when one round of data is displayed, but there is no need to connect them unless required by the application. D0 D1 D2 D3 LE3 LE2 VDD (+) VSS (0) LE1 LE0 VDD (+) VSS (0) LE3 LE2 LE1 D0 D1 D2 D3 LE0 OD212 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DC COM The outputs must be connected from an Output Unit with 8 or more output points for four digits or 16 or more output points for eight digits.
Section 5-28 Advanced I/O Instructions Timing The timing of data output is shown in the following table. “O” is the first word holding display data and “C” is the output word.
Section 5-28 Advanced I/O Instructions Overview DSW(––) is used to read the value set on a digital switch connected to I/O Units. When the execution condition is OFF, DSW(––) is not executed. When the execution condition is ON, DSW(––) reads the 8-digit value set on the digital switch from IW and places the result in R. The 8-digit value it is placed in R and R+1, with the most significant digits placed in R+1.
Section 5-28 Advanced I/O Instructions The following example illustrates connections for an A7B Thumbwheel Switch. ID212 Input Unit 0 1 2 3 4 5 6 7 8 9 A7B Thumbwheel Switch 10 11 12 8 4 2 1 13 14 OD212 15 COM COM Switch no. 8 7 6 5 4 3 2 1 C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Output Unit 15 DC COM Note The data read signal is not required in the example.
Section 5-28 Advanced I/O Instructions Using the Instruction If the input word for connecting the digital switch is specified at for word A, and the output word is specified for word B, then operation will proceed as shown below when the program is executed. IW Four digits: 00 to 03 100 101 102 Input data Leftmost 4 digits 103 Eight digits: 00 to 03, 04 to 07 Wd 0 D+1 Rightmost 4 digits D 00 When only 4 digits are read, only word D is used.
Section 5-28 Advanced I/O Instructions 5-28-3 HEXADECIMAL KEY INPUT – HKY(––) Ladder Symbols Operand Data Areas IW: Input word HKY(––) IR, SR, AR, DM, HR, LR IW OW: Control signal output word OW D IR, SR, AR, DM, HR, LR D: First register word IR, SR, AR, DM, HR, LR Limitations D and D+2 must be in the same data area. Overview When the execution condition is OFF, HKY(––) is not executed.
Section 5-28 Advanced I/O Instructions Hardware This instruction inputs 8 digits in hexadecimal from a hexadecimal keyboard. It utilizes 5 output bits and 4 input bits. Prepare the hexadecimal keyboard, and connect the 0 to F numeric key switches, as shown below, to input points 0 through 3 and output points 0 through 3. Output point 4 will be turned ON while any key is being pressed, but there is no need to connect it unless required by the application.
Section 5-28 Advanced I/O Instructions Using the Instruction If the input word for connecting the hexadecimal keyboard is specified at word A, and the output word is specified at word B, then operation will proceed as shown below when the program is executed. IW 00 01 02 03 16-key 0 to 9 to F 16-key selection control signals Status of 16 keys D+2 00 to 09 to 15 OW 04 Turn ON flags corresponding to input keys (The flags remain ON until the next input.) ON for a 12-cycle period if a key is pressed.
Section 5-28 Advanced I/O Instructions 5-28-4 TEN KEY INPUT – TKY(––) Ladder Symbols Operand Data Areas IW: Input word TKY(––) IR, SR, AR, DM, HR, LR IW D1: First register word D1 IR, SR, AR, DM, HR, LR D2 D2: Key input word IR, SR, AR, DM, HR, LR Limitations D1 and D1+1 must be in the same data area. Overview When the execution condition is OFF, TKY(––) is not executed. When the execution condition is ON, TKY(––) inputs data from a ten-key keypad connected to the input indicated by IW.
Section 5-28 Advanced I/O Instructions Using the Instruction If the input word for connecting the 10-key keypad is specified for IW, then operation will proceed as shown below when the program is executed. IW D1+1 00 01 02 D1 Before execution 0 0 0 0 0 0 0 0 (1) 0 0 0 0 0 0 0 1 Input from 10-key to 09 “1” key input D2 (2) 00 0 0 0 0 0 01 Turn ON flags corresponding to 10-key inputs (The flags remain ON until the next input.
Section 5-28 Advanced I/O Instructions 5-28-5 MATRIX INPUT – MTR(––) Ladder Symbols Operand Data Areas IW: Input word MTR(––) IR, SR, AR, DM, HR, LR IW OW: Output word OW IR, SR, AR, DM, HR, LR D D: First destination word IR, SR, AR, DM, HR, LR Limitations D and D+3 must be in the same data area. Overview When the execution condition is OFF, MTR(––) is not executed. When the execution condition is ON, MTR(––) inputs data from an 8 × 8 matrix and records that data in D to D+3.
Section 5-28 Advanced I/O Instructions Hardware This instruction inputs up to 64 signals from an 8 x 8 matrix using 8 input points and 8 output points. Any 8 x 8 matrix can be used. The inputs must be connected through a DC Input Unit with 8 or more points and the outputs must be connected through a Transistor Output Unit with 8 or more points. The basic wiring and timing diagrams for MTR(––) are shown below.
Section 5-29 Special I/O Unit Instructions Example The following examples shows programming MTR(––) in a scheduled subroutine, where IORF(97) is programmed to ensure that the I/O words used by MTR(––) are refreshed each time MTR(––) is executed. INT(89) 001 004 # 0002 INT(89) 000 004 # 0002 SBN(92) 99 MTR(––) S D1 D2 IORF(97) D1 D2 RET(93) END(01) Flags Indirectly addressed DM word is non-existent. (Content of DM word is not BCD, or the DM area boundary has been exceeded.
Section 5-29 Special I/O Unit Instructions Description When the execution condition is OFF, IORD(––) is not executed. When the execution condition is ON, IORD(––) transfers data from the specified Special I/O Unit’s memory to words beginning at D. The source information provides the node number of the Special I/O Unit and the number of words to be read, as shown in the following diagram.
Section 5-29 Special I/O Unit Instructions Description When the execution condition is OFF, IOWR(––) is not executed. When the execution condition is ON, IOWR(––) transfers data from the words beginning at D to the specified Special I/O Unit’s memory. The destination information provides the node number of the Special I/O Unit and the number of words to be written, as shown in the following diagram.
Section 5-29 Special I/O Unit Instructions 5-29-3 PCMCIA CARD MACRO – CMCR(––) Operand Data Areas Ladder Symbols C: First control word CMCR(––) @CMCR(––) C C S S D D IR, SR, AR, DM, HR, TC, LR, # S: First command word IR, SR, AR, DM, HR, TC, LR, # D: Response word IR, SR, AR, DM, HR, TC, LR Limitations DM 6144 through DM 6655 cannot be used for D. Description When the execution condition is OFF, CMCR(––) is not executed.
Section 5-29 Special I/O Unit Instructions Process Number The process number (1 through 4) determines what function CMCR(––) will perform. Process number 1 Process name Write file 2 Read file 3 Compare file with memory Search file 4 Port Settings Process number Function Writes data from the PC’s memory to the specified file in the Card in the PC Card Unit. Reads data from the specified file in the Card in the PC Card Unit to the PC’s memory.
Section 5-29 Special I/O Unit Instructions The data length, offset, and command data settings depend on the process number that is specified, as shown in the following table. Process number 1 Data length Offset Number of words of data (BCD: 1 to 1001) Command data Number of elements of write data (0 to FFFF) Data to be written to the file Specify number of words for one-word comma delimiter and binary. Specify number of elements for two-word comma delimiter. 2 3 Always set to 0003.
Section 5-29 Special I/O Unit Instructions SR Bits and the Termination Code The instruction’s termination code is output to SR 237 after CMCR(––) is executed. Also, SR 252 contains flags that indicate the instruction’s completion status (normal/error) and the execution status for operating levels 0 and 1. The following table shows the function of these bits. Word Bit(s) Function SR 237 00 to 07 Termination code output area for operating level 0 after execution of CMCR(––).
Section 5-29 Special I/O Unit Instructions DM 0000 to DM 0007 contain the control data and DM 0098 to DM 0199 contain the command data, as shown below. Word Content Function DM 0000 --- Control data DM 0001 47 3A ASCII: “G :” DM 0002 5C 44 ASCII: “\ D” DM 0003 4D 53 ASCII: “M S” DM 0004 41 56 ASCII: “A V” DM 0005 45 2E ASCII: “E .
SECTION 6 Program Execution Timing The timing of various operations must be considered both when writing and debugging a program. The time required to execute the program and perform other CPU Unit operations is important, as is the timing of each signal coming into and leaving the PC in order to achieve the desired control action at the right time. This section explains the cycle and shows how to calculate the cycle time and I/O response times. 6-1 6-2 6-3 6-4 Cycle Time . . . . . . . . . . . . . . . . .
Cycle Time 6-1 Section 6-1 Cycle Time To aid in PC operation, the average, maximum, and minimum cycle times can be displayed on the Programming Console or any other Programming Device and the maximum cycle time and current cycle time values are held in AR 26 and AR 27. Understanding the operations that occur during the cycle and the elements that affect cycle time is, however, essential to effective programming and PC operations.
Section 6-1 Cycle Time Flowchart of CPU Unit Operation Power application Clears IR area and resets all timers Initialization on power-up Checks I/O Unit connections Resets watchdog timer Checks hardware and Program Memory NO Overseeing processes Check OK? YES Resets watchdog timer and program address counter Sets error flags and turns ON or flashes indicator ERROR (Solid ON) Program execution Executes user program ALARM/ERROR ALARM (Flashing) End of program? Note A minimum cycle time can b
Section 6-1 Cycle Time The first three operations immediately after power application are performed only once each time the PC is turned on. The rest of the operations are performed in cyclic fashion. The cycle time is the time that is required for the CPU Unit to complete one of these cycles.
Section 6-1 Cycle Time PC Link Unit I/O Refresh I/O pts to refresh Time required (ms) Special I/O Unit Refresh 512 7.4 256 4.1 128 2.7 64 1.
Section 6-2 Calculating Cycle Time Watchdog Timer and Long Cycle Times Within the PC, the watchdog timer measures the cycle time and compares it to a set value. If the cycle time exceeds the set value of the watchdog timer, a FALS 9F error is generated and the CPU Unit stops. WDT(94) can be used to extend the set value for the watchdog timer.
Section 6-2 Calculating Cycle Time 6-2-1 PC with I/O Units Only Here, we’ll compute the cycle time for a simple PC. The CPU Unit controls only I/O Units, eight on the CPU Rack and five on a 5-slot Expansion I/O Rack. The PC configuration for this would be as shown below. It is assumed that the program contains 5,000 instructions requiring an average of 0.156 µs each to execute.
Section 6-2 Calculating Cycle Time It is assumed that the program contains 5,000 instructions requiring an average of 0.156 µs each to execute, and that nothing is connected to the RS-232C port and no SYSMAC NET/SYSMAC LINK Unit is mounted.
Section 6-3 Instruction Execution Times 6-3 Instruction Execution Times The following table lists the execution times for all instructions that are available for the C200HX/HG/HE. The maximum and minimum execution times and the conditions which cause them are given where relevant. When “word” is referred to in the Conditions column, it implies the content of any word except for indirectly addressed DM words.
Section 6-3 Instruction Execution Times Instruction Conditions ON execution time (µs) OFF execution time (µs) C200HX C200HG C200HE C200HX C200HG C200HE JMP(04) --- 7.65 22.35 0.313 0.469 0.938 JME(05) --- 7.95 22.65 0.313 0.469 0.938 FAL(06) FAL numbers 01 to 99 FAL number 00 88.6 86.6 88.6 86.6 0.313 0.313 0.469 0.469 0.938 0.938 FALS(07) --- --- (see note 2) 0.313 0.469 0.938 STEP(08) --- 33.1 47.8 0.313 0.469 0.938 15.3 30 SNXT(09) --- 9.25 23.95 0.313 0.
Section 6-3 Instruction Execution Times Instruction ASR(26) ROL(27) ROR(28) COM(29) ADD(30) SUB(31) MUL(32) DIV(33) ANDW(34) ORW(35) XORW(36) XNRW(37) INC(38) DEC(39) Conditions ON execution time (µs) OFF execution time (µs) C200HX C200HG C200HE C200HX C200HG C200HE When shifting a word 11.95 26.65 When shifting DM 22.95 37.65 When rotating a word 13.15 27.85 When rotating DM 24.25 38.95 When rotating a word 13.15 27.85 When rotating DM 24.25 38.95 When inverting a word 11.
Section 6-3 Instruction Execution Times Instruction Conditions ON execution time (µs) OFF execution time (µs) C200HX C200HG C200HE C200HX C200HG C200HE Constant × word → word 16.95 31.65 Word × word → word 17.85 32.55 DM × DM → DM 49.3 64 Word ÷ constant → word 17.15 31.85 Word ÷ word → word 18.05 32.75 DM ÷ DM → DM 49.7 64.4 Word + word → word 22.45 37.15 DM + DM → DM 53.9 68.6 Word – word → word 22.45 37.15 DM – DM → DM 53.9 68.6 Word × word → word 110.
Section 6-3 Instruction Execution Times Instruction SDEC(78) FDIV(79) DIST(80) COLL(81) Conditions ON execution time (µs) OFF execution time (µs) C200HX C200HG C200HE C200HX C200HG C200HE When decoding a word to a word 26.95 41.65 When decoding 2 digits DM to DM 63.3 78 When decoding 4 digits DM to DM 71.7 86.4 Word ÷ word → word (equals 0) 62.3 77 Word ÷ word → word (doesn’t equal 0) 499 513.7 DM ÷ DM → DM 843 857.7 Constant → (word + (word)) 27.65 42.
Section 6-3 Instruction Execution Times Instruction LMSG(––) Conditions ON execution time (µs) OFF execution time (µs) C200HX C200HG C200HE C200HX C200HG C200HE Word for SV 17.95 32.65 Default: (47) DM for SV 27.65 42.35 TERM(––) --Default: (48) 8.55 CMPL(––) When comparing words to words 0.313 0.469 0.938 23.25 0.313 0.469 0.938 0.313 0.469 0.938 0.313 0.469 0.938 0.313 0.469 0.938 0.313 0.469 0.938 0.313 0.469 0.938 0.313 0.469 0.938 0.313 0.469 0.938 16.55 31.
Section 6-3 Instruction Execution Times Instruction TXD(––) Conditions ON execution time (µs) OFF execution time (µs) C200HX C200HG C200HE C200HX C200HG C200HE When designating a word 56.1 70.8 When designating DM 99.4 114.1 Word-designated 4 digits 19 to 22 (see note 2) DM-designated 4 digits 30 to 34 (see note 2) Word-designated 8 digits 19 to 22 (see note 2) DM-designated 8 digits 30 to 34 (see note 2) Word designation, code output 74.60 to 89.
Section 6-3 Instruction Execution Times Instruction MBS(––) DBS(––) MBSL(––) Conditions ON execution time (µs) OFF execution time (µs) C200HX C200HG C200HE C200HX C200HG C200HE Constant × word → word 20.85 35.55 DM × DM → DM 21.65 36.35 DM × DM → DM 53.5 68.2 Constant ÷ word → word 21.55 36.25 DM ÷ DM → DM 22.45 37.15 DM ÷ DM → DM 54.9 69.6 DM × DM → DM 45.3 60 0.313 0.469 0.938 0.313 0.469 0.938 0.313 0.469 0.938 DM × DM → DM 77.1 91.
Section 6-3 Instruction Execution Times Instruction IEMS(––) Conditions ON execution time (µs) OFF execution time (µs) C200HX C200HG C200HE C200HX C200HG C200HE IORD(––) Constant designation (Switch to DM.) Word designation (Switch to EM bank.) --- 19.25 24.
Section 6-4 I/O Response Time 6-4 I/O Response Time The I/O response time is the time it takes for the PC to output a control signal after it has received an input signal. The time it takes to respond depends on the cycle time and when the CPU Unit receives the input signal relative to the input refresh period.
Section 6-4 I/O Response Time Maximum I/O Response Time The PC takes longest to respond when it receives the input signal just after the I/O refresh phase of the cycle. In this case the CPU Unit does not recognize the input signal until the end of the next cycle. The maximum response time is thus one cycle longer than the minimum I/O response time, except that the I/O refresh time would not need to be added in because the input comes just after it rather than before it.
Section 6-4 I/O Response Time In looking at the following timing charts, it is important to remember the sequence in which processing occurs during the PC scan, particular that inputs will not produce programmed actions until the program has been executed. When calculating the response times involving inputs and outputs from another CPU Unit connected by an I/O Link Unit, the cycle time of the controlling CPU Unit and the cycle time of the PC to which the I/O Link Unit is mounted must both be considered.
Section 6-4 I/O Response Time Maximum I/O Response Time The maximum response time occurs when the input just misses the program execution portion of the scan, meaning that processing must wait for the next transmission and then the next (i.e., the fourth) scan. Time = Input ON delay + cycle time × 4 + output ON delay Cycle time > Remote I/O transmission times Note Use the maximum cycle time output to AR 26 in computing the maximum I/O response time.
Section 6-4 I/O Response Time 6-4-3 Host Link Systems The following diagram illustrates the processing that takes place when an input on one PC is transferred through the Host Link System to turn ON an output on another PC. Refer to Host Link System documentation for further details.
Section 6-4 I/O Response Time In looking at the following timing charts, it is important to remember the sequence processing occurs during the PC scan, particular that inputs will not produce programmed-actions until the program has been execution. Unit 0 PC Link Unit PC Link Unit PC PC Input on PC of Unit 0 Input LR bit Output on PC of Unit 7 Unit 7 X Output X Input LR XXXX LR XXXX Output X Note Noise may increase I/O delays.
Section 6-4 I/O Response Time Output ON delay: Cycle time for PC of Unit 0: Cycle time for PC of Unit 7: Minimum transmission time: Maximum Response Time 15 ms 20 ms 50 ms 2.8 ms+10 ms=12.8 ms The following diagram illustrates the data flow that will produce the maximum response time. Delays occur because signals or data is received just after they would be processed or because data is sent during processing. In either case, processing must wait until the next scan/polling cycle.
Section 6-4 I/O Response Time Reducing Response Time I/O refresh bits for Unit 0 256 I/O refresh bits for Unit 7 256 IORF(97) can be used in programming to shorten the I/O response time greater than is possible by setting a high number of refresh bits. (Remember, increasing the number of refresh bits set on the back-panel LED shortens response time, but increases the cycle time of the PC.
Section 6-4 I/O Response Time The minimum and maximum I/O response times are shown here, using as an example the following instructions executed at the master and the slave. In this example, communications proceed from the master to the slave. Output (LR) Input (LR) Input Output The following conditions are taken as examples for calculating the I/O response times.
Section 6-4 I/O Response Time 3. Communications are completed just after the slave executes communications servicing. Input point I/O refresh Input ON delay Overseeing, communications, etc.
Section 6-4 I/O Response Time Scheduled Interrupts Scheduled interrupt interval Hardware time clock Scheduled interrupt subroutine execution t3 t3 t3 t3 t3 = Software interrupt response time Total interrupt response time = t3 (software interrupt response time) The software interrupt response time depends on the interrupt response parameter setting in DM 6620 of the PC Setup. If the DM 6620 is set for the C200Hcompatible mode (0000), the software interrupt response time is less than 10 ms.
Section 6-4 I/O Response Time The interrupt return time is 0.04 ms. Note Interrupt Input Pulse Width 1. If there are several elements that can cause interrupts or if the interrupt period is shorted than the average interrupt processing time, the interrupt subroutine will be executed and the main program will not be executed. This will cause the cycle monitoring time to be exceeded and an FALS 9F error will be generated, stopping PC operation. 2.
SECTION 7 Program Monitoring and Execution This section provides the procedures for monitoring and controlling the PC through a Programming Console. Refer to the SYSMAC Support Software Operation Manual for SSS procedures if you are using a computer running SSS. 7-1 7-2 Monitoring Operation and Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Console Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Console Operations 7-1 Section 7-2 Monitoring Operation and Modifying Data The simplest form of operation monitoring is to display the address whose operand bit status is to be monitored using the Program Read or one of the search operations. As long as the operation is performed in RUN or MONITOR mode, the status of any bit displayed will be indicated. This section provides other procedures for monitoring data as well as procedures for modifying data that already exists in a data area.
Section 7-2 Programming Console Operations Key Sequence Clears leftmost address Cancels monitor operation (EM area) (EM bank 0, 1, or 2.) Examples The following examples show various applications of this monitor operation.
Section 7-2 Programming Console Operations Bit Monitor 00000 00000 LD 00001 00001 ^ ON 00000 CONT 00001 Note The status of TR bits SR flags SR 25503 to 25507 (e.g., the arithmetic flags), cleared when END(01) is executed, cannot be monitored. Word Monitor 00000 00000 CHANNEL 00000 CHANNEL 000 LR 01 cL01 FFFF cL00 0000 EM Area Word Monitor 00000 00000 CHANNEL e0Ć0000 00000 CHANNEL e1Ć0100 e0100 10000 392 Specify the EM bank and address to be monitored.
Section 7-2 Programming Console Operations Multiple Address Monitoring 00000 00000 TIM 000 T000 0100 00000 T000 0100 00001 T000 0100 00001 T000 OFF 0100 D000000001 T000 ^OFF 0100 D000000001 T000 10FF^ OFF 0100 T000D000000001 0100 10FF^ OFF D000000001 10FF^ OFF Cancels monitoring of leftmost address 00001 ^ OFF 00000 CONT 00000 CHANNEL 00001 DM 0000 Monitor operation is cancelled 0000000001 S ONR OFF Indicates Force Reset in operation. Indicates Force Set in operation.
Section 7-2 Programming Console Operations Bit status will remain ON or OFF only as long as the key is held down; the original status will return as soon as the key is released. If a timer is started, the completion flag for it will be turned ON when SV has been reached. SHIFT and PLAY/SET or SHIFT and REC/RESET can be pressed to maintain the status of the bit after the key is released. The bit will not return to its original status until the NOT key is pressed, or one of the following conditions is met.
Section 7-2 Programming Console Operations The following displays show what happens when TIM 000 is set with 00100 OFF (i.e., 00500 is turned ON) and what happens when TIM 000 is reset with 00100 ON (i.e., timer starts operation, turning OFF 00500, which is turned back ON when the timer has finished counting down the SV). (This example is performed in MONITOR mode.) 0010000500 ^ OFF^ OFF Monitoring 00100 and 00500. 0010000500 ON^ OFF Force set bit status.
Section 7-2 Programming Console Operations Example The following example shows the displays that appear when Restore Status is carried out normally. 00000 00000 00000FORCE RELE? 00000FORCE RELE END 7-2-4 Hexadecimal/BCD Data Modification When the Bit/Digit Monitor operation is being performed and a BCD or hexadecimal value is leftmost on the display, CHG can be input to change the value. SR words cannot be changed.
Section 7-2 Programming Console Operations Example The following example shows the effects of changing the PV of a timer. This example is in MONITOR mode 00000 00000 TIM 000 Monitor status of timer PV that will be changed. T000 0122 Timing PRES VAL? T000 0119 ???? PV decrementing Timing PRES VAL? T000 0100 0200 Timing T000 0199 PV changed. Timer/counter PVs can be changed even when the timer/counter is operating.
Section 7-2 Programming Console Operations 7-2-5 Hex/ASCII Display Change This operation converts DM data displays from 4-digit hexadecimal data to ASCII and vice versa. Key Sequence Word currently displayed. Example 00000 00000 CH DM 0000 Monitor the desired DM word. D0000 4412 398 D0000 "AB" Press TR to change the display to ASCII code. D0000 4142 Press TR again to return the display to hexadecimal.
Section 7-2 Programming Console Operations 7-2-6 4-digit Hex/Decimal Display Change This operation converts data displays from normal or signed 4-digit hexadecimal data to decimal and vice versa. Decimal values from 0 to 65,535 are valid when inputting normal 4-digit hexadecimal data, and decimal values from –32,768 to +32,767 are valid when inputting signed 4-digit hexadecimal data. Key Sequence Single word or 3-word monitor currently displayed. [New data] TR TR Clear new input data.
Section 7-2 Programming Console Operations 7-2-7 8-digit Hex/Decimal Display Change This operation converts data displays from normal or signed, 4 or 8-digit hexadecimal data to decimal and vice versa. Decimal values from 0 to 4,294,967,295 are valid when inputting normal 8-digit hexadecimal data, and decimal values from –2,147,483,648 to +2,147,483,647 are valid when inputting signed 8-digit hexadecimal data. Key Sequence 3-word monitor currently displayed. [New data] TR TR Clear new input data.
Section 7-2 Programming Console Operations 7-2-8 Differentiation Monitor This operation can be used to monitor the up or down differentiation status of bits in the IR, SR, AR, LR, HR, and TC areas. To monitor up or down differentiation status, display the desired bit leftmost on the bit monitor display, and then press SHIFT and the Up or Down Arrow Key. A CLR entry changes the Differentiation Monitor operation back to a normal bit monitor display.
Section 7-2 Programming Console Operations 7-2-9 3-word Monitor To monitor three consecutive words together, specify the lowest numbered word, press MONTR, and then press EXT to display the data contents of the specified word and the two words that follow it. A CLR entry changes the Three-word Monitor operation to a single-word display. Key Sequence Single-word monitor in progress Example 00000 00000 CHANNEL DM 0000 Specify the first of the 3 words you want to monitor.
Section 7-2 Programming Console Operations Example D0002D0001D0000 0123 4567 89AB 3-word Monitor in progress. D0002 3CH CHG? 0123 4567 89AB Stops in the middle of monitoring. D0002 3CH CHG? 0001 4567 89AB Input new data. D0002 3CH CHG? 0001 4567 89AB D0002 3CH CHG? 0001 2345 89AB D0002D0001D0000 0001 2345 89AB D0002D0001D0000 0123 4567 89AB 7-2-11 Resumes previous monitoring.
Section 7-2 Programming Console Operations Example 00000 00000 CHANNEL 000 c000 MONTR 0000000000001111 c001 MONTR 0000010101010100 00000 CHANNEL 001 00000 00000 CHANNEL DM 0000 D0000 FFFF D0000 MONTR 1111111111111111 D0000 FFFF 00000 CHANNEL DM 0000 0000S0100R0110SR Indicates Force Reset in effect Indicates Force Set in effect 404
Programming Console Operations Section 7-2 7-2-12 Binary Data Modification This operation assigns a new 16-digit binary value to an IR, HR, AR, DM, EM, or LR word. The cursor, which can be shifted to the left with the up key and to the right with the down key, indicates the position of the bit that can be changed. After positioning to the desired bit, a 0 or a 1 can then be entered as the new bit value. The bit can also be Force Set or Force Reset by pressing SHIFT and either PLAY/SET or REC/RESET.
Section 7-2 Programming Console Operations Example 00000 00000 CHANNEL 000 00000 CHANNEL 001 c001 MONTR 0000010101010101 c001 CHG? 000010101010101 c001 CHG? 1 00010101010101 c001 CHG? 10 0010101010101 c001 CHG? 100 010101010101 c001 CHG? 100S 10101010101 c001 CHG? 100 010101010101 c001 CHG? 10 S010101010101 c001 CHG? 1 RS010101010101 c001 MONTR 10RS010101010101 IR bit 00115 IR bit 00100 7-2-13 Changing Timer/Counter SV There are two ways to change the SV of a timer or counter.
Section 7-2 Programming Console Operations Key Sequence Example Inputting New SV and Changing to Word Designation The following examples show inputting a new constant, changing from a constant to an address, and incrementing to a new constant.
Section 7-2 Programming Console Operations Incrementing and Decrementing 00000 00000 TIM 000 00201SRCH TIM 000 00201 TIM DATA #0123 00201 TIM DATA T000 #0123 #???? 00201DATA ? U/D T000 #0123 #0123 Current SV (during change operation) SV before the change 00201DATA ? T000 #0123 #0122 00201DATA ? T000 #0123 #0123 00201DATA ? T000 #0123 #0124 00201DATA ? T000 #0124 #???? 00201 TIM 408 DATA #0124 Returns to original display with new SV
Section 7-2 Programming Console Operations 7-2-14 Expansion Instruction Function Code Assignments This operation is used to read or change the function codes assigned to expansion instructions. There are 18 function codes that can be assigned to expansion instructions: 17, 18, 19, 47, 48, 60 to 69, and 87 to 89. More than one function code can be assigned to an expansion instruction. Note Function Code Assignments can be read in any mode, but can be changed in PROGRAM mode only.
Section 7-2 Programming Console Operations 7-2-15 UM Area Allocation This operation is used to allocate part of the UM Area for use as expansion DM. It can be performed in PROGRAM mode only. Memory allocated to expansion DM is deducted from the ladder program area. The amount of memory available for the ladder program depends on the amount of RAM in the CPU Unit. About 15.2 KW of memory is available with the16-KW RAM and about 31.2 KW is available with the 32-KW RAM.
Section 7-2 Programming Console Operations 7-2-16 Reading and Setting the Clock This operation is used to read or set the CPU Unit’s clock. The clock can be read in any mode, but it can be set in MONITOR or PROGRAM mode only. The CPU Unit will reject entries outside of the acceptable range, i.e., 01 to 12 for the month, 01 to 31 for the day of the month, 00 to 06 for the day of the week, or 00 to 60 for the seconds, but it will not recognize non-existent dates, such as 2/31.
Section 7-2 Programming Console Operations To enable expansion keyboard mapping, pin 6 of the CPU Unit’s DIP switch and AR 0709 must be ON and AR 0708 must be OFF. Bits turned ON with this operation can be turned OFF by toggling AR 0708. Turn AR 0709 OFF to stop expansion keyboard mapping and switch the Programming Console from Expansion TERMINAL mode to CONSOLE mode. TERMINAL Mode The Programming Console can be put into TERMINAL mode by pressing CHG or executing TERM(48) in the program.
Section 7-2 Programming Console Operations With keyboard mapping, bits 00 to 15 of AR 22 will be turned ON when keys 0 to F are pressed on the Programming Console’s keyboard. A bit will remain ON after the Programming Console’s key is released. All bits in AR 22 will be turned OFF when AR 0708 is turned ON. Keyboard mapping inputs are disabled when AR 0708 is ON.
Section 7-2 Programming Console Operations SR word 277 Bit 03 *1 04 *2 05 06 07 08 09 10 11 12 13 14 15 278 00 01 02 03 04 05 06 07 08 09 10 414 Corresponding key(s)
Section 7-2 Programming Console Operations SR word 278 Bit Corresponding key(s) 11 12 13 14 15 279 00 01 02 03 04 05 *3 06 07 VER 08 09 415
SECTION 8 Serial Communications This section provides an overview of the serial communications (Host Link, RS-232C, one-to-one links, NT links, and protocol macros) that operate through the RS-232C, RS-422/485, and Peripheral Ports. 8-1 8-2 8-3 8-4 8-5 8-6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Link Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 8-1 Introduction 8-1 Introduction The RS-232C port and peripheral port built into the C200HX/HG/HE PC’s CPU Unit support the following communications functions: • Communications with Programming Devices (e.g., Programming Console or SSS.) • Host Link communications with personal computers and other external devices. • RS-232C (no-protocol) communications with personal computers and other external devices. • One-to-one link communications with another PC.
Host Link Communications 8-2 Section 8-2 Host Link Communications 8-2-1 Host Link Command Summary Host Link communications are used to transfer data between the PC and a host computer (a personal computer or PT). It is possible to monitor the PC’s operating status and the contents of PC data areas from the host computer using Host Link commands.
Host Link Communications Section 8-2 The connections between the C200HX/HG/HE and a personal computer are illustrated below as an example. C200HX/HG/HE Personal computer Signal Pin No. Pin No. Signal FG 1 1 – SD 2 2 RD RD 3 3 SD RS 4 4 DTR CS 5 5 SG – 6 6 DSR – 7 7 RS – 8 8 CS SG 9 9 – Shielded cable Applicable Connectors The following connectors are applicable. One plug and one hood are included with the CPU Unit.
Host Link Communications Section 8-2 Custom Port Settings Standard settings or custom settings can be used for the RS-232C and peripheral ports. The custom settings are used when the following bits are set to 1. RS-232C port: Bits 00 through 03 of DM 6645 (0: standard; 1: custom). Peripheral port: Bits 00 through 03 of DM 6650 (0: standard; 1: custom). The custom settings for the RS-232C port are defined in DM 6646 and the custom settings for the peripheral port are defined in DM 6651.
Host Link Communications Section 8-2 Note If pin 5 of the CPU Unit’s DIP switch is ON, the standard communications settings will be used regardless of the settings in the PC Setup.
Host Link Communications Response Frame Format @ The response from the PC is returned in the format shown below. Prepare a program so that the response data can be interpreted and processed. x 101 x 100 Node no. Section 8-2 x 161 x 160 Header code ↵ End code Text FCS Terminator The header code and text depend on the Host Link command that was received. The end code indicates the completion status of the command (e.g., whether or not an error has occurred).
Host Link Communications Communications Sequence Section 8-2 The right to send a frame is called the “transmission right.” The Unit that has the transmission right is the one that can send a frame at any given time. The transmission right is traded back and forth between the host computer and the PC each time a frame is transmitted. An example communications sequence between the host computer and PC is described below.
Host Link Communications Section 8-2 8-2-3 Example Programs Command Transmission The following type of program must be prepared in the host computer to receive the data. This program allows the computer to read and display the data received from the PC while a host link read command is being executed to read data from the PC.
RS-232C Communications Section 8-3 The default values are assumed for all of the PC Setup (i.e., the RS-232C port is used in Host Link mode, the node number is 00, and the standard communications parameters are used.) 00100 SR 26405 @TXD DM 0000 #0000 #0010 8-3 If SR 26405 (the Transmit Ready Flag) is ON when IR 00100 turns ON, the ten bytes of data (DM 0000 to DM 0004) will be transmitted. RS-232C Communications This section explains RS-232C communications.
RS-232C Communications Section 8-3 Specify whether or not a start code is to be set at the beginning of the data, and whether or not an end code is to be set at the end. Instead of setting the end code, it is possible to specify the number of bytes to be received before the reception operation is completed. Both the codes and the number of bytes of data to be received are set in DM 6649 or DM 6654.
RS-232C Communications Section 8-3 2. Use the TXD(––) instruction to transmit the data. (Bits 08 to 11 are valid only when bits 12 to 15 are set to 0.) (@)TXD S: Address of first word of data to be transmitted S C N C: Control data Bits 00 to 03 0: Leftmost bytes first 1: Rightmost bytes first Bits 04 to 07 0: Normal data transmission operation 1: Status of bit 15 for the leftmost word of the transmission data is reflected on the RTS of the corresponding port.
RS-232C Communications Section 8-3 3. When RXD(––) is executed, the received data is transferred to the specified words (without the start and end codes) and the Reception Completed Flag is turned OFF. The start and end of reception are as follows: Start: Continuous reception status if the start code is not enabled. Reception starts when the start code is received if it is enabled. End: Reception ends when the end code is received or 259 bytes of data have been received. 4.
One-to-one PC Links 8-4 Section 8-4 One-to-one PC Links If two PCs are linked one-to-one by connecting them together through their RS-232C ports, they can share common LR areas. When two PCs are linked one-to-one, one of them will serve as the master and the other as the slave. As shown in the diagram below, when data is written into a word the LR area of one of the linked Units, it will automatically be written identically into the same word of the other Unit.
One-to-one PC Links PC Setup Section 8-4 To use a 1:1 link, the only settings necessary are the communications mode and the link words. Set the communications mode for one of the PCs to one-to-one link master and the other PC to one-to-one link slave, and then set the link words in the PC designated as the master. Bits 08 to 11 are valid only for the master for link one-to-one.
NT Links 8-5 Section 8-5 NT Links A one-to-one NT link that uses NT link commands can be established by connecting the RS-232C port of the PC to the RS-232C port of a Programmable Terminal (PT). A one-to-N NT link that uses NT link commands can be established by connecting the PC and Programmable Terminal (PT) with RS-422/485 cable. One-to-one NT Links The following diagram shows the connections for a one-to-one NT link.
The Protocol Macro Function Section 8-6 Restrictions on Use If the C200H-OV001 Voice Unit is being used, the 1:N mode cannot be used with the RS-232 port. In that case, either use the NT Link in 1:1 mode or use the 1:N mode with the port on the communications board. Applications Refer to the documentation provided for the NT Link Interface Unit for details on actual NT link applications. 8-6 The Protocol Macro Function This section explains how to use the Protocol Macro function.
The Protocol Macro Function RS-422/485 Connection (One-to-N) (RS-232C) Port B (RS-422/485) Port A Section 8-6 An RS-422/485 connection allows 2 or more devices to be connected (one-to-N connection) with a maximum cable length of 500 m. The RS-422/485 connection is also useful for distant one-to-one connections.
The Protocol Macro Function Section 8-6 General Device/Computer Connections (RS/CS Flow, Cross Connection) Host computer C200HX/HG/HE Modem Connection (Straight Connection) Modem C200HX/HG/HE Note Ground the FG terminals on the PC and at the other device to 100 Ω or less. Refer to the C200HX/HG/HE Installation Manual and the documentation included with the other device for details.
The Protocol Macro Function Section 8-6 8-6-2 Communications Board Settings The following parameters must be set in advance in order to use the Protocol Macro function through a Communications Board. Communications Mode Set the communications mode to Protocol Macro mode. Port B: Set bits 12 through 15 of DM 6550 to 6. Port A: Set bits 12 through 15 of DM 6555 to 6. Standard Port Settings Standard settings or custom settings can be used for ports A and B.
The Protocol Macro Function Section 8-6 Parameter Setting Baud rate 00 01 02 03 04 Baud rate 1,200 bps 2,400 bps 4,800 bps 9,600 bps 19,200 bps 8-6-3 Communications Procedure The Protocol Macro’s communications sequences must be created with the Protocol Support Software and transferred to the Communications Board in advance. In the PC, the PMCR(––) instruction is executed to execute a communications sequence stored in the Communications Board.
The Protocol Macro Function Transmission/Reception Message Structure Section 8-6 The transmission message and reception message have the following structure. Header Address Length Data Error check Item Terminator Function Header Set the data that indicates the beginning of the message. Address Length Set the node number or other identifier that indicates the destination for the message. The data length (number of bytes) is added automatically. Data Set the message contents.
The Protocol Macro Function Section 8-6 Read Word (R) Word data can be read by setting the desired attributes for the “address” or “data” in the transmission and reception messages. When the attribute is set, the address or data is read from the specified word. There are three ways to specify the word: 1, 2, 3... 1. The second operand of the PMCR(––) instruction (S, the first output word) can be used.
The Protocol Macro Function Section 8-6 Example: R(2N+6) Specifies the sixth word following the PMCR(––) instruction’s second operand for the “address” or “data” and adds two words to the specification each time that the step is repeated. Specifying the first address with 2N+6 (a first order equation using N).
The Protocol Macro Function Section 8-6 Set the wild card ( ) in the reception message so that all data will be received. In the next process, set “End” in both the transmission step and the reception step. In error processing, set “Abort” in both the transmission step and the reception step.
SECTION 9 Troubleshooting The C200HX/HG/HE provides self-diagnostic functions to identify many types of abnormal system conditions. These functions minimize downtime and enable quick, smooth error correction. This section provides information on hardware and software errors that occur during PC operation. Program input errors are described in 4-7 Inputting, Modifying, and Checking the Program.
Reading and Clearing Errors and Messages 9-1 Section 9-3 Alarm Indicators The ALM/ERR indicator on the front of the CPU Unit provides visual indication of an abnormality in the PC. When the indicator is ON (ERROR), a fatal error (i.e., ones that will stop PC operation) has occurred; when the indicator is flashing (ALARM), a nonfatal error has occurred. This indicator is shown in 2-1-1 CPU Unit Indicators.
Section 9-4 Error Messages 9-4 Error Messages There are basically three types of errors for which messages are displayed: initialization errors, non-fatal operating errors, and fatal operating errors. Most of these are also indicated by FAL number being transferred to the FAL area of the SR area. The type of error can be quickly determined from the indicators on the CPU Unit, as described below for the three types of errors.
Section 9-4 Error Messages Error and message FAL no. 8B Probable cause Possible correction An interrupt subroutine longer than 10 ms was executed during I/O refreshing of a Remote I/O Unit or during Host Link servicing. An attempt was made to execute a different type of I/O refresh from the type set for the Special I/O Unit cycle refresh. Check the contents of SR 262 and SR 263 and verify that the interrupt subroutine’s processing time is less than 10 ms.
Section 9-4 Error Messages Error and message FAL no. Special I/O Unit error Probable cause Possible correction D0 Error has occurred in PC Link Unit, Remote I/O Master Unit, between a Host Link, SYSMAC LINK, or SYSMAC NET Link Unit and the CPU Unit, or in refresh between Special I/O Unit and the CPU Unit. Determine the unit number of the Unit which caused the error (AR 00 or SR 282), correct the error, and toggle the appropriate Restart Bit in AR 01, SR 250, or SR 252.
Section 9-4 Error Messages Error and message Too many Units FAL no. E1 I/O UNIT OVER Probable cause Possible correction Two or more Special I/O Units or Group-2 High-density I/O Units are set to the same unit number. Perform the I/O Table Read operation to check unit numbers, and eliminate duplications. The unit number of a Special I/O Unit that requires two words is set to the last unit number (9 or F). Unit numbers of Units that require two words cannot be set to the last unit number.
Section 9-5 Error Flags 9-5 Error Flags The following table lists the flags and other information provided in the SR and AR areas that can be used in troubleshooting. Details are provided in 3-4 SR Area and 3-5 AR Area.
Section 9-6 Host Link Errors Address(es) 28000 to 28015 28200 to 28215 28300 to 28303 28308 to 28311 Function Group-2 High-density I/O Unit Error Flags for Units 0 to F Special I/O Unit Error Flags for Units 0 to F Communications Board Port A Error Code Communications Board Port B Error Code AR Area Address(es) 0000 to 0009 0010 0011 0012 0013 0014 0015 0200 to 0204 0205 to 0214 0215 0300 to 0315 0400 to 0415 0500 to 0515 0600 to 0615 0713 to 0715 1114 1115 1514 1515 9-6 Function Special I/O or PC Link
Section 9-6 Host Link Errors End code 16 Command not supported The operand specified in an SV Check the command and program. Read or SV Change command does not exist in the program. 18 Frame length error The maximum frame length of 132 Check the command and divide it bytes was exceeded. into multiple frames if necessary. (If the frame exceeds 280 bytes, the Reception Overflow Flag will be turned ON and there won’t be a response.
SECTION 10 Host Link Commands This section describes the host link commands which can be used for host link communications via the C200HX/HG/HE ports. Refer to 8-2 Host Link Communications for information on the procedures for using host link commands and errors associated with host link commands. 10-1 Host Link Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 Host Link End Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 10-1 Host Link Command Summary 10-1 Host Link Command Summary Command Chart The commands listed in the chart below can be used for host link communications with the C200HX/HG/HE.
Host Link End Codes Section 10-2 10-2 Host Link End Codes 10-2-1 End Code Summary These are the response (end) codes that are returned in the response frame. When two or more errors occur, the end code for the first error will be returned. End code Contents Probable cause Corrective measures 00 Normal completion --- 01 Not executable in RUN mode The command that was sent cannot Check the relation between the be executed when the PC is in RUN command and the PC mode. mode.
Host Link End Codes Errors without Responses Section 10-2 A response won’t be received with some errors, regardless of the command. These errors are listed in the following table. Error Parity overrun or framing error during command reception PC operation The Communications Error Flag will be turned ON, an error code will be registered, and receptions will be reset. (The error will be cleared automatically if communications restart normally.) A carriage return (CR) isn’t received within 280 bytes.
Host Link End Codes Section 10-2 10-2-2 Command/End Code Table The following table shows which end codes can be returned for each command.
Host Link Commands Section 10-3 10-3 Host Link Commands This section explains the various Host Link commands that can be issued from the host computer to the PC. Refer to 8-2 Host Link Communications for information on the procedures for using host link commands and errors associated with host link commands. 10-3-1 IR/SR AREA READ –– RR Reads the contents of the specified number of IR and SR words, starting from the specified word. Command Format @ x 101 x 100 Node no.
Host Link Commands Section 10-3 10-3-2 LR AREA READ –– RL Reads the contents of the specified number of LR words, starting from the specified word. Command Format @ x 101 x 100 Node no. R L Header code x 103 x 102 x 101 x 100 x 103 x 102 x 101 x 100 Beginning word (0000 to 0063) No. of words (0001 to 0064) FCS ↵ Terminator Response Format @ x 101 x 100 Node no.
Host Link Commands Section 10-3 10-3-3 HR AREA READ –– RH Reads the contents of the specified number of HR words, starting from the specified word. Command Format @ x 101 x 100 Node no. R H Header code x 103 x 102 x 101 x 100 x 103 x 102 x 101 x 100 Beginning word (0000 to 0099) No. of words (0001 to 0100) FCS ↵ Terminator Response Format @ x 101 x 100 Node no.
Host Link Commands Section 10-3 10-3-4 PV READ –– RC Reads the contents of the specified number of timer/counter PVs (present values), starting from the specified timer/counter. Command Format @ x 101 x 100 Node no. R C Header code x 103 x 102 x 101 x 100 x 103 x 102 x 101 x 100 Beginning timer/counter (0000 to 0511) ↵ No. of timers/counters (0001 to 0512) FCS Terminator Response Format @ x 101 x 100 Node no.
Host Link Commands Section 10-3 10-3-5 TC STATUS READ –– RG Reads the status of the Completion Flags of the specified number of timers/ counters, starting from the specified timer/counter. A “1” indicates that the Completion Flag is ON. Command Format @ x 101 x 100 Node no. R G Header code x 103 x 102 x 101 x 100 x 103 x 102 x 101 x 100 Beginning timer/counter (0000 to 0511) No. of timers/counters (0001 to 0512) FCS ↵ Terminator Response Format @ x 101 x 100 Node no.
Host Link Commands Section 10-3 10-3-6 DM AREA READ –– RD Reads the contents of the specified number of DM words, starting from the specified word. Command Format @ x 101 x 100 Node no. R D Header code x 103 x 102 x 101 x 100 x 103 x 102 x 101 x 100 Beginning word (0000 to 9999) No. of words (0001 to 10000) (see note) FCS ↵ Terminator Note To specify 10,000 words, input 0000 for the number of words to be read. Response Format @ x 101 x 100 Node no.
Host Link Commands Section 10-3 10-3-7 AR AREA READ –– RJ Reads the contents of the specified number of AR words, starting from the specified word. Command Format @ x 101 x 100 Node no. R J x 103 x 102 x 101 x 100 x 103 x 102 x 101 x 100 Header code Beginning word (0000 to 0027) No. of words (0001 to 0028) FCS ↵ Terminator Response Format @ x 101 x 100 Node no.
Host Link Commands Section 10-3 Response Format @ x 101 x 100 Node no. R x 161 x 160 x 163 x 162 x 161 x 160 E Header code Limitations End code Read data (1 word) FCS ↵ Terminator Read data (for number of words read) The text portion of the response’s first frame can contain up to 30 words. If more than 30 words are read, the data will be returned in multiple frames. In the second and later frames, the text portion of the response can contain up to 31 words.
Host Link Commands Section 10-3 Response Format x 101 x 100 @ Node no. Limitations R x 161 x 160 Header code End code W ↵ FCS Terminator Data cannot be written to words 253 to 255. If there is an attempt to write to these words, no error will result, but nothing will be written to these words. Except for the first word of the write data, the write data can be divided into multiple frames.
Host Link Commands Section 10-3 Response Format x 101 x 100 @ Node no. Limitations L x 161 x 160 Header code End code W ↵ FCS Terminator Except for the first word of the write data, the write data can be divided into multiple frames.
Host Link Commands Section 10-3 Limitations Except for the first word of the write data, the write data can be divided into multiple frames. PC Settings PC Mode MONITOR OK RUN --- UM Area Write-protected Read-protected OK OK PROGRAM OK Execution Conditions Commands Single OK End Codes Responses Multiple OK Single OK Multiple --- An end code of 14 (format error) will be returned if the length of the command is incorrect or the first word of write data isn’t in the first frame.
Host Link Commands Section 10-3 Execution Conditions Commands Single OK End Codes Responses Multiple OK Single OK Multiple --- An end code of 14 (format error) will be returned if the length of the command is incorrect or the first word of write data isn’t in the first frame. An end code of 15 (entry number data error) will be returned if the specified write data exceeds the data area boundary, the beginning word isn’t specified in BCD, or the write data isn’t hexadecimal.
Host Link Commands Section 10-3 End Codes An end code of 14 (format error) will be returned if the length of the command is incorrect or the first word of write data isn’t in the first frame. An end code of 15 (entry number data error) will be returned if the digits of write data aren’t 0 or 1, the specified write data exceeds the data area boundary, the beginning word isn’t specified in BCD, or the write data isn’t hexadecimal.
Host Link Commands Section 10-3 End Codes An end code of 14 (format error) will be returned if the length of the command is incorrect or the first word of write data isn’t in the first frame. An end code of 15 (entry number data error) will be returned if the specified write data exceeds the data area boundary, the beginning word isn’t specified in BCD, or the write data isn’t hexadecimal. (An end code of A5 will be returned instead of 15 for non-hexadecimal write data in multiple command frames.
Host Link Commands Section 10-3 An end code of 15 (entry number data error) will be returned if the specified write data exceeds the data area boundary, the beginning word isn’t specified in BCD, or the write data isn’t hexadecimal. (An end code of A5 will be returned instead of 15 for non-hexadecimal write data in multiple command frames.
Host Link Commands Section 10-3 An end code of 15 (entry number data error) will be returned if the specified write data exceeds the data area boundary, the beginning word isn’t specified in BCD, or the write data isn’t hexadecimal. (An end code of A5 will be returned instead of 15 for non-hexadecimal write data in multiple command frames.
Host Link Commands Section 10-3 Execution Conditions Commands Single OK End Codes Responses Multiple --- Single OK Multiple --- An end code of 14 (format error) will be returned if the length of the command is incorrect. An end code of 15 (entry number data error) will be returned if an incorrect instruction mnemonic or TC number is used. An end code of 16 (command not supported) will be returned if the specified instruction doesn’t exist in the program.
Host Link Commands Section 10-3 The “Operand” parameter indicates the data area where the SV is stored or a constant. The “SV” parameter indicates the word address or the SV itself if it is a constant.
Host Link Commands 10-3-19 Section 10-3 SV READ 3 –– R% Reads the constant SV or the word address where the SV is stored. The SV that is read is a 4-digit decimal number (BCD) written in the second word of the TIM, TIMH(15), CNT, CNTR(12), or TTIM(87) instruction at the specified program address in the user’s program. Command Format @ x 101 x 100 Node no.
Host Link Commands Section 10-3 PC Settings RUN OK PC Mode MONITOR OK PROGRAM OK UM Area Write-protected Read-protected OK --- Execution Conditions Commands Single OK End Codes Responses Multiple --- Single OK Multiple --- An end code of 04 (address over) will be returned if the program address is above the highest program address but less than 65,536 (32,768 in the C200HS). An end code of 14 (format error) will be returned if the length of the command is incorrect.
Host Link Commands Section 10-3 Response Format @ x 101 x 100 Node no. Limitations W # x 161 x 160 Header code End code FCS ↵ Terminator The command can’t be executed unless the SV is BCD from 0000 to 9999. The command can’t be executed if the UM area is write-protected. If the same instruction is used more than once in a program, the SV of the first one will be changed.
Host Link Commands Section 10-3 Use all four characters to specify the timer or counter instruction’s mnemonic. Add a space to the end of a TIM or CNT mnemonic to make it 4 characters long. Mnemonic Instruction name OP1 TIMER HIGH-SPEED TIMER COUNTER REVERSIBLE COUNTER TOTALIZING TIMER T T C C T OP2 TC number range OP3 M M T T I I I N N T OP4 (Space) 0000 to 0511 H (Space) R M The “Operand” parameter indicates the data area where the SV is stored or a constant.
Host Link Commands Section 10-3 End code 10-3-22 Contents 04 Address over 13 FCS error 14 Format error 15 Entry number data error 16 Command not supported 18 Frame length error 23 User memory protected SV CHANGE 3 –– W% Changes the contents of the second word of the TIM, TIMH(15), CNT, CNTR(12), or TTIM(87) at the specified program address in the user’s program. Command Format @ x 101 x 100 Node no.
Host Link Commands Section 10-3 Response Format @ x 101 x 100 Node no. Limitations W % Header code x 161 x 160 End code FCS ↵ Terminator The command is valid only when the UM setting is ladder only. SR 253 through SR 255 can’t be specified. The command can’t be executed if the UM area is write-protected.
Host Link Commands Section 10-3 “Status data” consists of four digits (two bytes) hexadecimal. The leftmost byte indicates CPU Unit operation mode, and the rightmost byte indicates the size of the program area. x 163 Bit 15 14 13 0 0 x 162 12 11 10 9 8 Bit Operation mode 1: Waiting for Remote I/O power application 9 8 0 0 PROGRAM mode 1: Forced Set/Reset in effect 1 0 RUN mode 1: Fatal error generated 1 1 MONITOR mode This area is different from that of STATUS WRITE.
Host Link Commands 10-3-24 Section 10-3 STATUS WRITE –– SC Changes the PC operating mode. Command Format x 101 x 100 @ S Node no. C x 161 x 160 Header code Mode data S x 161 x 160 FCS ↵ Terminator Response Format x 101 x 100 @ Node no. C Header code End code FCS ↵ Terminator “Mode data” consists of two digits (one byte) hexadecimal. With the leftmost two bits, specify the PC operating mode. Set all of the remaining bits to “0.
Host Link Commands 10-3-25 Section 10-3 ERROR READ –– MF Reads and clears errors in the PC. Also checks whether previous errors have been cleared. Command Format @ x 101 x 100 M Node no. x 101 x 100 F Header code Error clear FCS ↵ Terminator For the “error clear” parameter, specify 01 to clear errors and 00 to not clear errors (BCD). Fatal errors can be cleared only when the PC is in PROGRAM mode. Response Format @ x 101 x 100 Node no.
Host Link Commands Section 10-3 Limitations When errors are being cleared (error clear = 01), the errors are read after the error clear function is executed. PC Settings PC Mode MONITOR OK RUN OK PROGRAM OK UM Area Write-protected Read-protected OK OK Execution Conditions Commands Single OK End Codes Responses Multiple --- Single OK Multiple --- An end code of 14 (format error) will be returned if the length of the command is incorrect.
Host Link Commands Section 10-3 Response Format @ x 101 x 100 Node no. Limitations K S Header code End code ↵ x 161 x 160 FCS Terminator Bits in SR 253 through SR 255 can’t be specified. PC Settings PC Mode MONITOR OK RUN --- PROGRAM OK UM Area Write-protected Read-protected OK OK Execution Conditions Commands Single OK End Codes Responses Multiple --- Single OK Multiple --- An end code of 14 (format error) will be returned if the length of the command is incorrect.
Host Link Commands Section 10-3 For the TC area, “Operand” parameter indicates the mnemonic of the timer or counter instruction and the “Word address” parameter indicates the TC number. Operand Data area/ instruction OP4 (Space) (Space) (Space) (Space) (Space) H (Space) R M Word address Bit 0000 to 0511 0000 to 0063 0000 to 0099 0000 to 0027 0000 to 0511 00 to 15 IR or SR LR HR AR TIMER HIGH-SPEED TIMER COUNTER REVERS.
Host Link Commands 10-3-28 Section 10-3 MULTIPLE FORCED SET/RESET –– FK Force sets, force resets, or cancels the forced status of the bits in one word in the IR, SR, LR, HR, or AR, or a timer/counter Completion Flag. Command Format @ x 101 x 100 Node no.
Host Link Commands Limitations Section 10-3 Bits in SR 253 through SR 255 can’t be specified. Only 15 timers/counters or 15 Transition Flags can be set/reset. The UM settings are not checked when Transition Flags are specified, i.e., as long as the Transition Flag address does not exceed 1023, the command will be executed normally even if the specified Flag does not actually exist in the remote PC.
Host Link Commands Section 10-3 PC Settings PC Mode MONITOR OK RUN --- UM Area Write-protected Read-protected OK OK PROGRAM OK Execution Conditions Commands Single OK End Codes Responses Multiple --- Single OK An end code of 14 (format error) will be returned if the length of the command is incorrect. End code 10-3-30 Multiple --- Contents 00 Normal completion 13 FCS error 14 Format error 18 Frame length error PC MODEL READ –– MM Reads the model type of the PC.
Host Link Commands Section 10-3 Execution Conditions Commands Single OK End Codes Responses Multiple --- Single OK An end code of 14 (format error) will be returned if the length of the command is incorrect. End code 10-3-31 Multiple --- Contents 00 Normal completion 13 FCS error 14 Format error 18 Frame length error TEST–– TS Returns, unaltered, one block of data transmitted from the host computer. Command Format Specify any characters other than the carriage return (CHR$(13)).
Host Link Commands 10-3-32 Section 10-3 PROGRAM READ –– RP Reads the contents of the PC user’s program area in machine language (object code). The contents are read as a block, from the beginning to the end. Command Format @ x 101 x 100 Node no. R P Header code FCS ↵ Terminator Response Format @ x 101 x 100 Node no.
Host Link Commands 10-3-33 Section 10-3 PROGRAM WRITE –– WP Writes to the PC user’s program area the machine language (object code) program transmitted from the host computer. The contents are written as a block, from the beginning. Command Format @ x 101 x 100 Node no. W P x 161 x 160 Header code 1 byte FCS ↵ Terminator Program (Up to maximum memory size) Response Format @ x 101 x 100 Node no.
Host Link Commands Section 10-3 End code 10-3-34 Contents 14 Format error 15 Entry number data error 18 Frame length error 19 Not executable 23 User memory protected A3 Aborted due to FCS error in transmit data A4 Aborted due to format error in transmit data A5 Aborted due to entry number data error in transmit data A8 Aborted due to frame length error in transmit data I/O TABLE GENERATE –– MI Corrects the registered I/O table to match the actual I/O table.
Host Link Commands 10-3-35 Section 10-3 COMPOUND COMMAND –– QQMR Registers at the PC all of the bits, words, and timers/counters that are to be read, and reads the status of all of them as a batch. The registered information is retained in the PC until it is overwritten by the COMPOUND COMMAND or the PC’s power is turned off. Command Format @ x 101 x 100 Node no.
Host Link Commands Limitations Section 10-3 The registered data is checked from the beginning and the data will be registered up to any errors. For example, if a command attempts to register 129 items, a frame length error (end code 18) will occur but the first 128 items will be registered. DM 6656 to DM 6999 do not exist, but an error will not occur if you try to register these words. Bits and words can be specified in any order and they will be registered in the order that they were specified.
Host Link Commands Section 10-3 Response Format @ x 101 x 100 Node no. Q Q Header code I R x 161 x 160 ON/ x 103 x 102 x 101 x 100 OFF Sub-header End code code ON/ OFF , Timer/Counter If PV is specified the status of the Completion Flag is also returned. , , Data break x 163 x 162 x 161 x 160 Word data IR, SR, LR, HR, AR, DM Bit data ON/OFF Limitations , FCS ↵ Terminator The data is read in the same order in which it was registered with QQMR.
Host Link Commands Limitations Section 10-3 Multiple responses to a command can be cancelled with this command. This command is valid even without the FCS code and terminator. PC Settings RUN OK PC Mode MONITOR OK PROGRAM OK UM Area Write-protected Read-protected OK OK Execution Conditions Commands Single OK End Codes 10-3-38 Responses Multiple --- Single --- Multiple --- There are no end codes with this command.
Host Link Commands Section 10-3 Execution Conditions Commands Single Multiple --- --End Codes 10-3-40 Responses Single OK Multiple --- There are no end codes with this command. Undefined Command –– IC This response is returned if the header code of a command cannot be decoded. Check the header code. Response Format @ x 101 x 100 Node no.
Appendix A Standard Models CPU Rack Name CPU Units (All models are proUM vided with clock function and slots 3.2K words for communications except 7.2K words CPU11-E.
Appendix A Standard Models Expansion I/O Racks Name Power Supply Units Expansion I/O Backplanes I/O Connecting Cables Specifications Model number 100 to 120/200 to 240 VAC C200HW-PA204 100 to 120/200 to 240 VAC (with 24-VDC output terminals) C200HW-PA204S 24 VDC C200HW-PD024 3 slots C200HW-BI031 5 slots C200HW-BI051 8 slots C200HW-BI081 10 slots C200HW-BI101 30 cm 70 cm 200 cm 500 cm 1,000 cm The total length of the I/O Connecting Cables used in a network must be 12 m maximum.
Appendix A Standard Models I/O Units Name Input Units Output Units AC Input Units Specifications Model number 8 pts 100 to 120 VAC C200H-IA121 16 pts 100 to 120 VAC C200H-IA122/IA122V 8 pts 200 to 240 VAC C200H-IA221 16 pts 200 to 240 VAC C200H-IA222/IA222V DC Input Units 8 pts 12 to 24 VDC C200H-ID211 DC Input Units 16 pts 24 VDC C200H-ID212 AC/DC Input Units 8 pts 12 to 24 VAC/DC C200H-IM211 16 pts 24 VAC/DC C200H-IM212 Interrupt Input Unit (see note) 8 pts 12 to 24 VDC
Appendix A Standard Models Name B7A Interface Units Specifications Model number 15 or 16 input pts Connects to B7A Link Terminals. Standard transmission delay. C200H-B7AI1 16 output pts Connects to B7A Link Terminals. Standard transmission delay. C200H-B7AO1 (see note) Note: If the Interrupt Input Unit is mounted on an Expansion I/O Rack, the interrupt function cannot be used and the Interrupt Input Unit will be treated as an ordinary 8-point Input Unit.
Appendix A Standard Models Analog I/O Units Name Analog Input Units Analog Output Unit Fuzzy Logic Unit Fuzzy Support Software Temperature Sensor Units Specifications 4 to 20 mA, 1 to 5/0 to 10 V (switchable); 4 inputs; 12 bits Model number C200H-AD001 4 to 20 mA, 1 to 5/0 to 10 V/–10 to 10V (switchable); 8 inputs; 12 bits or BCD C200H-AD002 4 to 20 mA, 1 to 5/0 to 10 V (switchable); 2 outputs C200H-DA001 Programmed using the Fuzzy Support Software. Up to 8 inputs and 4 outputs.
Appendix A Standard Models Name Position Control Units Specifications Pulse output; speeds: 1 to 100,000 pps Pulse output; directly connects to servomotor driver; compatible with line driver; speeds: 1 to 250,000 pps Model number C200H-NC111 C200H-NC112 Pulse output; directly connects to servodriver 2 axes Pulse output; speeds: 1 to 250,000 pps, 53 pts per axis 2 axes Pulse output; directly connects to servodriver 4 axes Pulse output; directly connects to servodriver 1 axis Pulse input; counting speed:
Appendix A Standard Models Name SYSMAC LINK Unit (optical fiber cable) Power Supply Adapter Power Cable SYSMAC LINK Support Board (coaxial cable) SYSMAC NET Link Unit Power Supply Adapter Power Cable Bus Connection Units Host Link Units Specifications Connect with H-PCF cable. A Bus Data link table: Connection Unit must be ordered 918 words separately. Data link table: 2,966 words Required when supplying backup power For 1 or 2 Units Connects Power Supply Adapter and SYSMAC For 1 Unit NET Link Unit.
Appendix A Standard Models Link Adapters Name Link Adapters Specifications Model number 3 RS-422 connectors 3G2A9-AL001 3 optical connectors (APF/PCF) 3G2A9-AL002-PE 3 optical connectors (PCF) 3G2A9-AL002-E 1 connector for RS-232C; 2 for RS-422 3G2A9-AL003 1 connector each for APF/PCF, RS-422, and RS-232C 3G2A9-AL004-PE 1 connector each for PCF, RS-422, and RS-232C 3G2A9-AL004-E 1 connector each for APF/PCF and AGF 3G2A9-AL005-PE 1 connector each for PCF and AGF 3G2A9-AL005-E 1 connecto
Appendix A Standard Models Model Numbers The above cable model numbers specify the type of cable, the length, and the type of connectors attached. S3200-CN -20-25 1. 2. 3. 1. S3200-CN specifies H-PCF optical fiber cable. 2. The boxes ( ) are replaced by codes indicating the standard model lengths, as shown below. Consult with your OMRON representative for longer cables. When ordering longer cables, omit the portion represented by the boxes and specify the length in meters separately, e.g.
Appendix A Standard Models Plastic Clad Optical Fiber Cable for SYSMAC BUS Name Plastic Clad Optical Fiber Cables (indoor) Specifications Model number Ambient temp: –10°° to 70°C ° 0.
Appendix A Standard Models Name Optical Fiber Cable Connector Specifications Model number SYSMAC NET: S3200-LSU03-01E B700-AL001 C500-SNT31-V4 Full-lock connector for NSU, NSB, and C500 SYSMAC NET Link Unit S3200-COCH62M SYSMAC BUS: C200H-RM001-PV1 C200H-RT001/RT002-P C500-RM001-(P)V1 C500-RT001/RT002-(P)V1 3G2A9- (-P) Half-lock conS3200-COCH82 nector for Remote I/O Master, Remote I/O Slave, Host Link Unit, and Link Adapter SYSMAC NET/SYSMAC LINK C200HS-SNT32 C200HW-SLK13/14 Half-lock connector
Appendix A Standard Models Optical Power Tester Name Specifications Optical Power Tester (see note) SYSMAC NET: (provided with a connector CV500-SNT31 adapter, light source unit, small C200HS-SNT32 single-head plug, hard case, SYSMAC LINK: and AC adapter) CV500-SLK11 C200HW-SLK13/14 CV1000H-SLK11 Head Unit Model number S3200-CAT200 2 (provided with the Tester) S3200-CAT2000 S3200-CAT270 2 (provided with the Tester) S3200-CAT2700 SYSMAC BUS: C200H-RM001-PV1 C200H-RT001/RT002-P C500-RM001-(P)V1 C500
Appendix A Standard Models Programming Devices Name Specifications Model number Standards Hand-Held, w/backlight C200H-PRO27-E U, C 2-m Connecting Cable included CQM1-PRO01-E U, C Programming Console Mounting Bracket Used to attach Hand-held Programming Console to a panel.
Appendix A Standard Models Name Specifications Model number Standards Relay 24 VDC G6B-1174P-FD-US --- Backplane Insulation Plates For C200HW-BC031 (3-slot CPU Backplane) C200H-ATT31 For C200HW-BC051 (5-slot CPU Backplane) C200H-ATT51 For C200HW-BC081 (8-slot CPU Backplane) C200H-ATT81 For C200HW-BC101 (10-slot CPU Backplane) C200H-ATTA1 For C200HW-BI031 (3-slot I/O Backplane) C200HW-ATT32 For C200HW-BI051 (5-slot I/O Backplane) C200HW-ATT52 For C200HW-BI081 (8-slot I/O Backplane) C200
Appendix A Standard Models Protocol Support Software Name Protocol Support Software Specifications 3.5”, 2HD for IBM PC/AT compatible Model number C200HW-ZW3AT1-E Standards --- Training Materials Name Specifications Model number Standards SYSMAC Training System Includes text book, cassette tape, and input switch board.
Appendix B Programming Instructions A PC instruction is input either by pressing the corresponding Programming Console key(s) (e.g., LD, AND, OR, NOT) or by using function codes. To input an instruction with its function code, press FUN, the function code, and then WRITE. Refer to the pages listed programming and instruction details.
Appendix B Programming Instructions Code Mnemonic Name 13 DIFU DIFFERENTIATE UP 14 DIFD 15 TIMH DIFFERENTIATE DOWN HIGH-SPEED TIMER (@)16 WSFT WORD SHIFT 17 to 19 For expansion instructions.
Appendix B Programming Instructions Code Mnemonic Name Function Page (@)52 MLB BINARY MULTIPLY Multiplies two four-digit hexadecimal values and outputs result to specified result words. 248 (@)53 DVB BINARY DIVIDE Divides four-digit hexadecimal dividend by four-digit hexa- 248 decimal divisor and outputs result to specified result words. (@)54 ADDL DOUBLE BCD ADD Adds two eight-digit values (2 words each) and content of CY, and outputs result to specified result words.
Appendix B Programming Instructions Code Mnemonic Name (@)86 ASC ASCII CONVERT 87 to 89 For expansion instructions. (@)90 SEND NETWORK SEND (@)91 SBS 92 SBN 93 RET SUBROUTINE ENTRY SUBROUTINE DEFINE RETURN (@)94 WDT (@)97 IORF WATCHDOG TIMER REFRESH I/O REFRESH (@)98 RECV NETWORK RECEIVE (@)99 MCRO MACRO Function Page Converts hexadecimal values from the source word to 218 eight-bit ASCII code starting at leftmost or rightmost half of starting destination word.
Appendix B Programming Instructions Code Mnemonic Name --- 7SEG --- (@)ADBL 7-SEGMENT DISPLAY OUTPUT DOUBLE BINARY ADD --- AVG AVERAGE VALUE --- (@)BXF2 --- Function Page Converts 4- or 8-digit BCD data to 7-segment display format and then outputs the converted data. Adds two 8-digit binary values (normal or signed data) and outputs the result to R and R+1. Adds the specified number of hexadecimal words and computes the mean value. Rounds off to 4 digits past the decimal point.
Appendix B Programming Instructions Code Mnemonic --- (@)RXD RECEIVE Receives data via a communications port. --- (@)SBBL --- (@)SCL DOUBLE BINARY SUBTRACT SCALING Subtracts an 8-digit binary value (normal or signed data) 251 from another and outputs the result to R and R+1. Performs a scaling conversion on the calculated value. 222 --- (@)SRCH DATA SEARCH Searches the specified range of memory for the specified data. Outputs the word address(es) of words in the range that contain the data.
Appendix C Error and Arithmetic Flag Operation The following table shows the instructions that affect the N, OF, UF, ER, CY, GR, LE and EQ flags. In general, N indicates a negative result, OF indicates that the result of a 16-bit calculation is greater than 32,767 (7FFF) or the result of a 32-bit calculation is greater than 2,147,483,647 (7FFF FFFF). UF indicates that the result of a 16-bit calculation is less than –32,768 (8000) or the result of a 32-bit calculation is less than –2,147,483,648 (8000 0000).
Appendix C Error and Arithmetic Flag Operation Mnemonic CLC(41) 25503 (ER) --- 25504 (CY) --- 25505 (GR) --- 25506 (EQ) --- 25507 (LE) --- 25404 (OF) --- 25405 (UF) --- 25402 (N) --- Page 229 MSG(46) µ --- --- --- --- --- --- --- 303 ADB(50) µ µ --- µ --- µ µ µ 243 SBB(51) µ µ --- µ --- µ µ µ 245 MLB(52) µ --- --- µ --- --- --- µ 248 DVB(53) µ --- --- µ --- --- --- µ 248 ADDL(54) µ µ --- µ --- --- --- --- 230 SUBL(55) µ µ --- µ ---
Appendix C Error and Arithmetic Flag Operation Mnemonic BXF2(––) 25503 (ER) µ 25504 (CY) --- 25505 (GR) --- 25506 (EQ) --- 25507 (LE) --- 25404 (OF) --- 25405 (UF) --- 25402 (N) --- 191 CMCR(––) µ --- --- --- --- --- --- --- 353 CMPL(60) µ --- µ µ µ --- --- --- 196 COLM(64) µ --- --- µ --- --- --- --- 225 CPS(––) µ --- µ µ µ --- --- --- 202 CPSL(––) µ --- µ µ µ --- --- --- 203 DBS(––) µ --- --- µ --- --- --- µ 255 DBSL(––) µ --- ---
Appendix C Error and Arithmetic Flag Operation Mnemonic ZCPL(––) 526 25503 (ER) µ 25504 (CY) --- 25505 (GR) µ 25506 (EQ) µ 25507 (LE) µ 25404 (OF) --- 25405 (UF) --- 25402 (N) --- Page 201
Appendix D Word Assignment Recording Sheets This appendix contains sheets that can be copied by the programmer to record I/O bit allocations and terminal assignments, as well as details of work bits, data storage areas, timers, and counters.
I/O Bits Programmer: Word: Bit Program: Unit: Field device Date: Word: Notes Bit 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 10 10 11 11 12 12 13 13 14 14 15 15 Word: Bit Unit: Field device Bit 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 10 10 11 11 12 12 13 13 14 14 15 15 528 Field device Word: Notes Page: Unit: Notes Unit: Field device Notes
Work Bits Programmer: Program: Area: Bit Word: Usage Date: Notes Bit 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 10 10 11 11 12 12 13 13 14 14 15 15 Area: Bit Word: Usage Page: Area: Word: Usage Area: Notes Bit 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 10 10 11 11 12 12 13 13 14 14 15 15 Notes Word: Usage Notes 529
Data Storage Programmer: Word 530 Program: Contents Notes Date: Word Page: Contents Notes
Timers and Counters Programmer: TC address Program: T or C Set value Notes Date: TC address T or C Page: Set value Notes 531
Appendix E Program Coding Sheet The following page can be copied for use in coding ladder diagram programs. It is designed for flexibility, allowing the user to input all required addresses and instructions. When coding programs, be sure to specify all function codes for instructions and data areas (or # for constant) for operands. These will be necessary when inputting programs though a Programming Console or other Peripheral Device.
Program Coding Sheet Programmer: Address 534 Instruction Program: Operand(s) Address Date: Instruction Operand(s) Page: Address Instruction Operand(s)
Appendix F Data Conversion Tables Normal Data Decimal BCD Hex Binary 00 00000000 00 00000000 01 00000001 01 00000001 02 00000010 02 00000010 03 00000011 03 00000011 04 00000100 04 00000100 05 00000101 05 00000101 06 00000110 06 00000110 07 00000111 07 00000111 08 00001000 08 00001000 09 00001001 09 00001001 10 00010000 0A 00001010 11 00010001 0B 00001011 12 00010010 0C 00001100 13 00010011 0D 00001101 14 00010100 0E 00001110 15 00010101 0F 0
Appendix F Standard Models Signed Binary Data Decimal 2147483647 2147483646 . . . 32768 32767 32766 . . . 5 4 3 2 1 0 –1 –2 –3 –4 –5 . . . –32767 –32768 –32769 . . . –2147483647 –2147483648 536 16-bit Hex ----. . . --7FFF 7FFE . . . 0005 0004 0003 0002 0001 0000 FFFF FFFE FFFD FFFC FFFB . . . 8001 8000 --. . . ----- 32-bit Hex 7FFFFFFF 7FFFFFFE . . . 00008000 00007FFF 00007FFE . . . 00000005 00000004 00000003 00000002 00000001 00000000 FFFFFFFF FFFFFFFE FFFFFFFD FFFFFFFC FFFFFFFB . . .
Appendix G Extended ASCII Programming Console Displays Bits 0 to 3 BIN Bits 4 to 7 0000 HEX 0001 0010 0011 2 0100 3 0101 4 0110 5 0111 1010 7 A 0 1 0000 0 NUL DLE Space 0 @ P ` 6 p 0001 1 SOH DC1 ! 1 A Q a q 0010 2 STX DC2 " 2 B R b r 0011 3 ETX DC3 # 3 C S c 0100 4 EOT DC4 $ 4 D T d 0101 5 ENQ NAK % 5 E U 0110 6 ACK SYN & 6 F 0111 7 BEL ETB ' 7 G 1000 8 BS CAN ( 8 1001 9 HT EM ) 9 1010 A LF SUB * 1011
Glossary address The location in memory where data is stored. For data areas, an address consists of a two-letter data area designation and a number that designates the word and/or bit location. For the UM area, an address designates the instruction location (UM area). In the FM area, the address designates the block location, etc. allocation The process by which the PC assigns certain bits or words in memory for various functions. This includes pairing I/O bits to I/O points on Units.
Glossary bit designator An operand that is used to designate the bit or bits of a word to be used by an instruction. bit number A number that indicates the location of a bit within a word. Bit 00 is the rightmost (least-significant) bit; bit 15 is the leftmost (most-significant) bit. building-block PC A PC that is constructed from individual components, or “building blocks.” With building-block PCs, there is no one Unit that is independently identifiable as a PC.
Glossary counter A dedicated group of digits or words in memory used to count the number of times a specific process has occurred, or a location in memory accessed through a TC bit and used to count the number of times the status of a bit or an execution condition has changed from OFF to ON. CPU An acronym for central processing unit. In a PC System, the CPU executes the program, processes I/O signals, communicates with external devices, etc.
Glossary differentiated instruction An instruction that is executed only once each time its execution condition goes from OFF to ON. Non-differentiated instructions are executed each cycle as long as the execution condition stays ON. differentiation instruction An instruction used to ensure that the operand bit is never turned ON for more than one cycle after the execution condition goes either from OFF to ON for a Differentiate Up instruction or from ON to OFF for a Differentiate Down instruction.
Glossary extended counter A counter created in a program by using two or more count instructions in succession. Such a counter is capable of counting higher than any of the standard counters provided by the individual instructions. extended timer A timer created in a program by using two or more timers in succession. Such a timer is capable of timing longer than any of the standard timers provided by the individual instructions.
Glossary increment Increasing a numeric value. indirect address An address whose contents indicates another address. The contents of the second address will be used as the operand. Indirect addressing is possible in the DM area only. initialization error An error that occurs either in hardware or software during the PC System startup, i.e., during initialization. initialize Part of the startup process whereby some memory areas are cleared, system setup is checked, and default values are set.
Glossary inverse condition A condition that produces an ON execution condition when the bit assigned to it is OFF, and an OFF execution condition when the bit assigned to it is ON. I/O capacity The number of inputs and outputs that a PC is able to handle. This number ranges from around one hundred for smaller PCs to two thousand for the largest ones. I/O Control Unit A Unit mounted to the CPU Rack in certain PCs to monitor and control I/O points on Expansion I/O Units.
Glossary ladder diagram (program) A form of program arising out of relay-based control systems that uses circuittype diagrams to represent the logic flow of programming instructions. The appearance of the program is similar to a ladder, and thus the name. ladder diagram symbol A symbol used in a ladder-diagram program. ladder instruction An instruction that represents the ‘rung’ portion of a ladder-diagram program.
Glossary LR area A data area that is used in a PC Link System so that data can be transferred between two or more PCs. If a PC Link System is not used, the LR area is available for use as work bits. main program All of a program except for the subroutines. masking ‘Covering’ an interrupt signal so that the interrupt is not effective until the mask is removed. Master Short for Remote I/O Master Unit. memory area Any of the areas in the PC used to hold data or programs.
Glossary normal condition A condition that produces an ON execution condition when the bit assigned to it is ON, and an OFF execution condition when the bit assigned to it is OFF. NOT A logic operation which inverts the status of the operand. For example, AND NOT indicates an AND operation with the opposite of the actual status of the operand bit. NSB An acronym for Network Service Board. NSU An acronym for Network Service Unit.
Glossary output device An external device that receives signals from the PC System. output point The point at which an output leaves the PC System. Output points correspond physically to terminals or connector pins. output signal A signal being sent to an external device. Generally an output signal is said to exist when, for example, a connection point goes from low to high voltage or from a nonconductive to a conductive state.
Glossary Programmable Controller A computerized device that can accept inputs from external devices and generate outputs to external devices according to a program held in memory. Programmable Controllers are used to automate control of external devices. Although single-component Programmable Controllers are available, buildingblock Programmable Controllers are constructed from separate components.
Glossary Remote I/O System A system in which remote I/O points are controlled through a Master mounted to a CPU Rack or an Expansion I/O Rack connected to the CPU Rack. Remote I/O Unit Any of the Units in a Remote I/O System. Remote I/O Units include Masters, Slaves, Optical I/O Units, I/O Link Units, and Remote Terminals. remote I/O word An I/O word allocated to a Unit in a Remote I/O System.
Glossary Slave Short for Remote I/O Slave Unit. Slave Rack A Rack containing a Remote I/O Slave Unit and controlled through a Remote I/O Master Unit. Slave Racks are generally located away from the CPU Rack. slot A position on a Rack (Backplane) to which a Unit can be mounted. software error An error that originates in a software program. software protect A means of protecting data from being changed that uses software as opposed to a physical switch or other hardware setting.
Glossary terminal instruction An instruction placed on the right side of a ladder diagram that uses the final execution conditions of an instruction line. terminator The code comprising an asterisk and a carriage return (* CR) which indicates the end of a block of data, whether it is a single-frame or multi-frame block. Frames within a multi-frame block are separated by delimiters. timer A location in memory accessed through a TC bit and used to time down from the timer’s set value.
Glossary word setting made on the Unit is added to 32 times the word multiplier to arrive at the actual word to be allocated. work bit A bit in a work word. work word A word that can be used for data calculation or other manipulation in programming, i.e., a ‘work space’ in memory. A large portion of the IR area is always reserved for work words. Parts of other areas not required for special purposes may also be used as work words, e.g., LR words not used in a PC Link or Net Link System.
Index A address tracing. See tracing, data tracing.
Index decrementing, 228 definers, definition, 138 delay time, in C500 Remote I/O Systems, 378 differentiated instructions, 140 function codes, 138 digit, monitoring, 390 digit numbers, 26 DIP switch, 20 displays converting between 4-digit hex and decimal, 399 converting between 8-digit hex and decimal, 400 converting between hex and ASCII, 398 I/O Unit designations, 100 Programming Console, English/Japanese switch, 91 DM area allocating UM to expansion DM, 410 Using EM for indirect addressing, 316 E EM (Ex
Index R$, 474 R%, 476 RC, 461 RD, 463 RE, 464 RG, 462 RH, 460 RJ, 464 RL, 459 RP, 492 RR, 458 SC, 483 TS, 491 W#, 477 W$, 478 W%, 480 WC, 468 WD, 470 WE, 472 WG, 469 WH, 467 WJ, 471 WL, 466 WP, 493 WR, 465 XZ, 497 Host Link Systems, error bits and flags, 40 Host Link Units, PC cycle time, 365 HR area, 68 I I/O bit definition, 29 limits, 29 I/O numbers, 32 I/O points, refreshing, 306, 307 I/O response time, one-to-one link communications, 383 I/O response times, 376 I/O status, maintaining, 42 I/O table cle
Index ILC(03), 117, 155–157 INC(38), 228 INT(89), 287 IORD(––), 350 IORF(97), 306 IOWR(––), 351 JME(05), 157 JMP(04), 157 JMP(04) and JME(05), 119 KEEP(11), 154 in controlling bit status, 121 ladder instructions, 77 LD, 78, 149 LD NOT, 78, 149 LINE(63), 224 LMSG(47), 304 MAX(––), 257 MBS(––), 253 MBSL(––), 254 MCMP(19), 192 MCRO(99), 285 MIN(––), 258 MLB(52), 248 MLPX(76), 209 MOV(21), 180 MOVB(82), 187 MOVD(83), 188 MPRF(61), 307 MSG(46), 303 MTR(––), 348 MUL(32), 235 MULL(56), 236 MVN(22), 180 NEG(––), 22
Index instructions combining, AND LD and OR LD, 84 controlling bit status using KEEP(11), 121 using OUT and OUT NOT, 150 format, 138 notation, 138 structure, 75 using logic blocks, 81 ladder diagram instructions, 149–150 LEDs. See CPU Unit indicators leftmost, definition, 26 Link System, flags and control bits, 40–41 Link Units See also Units flags, 55 logic block instructions, converting to mnemonic code, 81–87 logic blocks.
Index R Racks, types, 15 Remote I/O Master Units, PC cycle time, 365 Remote I/O Systems, error bits and flags, 39 response time calculations, C500 PCs, 380 response times, I/O, 376–387 rightmost, definition, 26 RS-232C communications one-to-one link, 430 procedures, 426 receiving, 428 transmitting, 427 connecting Units, 430 RS-232C port, wiring example, 420 S self-maintaining bits, using KEEP(11), 154 set value.
Revision History A manual revision code appears as a suffix to the catalog number on the front cover of the manual. Cat. No. W303-E1-4 Revision code The following table outlines the changes made to the manual during each revision. Page numbers refer to the previous version. Revision code 1 Date Revised content June 1996 2 January 1998 All Pages: “LSS” replaced with “SYSMAC Support Software.” Pages xiv, xvi: Cautions added. Page 7: One “4000” changed to “4096.
