Garage Door Opener User Manual

ManualsBrandsOmron ManualsGarage Door OpenerC200HS

Cat. No. W235-E1-5

Programmable Controllers

SYSMAC

C200HS

Summary of content (504 pages)

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Cat. No.
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C200HS Programmable Controllers Operation Manual Revised February 2002
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Notice: OMRON products are manufactured for use according to proper procedures by a qualified operator and only for the purposes described in this manual. The following conventions are used to indicate and classify precautions in this manual. Always heed the information provided with them. Failure to heed precautions can result in injury to people or damage to property. DANGER Indicates an imminently hazardous situation which, if not avoided, will result in death or serious injury.
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About this Manual: This manual describes the operation of the C200HS C-series Programmable Controllers, and it includes the sections described below. Installation information is provided in the C200HS Programmable Controller Installation Guide. A table of other manuals that can be used in conjunction with this manual is provided in Section 1 Introduction. Provided in Section 2 Hardware Considerations is a description of the differences between the older CPUs and the new CPUs described in this manual.
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TABLE OF CONTENTS PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 3 4 5 6 xiii Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Safety Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of contents 3-4-10 I/O Verification Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4-11 First Cycle Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4-12 Clock Pulse Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4-13 Step Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4-14 Group-2 Error Flag . . . . . . . . . . . . . . . . . . . .
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Table of contents 4-5-1 The Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5-2 PC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5-3 The Display Message Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Preparation for Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6-1 Entering the Password . . . . . . . . . . . . . . . . . . . .
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Table of contents 5-15 Data Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15-1 SHIFT REGISTER – SFT(10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15-2 REVERSIBLE SHIFT REGISTER – SFTR(84) . . . . . . . . . . . . . . . . . 5-15-3 ARITHMETIC SHIFT LEFT – ASL(25) . . . . . . . . . . . . . . . . . . . . . . 5-15-4 ARITHMETIC SHIFT RIGHT – ASR(26) . . . . . . . . . . . . . . . . . . . . . 5-15-5 ROTATE LEFT – ROL(27) . .
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Table of contents 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-19-11 BCD DIVIDE – DIV(33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19-12 DOUBLE BCD DIVIDE – DIVL(57) . . . . . . . . . . . . . . . . . . . . . . . . . 5-19-13 FLOATING POINT DIVIDE – FDIV(79) . . . . . . . . . . . . . . . . . . . . . . 5-19-14 SQUARE ROOT – ROOT(72) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Binary Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of contents 5-28 Advanced I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28-1 7-SEGMENT DISPLAY OUTPUT – 7SEG(––) . . . . . . . . . . . . . . . . . 5-28-2 DIGITAL SWITCH INPUT – DSW(––) . . . . . . . . . . . . . . . . . . . . . . . 5-28-3 HEXADECIMAL KEY INPUT – HKY(––) . . . . . . . . . . . . . . . . . . . . 5-28-4 TEN KEY INPUT – TKY(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28-5 MATRIX INPUT – MTR(––) . . . . . . . .
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Table of contents SECTION 10 – Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10-2 10-3 10-4 10-5 10-6 391 Alarm Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmed Alarms and Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading and Clearing Errors and Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Messages . . . . . . . . . . . . . . . . .
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Table of contents xii Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 A – Standard Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B – Programming Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C – Error and Arithmetic Flag Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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PRECAUTIONS This section provides general precautions for using the Programmable Controller (PC) and related devices. The information contained in this section is important for the safe and reliable application of the PC. You must read this section and understand the information contained before attempting to set up or operate a PC system. 1 2 3 4 5 6 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Precautions . . . . . . . . . . .
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Operating Environment Precautions 1 4 Intended Audience This manual is intended for the following personnel, who must also have knowledge of electrical systems (an electrical engineer or the equivalent). • Personnel in charge of installing FA systems. • Personnel in charge of designing FA systems. • Personnel in charge of managing FA systems and facilities. 2 General Precautions The user must operate the product according to the performance specifications described in the operation manuals.
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Application Precautions ! Caution 5 5 The operating environment of the PC System can have a large effect on the longevity and reliability of the system. Improper operating environments can lead to malfunction, failure, and other unforeseeable problems with the PC System. Be sure that the operating environment is within the specified conditions at installation and remains within the specified conditions during the life of the system.
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Conformance to EC Directives 6 Section 6 Conformance to EC Directives Observe the following precautions when installing the C200HS-CPU01-EC and C200HS-CPU21-EC that conform to the EC Directives. Provide reinforced insulation or double insulation for the DC power source connected to the DC I/O Unit and for the Power Supply Unit. Use a separate power source for the DC I/O Unit from the external power supply for the Relay Output Unit.
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SECTION 1 Introduction This section gives a brief overview of the history of Programmable Controllers and explains terms commonly used in ladderdiagram programming. It also provides an overview of the process of programming and operating a PC and explains basic terminology used with OMRON PCs. Descriptions of peripheral devices used with the C200HS, a table of other manuals available to use with this manual for special PC applications, and a description of the new features of the C200HS are also provided.
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Section 1-2 The Origins of PC Logic 1-1 Overview A PC (Programmable Controller) is basically a CPU (Central Processing Unit) containing a program and connected to input and output (I/O) devices. The program controls the PC so that when an input signal from an input device turns ON, the appropriate response is made. The response normally involves turning ON an output signal to some sort of output device.
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OMRON Product Terminology 1-3 Section 1-4 PC Terminology Although also provided in the Glossary at the back of this manual, the following terms are crucial to understanding PC operation and are thus explained here. PC Because the C200HS is a Rack PC, there is no one product that is a C200HS PC. That is why we talk about the configuration of the PC, because a PC is a configuration of smaller Units.
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Section 1-5 Overview of PC Operation High-density I/O Units are designed to provide high-density I/O capability and include Group 2 High-density I/O Units and Special I/O High-density I/O Units. Special I/O Units are dedicated Units that are designed to meet specific needs. These include some of the High-density I/O Units, Position Control Units, Highspeed Counter Units, and Analog I/O Units. Link Units are used to create Link Systems that link more than one PC or link a single PC to remote I/O points.
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Section 1-7 Available Manuals Input/Output Requirements The first thing that must be assessed is the number of input and output points that the controlled system will require. This is done by identifying each device that is to send an input signal to the PC or which is to receive an output signal from the PC. Keep in mind that the number of I/O points available depends on the configuration of the PC. Refer to 3-3 IR Area for details on I/O capacity and the allocation of I/O bits to I/O points.
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Section 1-8 New C200HS Features Name Cat. No.
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Section 1-8 New C200HS Features 1-8-1 Improved Memory Capabilities Internal Memory (UM) The C200HS CPUs come equipped with 16 KW of RAM in the PC itself, so a very large memory capacity is available without purchasing a separate Memory Unit. Furthermore, the Ladder Program Area has been increased to 15.2 KW. Memory Cassettes Two types of Memory Cassettes are available for storage of data such as the program.
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Section 1-8 New C200HS Features I/O Refreshing Time The I/O refreshing time has been reduced for all units, as shown in the following table.
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Section 1-8 New C200HS Features TRSM(45) MCRO(99) MAX(--) MIN(--) SUM(--) SRCH(--) FPD(--) PID(--) HEX(--) XDMR(--) DSW(--) TKY(--) MTR(--) HKY(--) ADBL(--) SBBL(--) MBSL(--) DBSL(--) TRACE MEMORY SAMPLE MACRO FIND MAXIMUM FIND MINIMUM SUM DATA SEARCH FAILURE POINT DETECTION PID CONTROL ASCII TO HEX EXPANSION DM READ DIGITAL SWITCH INPUT TEN-KEY INPUT MATRIX INPUT 16-KEY INPUT DOUBLE BINARY ADD DOUBLE BINARY SUBTRACT DOUBLE SIGNED BINARY MULTIPLY DOUBLE SIGNED BINARY DIVIDE MBS(--) DBS(--) FCS(--) 7SEG(-
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Section 1-8 New C200HS Features 1-8-7 Built-in RS-232C Connector Host link communications are possible using the RS-232C connector built into the C200HS-CPU21-E/CPU23-E/CPU31-E/CPU33-E CPU. By using the TXD and RXD instructions, RS-232C communications is possible without using timeconsuming procedures. A 1-to-1 link using the LR Area or an NT link with the Programmable Terminal (PT) allows high-speed communications.
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Section 1-8 New C200HS Features I/O Comments Stored in PC By allocating a part of UM as the I/O Comment area, it is no longer necessary to read I/O Comments from a Peripheral Device’s floppy disk. If the Peripheral Device is connected to the C200HS online, the ladder diagram can be viewed with I/O comments. Online Editing A “CYCLE TIME OVER” error will no longer be generated when the program in the PC itself is being edited online.
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New C200HS Features Section 1-8 7. Transfer the program and and any other require data to the C200HS. You will probably want to transfer DM data and the I/O table, if you have created an I/O table for the C200H. 8. Turn the C200HS off and then back on to reset it. 9. Test program execution before attempting actual operation. Using Memory Cassettes 1, 2, 3... 12 The following procedure outlines the steps to transfer C200H programs to the C200HS via EEPROM or EPROM Memory Cassettes.
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New C200HS Features Section 1-8 10. Turn the C200HS off and then back on to reset it and transfer data from the Memory Cassette to the CPU. 11. Test program execution before attempting actual operation.
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SECTION 2 Hardware Considerations This section provides information on hardware aspects of the C200HS that are relevant to programming and software operation. These include CPU Components, basic PC configuration, CPU capabilities, and Memory Cassettes. This information is covered in detail in the C200HS Installation Guide. 2-1 2-2 2-3 2-4 2-5 2-6 CPU Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1-1 CPU Indicators . . . . . . . . . . . . .
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Section 2-1 CPU Components 2-1 CPU Components There are two groups of CPUs available, one that uses an AC power supply, and one that uses a DC power supply. Select one of the models shown below according to requirements of your control system. CPU model Power supply voltage C200HS-CPU01-E/CPU21-E/CPU31-E C200HS-CPU03-E/CPU23-E/CPU33-E 100 to 120 VAC or 200 to 240 VAC (voltage selector) 24 VDC The CPU21-E, CPU23-E, CPU31-E, and CPU33-E CPUs have an RS-232C connector.
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Section 2-1 CPU Components C200HS-CPU21-E/CPU23-E/CPU31-E/CPU33-E Indicators Power fuse (MF51NR, 5.2 dia. x 20 mm): C200HS-CPU21-E/CPU31-E: 2 A, 250 V C200HS-CPU23-E/CPU33-E: 5 A, 125 V Memory Casette compartment Bus connector: Available only with the CPU31-E and CPU33-E. Use this connector when SYSMAC NET Link Unit or SYSMAC LINK Unit is used.
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Section 2-2 PC Configuration 2-1-2 Peripheral Device Connection A Programming Console or IBM PC/AT running LSS can be used to program and monitor the C200HS PCs. Programming Console A C200H-PR027-E or CQM1-PRO01-E Programming Console can be connected as shown in the following diagram. The C200H-PR027-E is connected via the C200H-CN222 or C200H-CN422 Programming Console Connecting Cable, which must be purchased separately. A Connecting Cable is provided with the CQM1-PRO01-E.
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Section 2-3 CPU Capabilities Expansion I/O Racks An Expansion I/O Rack can be thought of as an extension of the PC because it provides additional slots to which other Units can be mounted. It is built onto an Expansion I/O Backplane to which a Power Supply and up to ten other Units are mounted. An Expansion I/O Rack is always connected to the CPU via the connectors on the Backplanes, allowing communication between the two Racks. Up to two Expansion I/O Racks can be connected in series to the CPU Rack.
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Section 2-4 Memory Cassettes C200HS Function C200HS Built-in clock/calendar CPU01-E CPU21-E CPU31-E CPU03-E CPU23-E CPU33-E Yes Error log Yes1 Data Trace Yes Differential Monitor Yes Expansion DM 3K words max.2 General-use DM 6K words Ladder Program capacity 15.2K words max2 SR Area SR 236 to SR 255 and SR 256 to SR 299 New instructions: (See 1-8-3 Larger Instruction Set for a list of the 36 new instructions.
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Section 2-5 Installing Memory Cassettes C200HS-MPj16K (EPROM) The program is written using a PROM Writer. The ROM is mounted to the Memory Casette and then installed in the CPU. I/O data cannot be stored. Notch 2-5 Installing Memory Cassettes An optional Memory Cassette can be installed in the C200HS. (The C200H Memory Unit cannot be used with the C200HS.) The two types of Memory Cassettes are described in 2-4 Memory Cassettes. To install a Memory Cassette, follow the procedure outlined below.
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Installing Memory Cassettes Section 2-5 3. Remove the bracket from the Memory Cassette, as shown in the illustration below. Metal bracket 4. Check that the connector side goes in first and that the Cassette’s circuit components face right and then insert the Cassette into the CPU. The Cassette slides in along a track in the CPU. 5. Replace the Memory Cassette bracket over the Cassette and tighten the screw that holds the bracket.
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Section 2-6 CPU DIP Switch 2-6 CPU DIP Switch The DIP switch on C200HS CPUs is located between the Memory Cassette compartment and battery. The 6 pins on the DIP switch control 6 of the CPU’s operating parameters. Pin no. 1 Item Memory protect Setting Function ON Program Memory and read-only DM (DM 6144 to DM 6655) data cannot be overwritten from a Peripheral Device. OFF Program Memory and read-only DM (DM 6144 to DM 6655) data can be overwritten from a Peripheral Device.
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SECTION 3 Memory Areas Various types of data are required to achieve effective and correct control. To facilitate managing this data, the PC is provided with various memory areas for data, each of which performs a different function. The areas generally accessible by the user for use in programming are classified as data areas. The other memory area is the UM Area, where the user’s program is actually stored.
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Section 3-1 Introduction 3-1 Introduction Details, including the name, size, and range of each area are summarized in the following table. Data and memory areas are normally referred to by their acronyms, e.g., the IR Area, the SR Area, etc. Area Size Range Comments I/O Area 480 bits IR 000 to IR 029 I/O words are allocated to the CPU Rack and Expansion I/O Racks by slot position.
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Data Area Structure Section 3-2 Work Bits and Words When some bits and words in certain data areas are not being used for their intended purpose, they can be used in programming as required to control other bits. Words and bits available for use in this fashion are called work words and work bits. Most, but not all, unused bits can be used as work bits. Those that can be used are described area-by-area in the remainder of this section.
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Section 3-2 Data Area Structure The same TC number can be used to designate either the present value (PV) of the timer or counter, or a bit that functions as the Completion Flag for the timer or counter. This is explained in more detail in 3-8 TC Area.
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Section 3-2 Data Area Structure Decimal Points Decimal points are used in timers only. The least significant digit represents tenths of a second. All arithmetic instructions operate on integers only. Signed and Unsigned Binary Data This section explains signed and unsigned binary data formats. Many instructions can use either signed or unsigned data and a few (CPS(––), CPSL(––), DBS(––), DBSL(––), MBS(––), and MBSL(––)) use signed data exclusively.
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Section 3-2 Data Area Structure The following table shows the corresponding decimal, 16-bit hexadecimal, and 32-bit hexadecimal values. Decimal 16-bit Hex 2147483647 2147483646 . . . 32768 32767 32766 . . . 2 1 0 –1 –2 . . . –32767 –32768 –32769 . . . –2147483647 –2147483648 32-bit Hex ––– ––– . . . ––– 7FFF 7FFE . . . 0002 0001 0000 FFFF FFFE . . . 8001 8000 ––– . . . ––– ––– 7FFFFFFF 7FFFFFFE . . . 00008000 00007FFF 00007FFE . . . 00000002 00000001 00000000 FFFFFFFF FFFFFFFE . . .
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Section 3-3 IR Area 3-3 IR (Internal Relay) Area The IR area is used both as data to control I/O points, and as work bits to manipulate and store data internally. It is accessible both by bit and by word. In the C200HS PC, the IR area is comprised of words 000 to 235 and 298 to 511. Words in the IR area that are used to control I/O points are called I/O words. Bits in I/O words are called I/O bits. Bits in the IR area which are not assigned as I/O bits can be used as work bits.
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Section 3-3 IR Area Allocation for Special I/O Units and Slave Racks Up to ten Special I/O Units may be mounted in any slot of the CPU Rack or Expansion I/O Racks. Up to five Slave Racks may be used, whether one or two Masters are used. IR area words are allocated to Special I/O Units and Slave Racks by the unit number on the Unit, as shown in the following tables.
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Section 3-4 SR Area Allocation for Group-2 High-density I/O Units and B7 Interface Units Group-2 High-density I/O Units and B7A Interface Units are allocated words between IR 030 and IR 049 according to I/O number settings made on them and do not use the words allocated to the slots in which they are mounted. For 32-point Units, each Unit is allocated two words; for 64-point Units, each Unit is allocated four words. The words allocated for each I/O number are in the following tables.
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Section 3-4 SR Area Note all SR words and bits are writeable by the user. Be sure to check the function of a bit or word before attempting to use it in programming.
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Section 3-4 SR Area Word(s) 254 255 256 to 261 262 263 Bit(s) Function 00 01 02 and 03 04 05 06 07 08 09 10 11 12 13 14 15 00 01 02 03 04 05 06 07 08 to 15 00 to 15 00 to 15 00 to 15 1-minute clock pulse bit 0.02-second clock pulse bit Reserved for function expansion. Do not use.
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Section 3-4 SR Area Word(s) 267 268 269 270 Bit(s) 00 to 04 05 06 to 12 13 14 and 15 00 to 15 00 to 07 08 to 10 Function Reserved by system (not accessible by user) Host Link Level 0 Send Ready Flag Reserved by system (not accessible by user) Host Link Level 1 Send Ready Flag Reserved by system (not accessible by user) Reserved by system (not accessible by user) Memory Cassette Contents 00: Nothing; 01: UM; 02: IOM (03: HIS) Memory Cassette Capacity 0: 0 KW (no cassette); 3: 16 KW 11 to 13 14 15 00 R
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Section 3-4 SR Area Word(s) 273 Bit(s) 00 01 02 to 11 12 13 14 274 275 276 277 to 279 280 to 289 290 to 293 294 to 297 298 to 299 Function Save IOM to Cassette Bit Data transferred to Memory Cassette when Bit is turned ON in PROGRAM mode. Bit will automatically turn OFF. An error will be produced if turned ON in any other Load IOM from Cassette Bit mode.
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Section 3-4 SR Area SYSMAC LINK Code Item Meaning 00 Normal end Processing ended normally. 01 Parameter error Parameters for network communication instruction is not within acceptable ranges. 02 Unable to send Unit reset during command processing or local node in not in network. 03 Destination not in network Destination node is not in network. 04 Busy error The destination node is processing data and cannot receive the command.
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Section 3-4 SR Area SYSMAC NET Operating p g l level l0 Operating p g l level l1 SR 238 Bit (Node numbers below) SR 242 15 8 14 7 13 6 12 5 11 4 10 3 09 2 08 1 07 8 06 7 05 6 04 5 03 4 02 3 01 2 00 1 SR 239 SR 243 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 SR 240 SR 244 24 23 22 21 20 19 18 17 24 23 22 21 20 19 18 17 SR 241 SR 245 32 31 30 29 28 27 26 25 32 31 30 29 28 27 26 25 1: PC CPU error 1: PC RUN status 3-4-2 Remote I/O
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Section 3-4 SR Area Host Link Systems Both Error flags and Restart bits are provided for Host Link Systems. Error flags turn ON to indicate errors in Host Link Units. Restart bits are turned ON and then OFF to restart a Host Link Unit. SR bits used with Host Link Systems are summarized in the following table. Rack-mounting Host Link Unit Restart bits are not effective for the Multilevel Rack-mounting Host Link Units. Refer to the Host Link System Manual for details.
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Section 3-4 SR Area Multilevel PC Link Systems Flag type Run flags Error flags Application Example Bit no.
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Section 3-4 SR Area Maintaining Status during Startup The status of SR 25211 and thus the status of force-set and force-reset bits can be maintained when power is turned off and on by enabling the Forced Status Hold Bit in the PC Setup. If the Forced Status Hold Bit is enabled, the status of SR 25211 will be preserved when power is turned off and on. If this is done and SR 25211 is ON, then the status of force-set and force-reset bits will also be preserved, as shown in the following table.
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Section 3-4 SR Area This bit can be programmed to activate an external warning for a low battery voltage. The operation of the battery alarm can be disabled in the PC Setup if desired. Refer to 3-6-4 PC Setup for details. 3-4-9 Cycle Time Error Flag SR bit 25309 turns ON if the cycle time exceeds 100 ms. The ALM/ERR indicator on the front of the CPU will also flash. Program execution will not stop, however, unless the maximum time limit set for the watchdog timer is exceeded.
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Section 3-4 SR Area 3-4-13 Step Flag SR bit 25407 turns ON for one cycle when step execution is started with the STEP(08) instruction. 3-4-14 Group-2 Error Flag SR bit 25414 turns ON for any of the following errors for Group-2 High-density I/O Units and B7A Interface Units: the same I/O number set twice, the same words allocated to more than one Unit, refresh errors. If one of these errors occurs, the Unit will stop operation and the ALARM indicator will flash, but the overall PC will continue operation.
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Section 3-4 SR Area Overflow Flag, OF SR bit 25404 turns ON when the result of a binary addition or subtraction exceeds 7FFF or 7FFFFFFF. Underflow Flag, UF SR bit 25405 turns ON when the result of a signed binary addition or subtraction exceeds 8000 or 80000000. Carry Flag, CY SR bit 25504 turns ON when there is a carry in the result of an arithmetic operation or when a rotate or shift instruction moves a “1” into CY. The content of CY is also used in some arithmetic operations, e.g.
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Section 3-4 SR Area 3-4-20 Peripheral Port Communications Areas Peripheral Port Error Code SR bits 26408 to 26411 are set when there is a peripheral port error in the General I/O Mode. Setting Error type 0 No error 1 Parity error 2 Framing error 3 Overrun error F Connected in Peripheral Mode Peripheral Port Communication Error Bit SR bit 26412 turns ON when there is a peripheral port communication error (effective in General I/O Mode).
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Section 3-4 SR Area Collation (Between DM and Memory Cassette) SR bit 27002 turns ON when data is verified between DM and a Memory Cassette. SR bit 27003 turns OFF when the contents of the verification coincide and turns ON when the contents of the verification do not coincide. 3-4-22 Data Transfer Error Bits Data will not be transferred from UM to the Memory Cassette if an error occurs (except for Board Checksum Error).
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Section 3-5 AR Area Save IOM to Cassette Bit SR bit 27300 turns ON when IOM is saved to a Memory Cassette. Load IOM from Cassette Bit SR bit 27301 turns ON when loading to IOM from a Memory Cassette. 3-4-26 Transfer Error Flags Data will not be transferred from IOM to the Memory Cassette if an error occurs (except for Read Only Error). Transfer Error Flag: Not PROGRAM mode SR bit 27312 turns ON when attempting to transfer data in other than Program Mode.
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Section 3-5 AR Area Word(s) 01 Bit(s) Function 00 to 09 Restart Bits for Special I/O Units 0 to 9 (also function as Restart Bits for PC Link Units) 10 Restart Bit for operating level 1 of SYSMAC LINK or SYSMAC NET Link System 11 Restart Bit for operating level 0 of SYSMAC LINK or SYSMAC NET Link System 12, 13 Not used. 14 Remote I/O Master Unit 1 Restart Flag. 15 Remote I/O Master Unit 0 Restart Flag.
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Section 3-5 AR Area Word(s) 24 Bit(s) Function 00 to 04 Reserved by system. 05 Cycle Time Flag 06 SYSMAC LINK System Network Parameter Flag for operating level 1 07 SYSMAC LINK System Network Parameter Flag for operating level 0 08 SYSMAC/SYSMAC NET Link Unit Level 1 Mounted Flag 09 SYSMAC/SYSMAC NET Link Unit Level 0 Mounted Flag 10 11 and 12 13 Reserved by system.
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Section 3-5 AR Area number, 0 through 31, and a letter, L or H. Bits are allocated as shown in the following table.
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Section 3-5 AR Area AR 0714 (Error History Reset Bit) is turned ON and then OFF by the user to reset the Error Record Pointer (DM 0969) and thus restart recording error records at the beginning of the history area. AR 0715 (Error History Enable Bit) is turned ON by the user to enable error history storage and turned OFF to disable error history storage. Refer to 3-6 DM Area for details on the Error History Area. Error history bits are refreshed each cycle.
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Section 3-5 AR Area 30-second Compensation Bit AR 2113 is turned ON to round the seconds of the Calendar/clock Area to zero, i.e., if the seconds is 29 or less, it is merely set to 00; if the seconds is 30 or greater, the minutes is incremented by 1 and the seconds is set to 00. Clock Stop Bit AR 2114 is turned OFF to enable the operation of the Calendar/clock Area and ON to stop the operation. Clock Set Bit AR 2115 is used to set the Calendar/clock Area as described below.
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Section 3-5 AR Area 3-5-11 Power OFF Counter AR 23 provides in 4-digit BCD the number of times that the PC power has been turned off. This counter can be reset as necessary using the PV Change 1 operation from the Programming Console. (Refer to 7-1-4 Hexadecimal/BCD Data Modification for details.) The Power OFF Counter is refreshed every time power is turned on. 3-5-12 Cycle Time Flag AR 2405 turns ON when the cycle time set with SCAN(18) is shorter than the actual cycle time.
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Section 3-6 DM Area 3-6 DM (Data Memory) Area The DM area is divided into various parts as described in the following table. A portion of UM (up to 3,000 words in 1,000-word increments) can be allocated as Expansion DM. Addresses DM 0000 to DM 0999 DM 1000 to DM 1999 DM 2000 to DM 5999 DM 6000 to DM 6030 DM 6100 to DM 6143 DM 6144 to DM 6599 DM 6600 to DM 6655 DM 7000 to DM 9999 Note User read/write Read/Write Read only Usage Normal DM. Special I/O Unit Area1 Normal DM.
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Section 3-6 DM Area 3-6-1 Expansion DM Area The expansion DM area is designed to provide memory space for storing operating parameters and other operating data for Link Units and Special I/O Units. Up to 3,000 words of UM can be allocated as Expansion DM (in 1K-word increments) using the UM ALLOCATION operation in the Programming Console or LSS. Expansion DM area addresses run from DM 7000 to DM 9999.
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Section 3-6 DM Area whether DM 1000 to DM 1999 or DM 7000 to 7999 will be used. Refer to 3-6-4 PC Setup for details.
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Section 3-6 DM Area The following table lists the possible error codes and corresponding errors.
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Section 3-6 DM Area The PC Setup is allocated to DM 6600 through DM 6655. Parameter Default Settings Remarks STARTUP MODE STARTUP MODE FORCED STATUS IOM HOLD BIT STATUS Programming Programming Console Console mode selector, previous mode selector mode (i.e., the mode in use last time power was interrupted), PROGRAM, MONITOR, or RUN Don’t hold Hold or don’t hold Determines the operating mode the PC will start in when power is turned ON. This setting is required for restart continuation.
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Section 3-8 TC Area 3-7 HR (Holding Relay) Area The HR area is used to store/manipulate various kinds of data and can be accessed either by word or by bit. Word addresses range from HR 00 through HR 99; bit addresses, from HR 0000 through HR 9915. HR bits can be used in any order required and can be programmed as often as required. The HR area retains status when the system operating mode is changed, when power is interrupted, or when PC operation is stopped.
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Section 3-11 TR Area 3-9 LR (Link Relay) Area The LR area is used as a common data area to transfer information between PCs. This data transfer is achieved through a PC Link System. Certain words will be allocated as the write words of each PC. These words are written by the PC and automatically transferred to the same LR words in the other PCs in the System.
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SECTION 4 Writing and Inputting the Program This section explains the basic steps and concepts involved in writing a basic ladder diagram program, inputting the program into memory, and executing it. It introduces the instructions that are used to build the basic structure of the ladder diagram and control its execution. The entire set of instructions used in programming is described in Section 5 Instruction Set. 4-1 Basic Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section 4-2 Instruction Terminology 4-1 Basic Procedure There are several basic steps involved in writing a program. Sheets that can be copied to aid in programming are provided in Appendix F Word Assignment Recording Sheets and Appendix G Program Coding Sheet. 1, 2, 3... 4-2 1. Obtain a list of all I/O devices and the I/O points that have been assigned to them and prepare a table that shows the I/O bit allocated to each I/O device. 2.
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Section 4-4 Basic Ladder Diagrams 4-3 Program Capacity The maximum user program size varies with the amount of UM allocated to expansion DM and the I/O Comment Area. Approximately 10.1 KW are available for the ladder program when 3 KW are allocated to expansion DM and 2 KW are allocated to I/O comments as shown below. Refer to the 3-10 UM Area for further information on UM allocation.
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Section 4-4 Basic Ladder Diagrams 4-4-1 Basic Terms Normally Open and Normally Closed Conditions Each condition in a ladder diagram is either ON or OFF depending on the status of the operand bit that has been assigned to it. A normally open condition is ON if the operand bit is ON; OFF if the operand bit is OFF. A normally closed condition is ON if the operand bit is OFF; OFF if the operand bit is ON.
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Section 4-4 Basic Ladder Diagrams Program Memory addresses start at 00000 and run until the capacity of Program Memory has been exhausted. The first word at each address defines the instruction. Any definers used by the instruction are also contained in the first word. Also, if an instruction requires only a single bit operand (with no definer), the bit operand is also programmed on the same line as the instruction.
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Section 4-4 Basic Ladder Diagrams LOAD and LOAD NOT The first condition that starts any logic block within a ladder diagram corresponds to a LOAD or LOAD NOT instruction. Each of these instruction requires one line of mnemonic code. “Instruction” is used as a dummy instruction in the following examples and could be any of the right-hand instructions described later in this manual. 00000 A LOAD instruction.
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Section 4-4 Basic Ladder Diagrams OR and OR NOT When two or more conditions lie on separate instruction lines which run in parallel and then join together, the first condition corresponds to a LOAD or LOAD NOT instruction; the other conditions correspond to OR or OR NOT instructions. The following example shows three conditions which correspond (in order from the top) to a LOAD NOT, an OR NOT, and an OR instruction. Again, each of these instructions requires one line of mnemonic code.
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Section 4-4 Basic Ladder Diagrams 4-4-4 OUTPUT and OUTPUT NOT The simplest way to output the results of combining execution conditions is to output it directly with the OUTPUT and OUTPUT NOT. These instructions are used to control the status of the designated operand bit according to the execution condition. With the OUTPUT instruction, the operand bit will be turned ON as long as the execution condition is ON and will be turned OFF as long as the execution condition is OFF.
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Section 4-4 Basic Ladder Diagrams Now you have all of the instructions required to write simple input-output programs. Before we finish with ladder diagram basic and go onto inputting the program into the PC, let’s look at logic block instruction (AND LOAD and OR LOAD), which are sometimes necessary even with simple diagrams. 4-4-6 Logic Block Instructions Logic block instructions do not correspond to specific conditions on the ladder diagram; rather, they describe relationships between logic blocks.
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Section 4-4 Basic Ladder Diagrams Analyzing the above ladder diagram in terms of mnemonic instructions, the condition for IR 00000 is a LOAD instruction and the condition below it is an OR instruction between the status of IR 00000 and that of IR 00001. The condition at IR 00002 is another LOAD instruction and the condition below is an OR NOT instruction, i.e., an OR between the status of IR 00002 and the inverse of the status of IR 00003.
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Section 4-4 Basic Ladder Diagrams The following diagram requires AND LOAD to be converted to mnemonic code because three pairs of parallel conditions lie in series. The two options for coding the programs are also shown.
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Section 4-4 Basic Ladder Diagrams The following diagram contains only two logic blocks as shown. It is not necessary to further separate block b components, because it can be coded directly using only AND and OR.
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Section 4-4 Basic Ladder Diagrams When working with complicated diagrams, blocks will ultimately be coded starting at the top left and moving down before moving across. This will generally mean that, when there might be a choice, OR LOAD will be coded before AND LOAD. The following diagram must be broken down into two blocks and each of these then broken into two blocks before it can be coded. As shown below, blocks a and b require an AND LOAD.
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Section 4-4 Basic Ladder Diagrams The following diagram requires an OR LOAD followed by an AND LOAD to code the top of the three blocks, and then two more OR LOADs to complete the mnemonic code.
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Section 4-4 Basic Ladder Diagrams Again, this diagram can be redrawn as follows to simplify program structure and coding and to save memory space.
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Section 4-5 The Programming Console 4-4-7 Coding Multiple Right-hand Instructions If there is more than one right-hand instruction executed with the same execution condition, they are coded consecutively following the last condition on the instruction line. In the following example, the last instruction line contains one more condition that corresponds to an AND with IR 00004.
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Section 4-5 The Programming Console Gray: Instruction and Data Area Keys Except for the SHIFT key on the upper right, the gray keys are used to input instructions and designate data area prefixes when inputting or changing a program. The SHIFT key is similar to the shift key of a typewriter, and is used to alter the function of the next key pressed. (It is not necessary to hold the SHIFT key down; just press it once and then press the key to be used with it.
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Section 4-6 Preparation for Operation 4-5-2 PC Modes The Programming Console is equipped with a switch to control the PC mode. To select one of the three operating modes—RUN, MONITOR, or PROGRAM— use the mode switch. The mode that you select will determine PC operation as well as the procedures that are possible from the Programming Console. RUN mode is the mode used for normal program execution.
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Section 4-6 Preparation for Operation 4. Confirm that the CPU’s POWER LED is lit and the following display appears on the Programming Console screen. (If the ALM/ERR LED is lit or flashing or an error message is displayed, clear the error that has occurred.) PASSWORD! 5. Enter the password. See 4-6-1 Entering the Password for details. 6. Clear memory. Skip this step if the program does not need to be cleared. See 4-6-3 Clearing Memory for details.
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Section 4-6 Preparation for Operation 4-6-3 Clearing Memory Using the Memory Clear operation it is possible to clear all or part of the UM area (RAM or EEPROM), and the IR, HR, AR, DM and TC areas. Unless otherwise specified, the clear operation will clear all of the above memory areas. The UM area will not be cleared if the write-protect switch (pin 1 of the CPU’s DIP switch) is set to ON.
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Section 4-6 Preparation for Operation The following procedure is used to clear memory completely. MEMORY ERR I/O VER ERR Continue pressing the CLR key once for each error message until “00000” appears on the display 00000 00000 00000MEMORY CLR? HR CNT DM 00000MEM ALLCLR? All clear 00000MEM ALLCLR END Partial Clear It is possible to retain the data in specified areas or part of the ladder program.
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Section 4-6 Preparation for Operation To leave the TC area uncleared and retain Program Memory addresses 00000 through 00122, input as follows: 00000 00000 00000 00000MEMORY CLR? HR CNT DM 00000MEMORY CLR? HR DM 00123MEMORY CLR? HR DM 00000MEMORY CLR END HR DM Memory Clear The memory clear operation clears all memory areas except the I/O comments and UM Allocation information. The key sequence for a partial memory clear is shown below.
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Section 4-6 Preparation for Operation It is necessary to register the I/O table if I/O Units are changed, otherwise an I/O verification error message, “I/O VER ERR” or “I/O SET ERROR”, will appear when starting programming operations. I/O Table Registration can be performed only in PROGRAM mode with the writeprotection switch (pin 1 of the CPU’s DIP switch) set to OFF (OFF=“WRITE”). Group-2 HIgh-density I/O Units will not be displayed in the I/O table when it is displayed using a host computer.
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Section 4-6 Preparation for Operation 4-6-6 Verifying the I/O Table The I/O Table Verification operation is used to check the I/O table registered in memory to see if it matches the actual sequence of I/O Units mounted. The first inconsistency discovered will be displayed as shown below. Every subsequent pressing of VER displays the next inconsistency. Note This operation can be executed only when the I/O table has been registered.
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Section 4-6 Preparation for Operation 4-6-7 Reading the I/O Table The I/O Table Read operation is used to access the I/O table that is currently registered in the CPU memory. This operation can be performed in any PC mode. Key Sequence [0 to 2] [0 to 9] Rack number Unit number Press the EXT key to select Remote I/O Slave Racks or Optical I/O Units.
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Section 4-6 Preparation for Operation Meaning of Displays I/O Unit Designations for Displays (see I/O Units Mounted in Remote Slave Racks, page 89) C500, 1000H/C2000H I/O Units No. of points Input Unit Output Unit 0*** 32 I*** II** 64 IIII 0000 16 00** C200H I/O Units No.
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Section 4-6 Preparation for Operation Remote I/O Slave Racks 00000IOTBL READ R**-*U=**** *** I/O word number I/O type: I, O i, o (see tables on previous page) Unit number (0 to 9) Remote I/O Slave Unit number (0 to 4) Remote I/O Master Unit number (0 or 1) Indicates a Remote I/O Rack Group-2 HIgh-density I/O Units 00000IOTBL READ *-*U=#*** 2: 4: 2 words (32 pts) 4 words (64 pts) I: O: Input Unit Output Unit Unit number (0 to 9) Indicates Group-2 HIgh-density I/O Unit Note Group-2 HIgh-density I/O U
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Section 4-6 Preparation for Operation Key Sequence Example 00000 00000 FUN (??) 00000IOTBL ?-?U= 00000IOTBL WRIT ???? 00000IOTBL CANC ???? 00000IOTBL CANC 9713 00000IOTBL CANC OK 4-6-9 SYSMAC NET Link Table Transfer (CPU31/33-E Only) The SYSMAC NET Link Table Transfer operation transfers a copy of the SYSMAC NET Link Data Link table to RAM or EEPROM program memory.This allows the user program and SYSMAC NET Link table to be written into EPROM together.
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Section 4-6 Preparation for Operation Key Sequence Example 00000 00000 FUN(??) 00000LINK TBL~UM (SYSMAC-NET)???? 00000LINK TBL~UM (SYSMAC-NET)9713 00000LINK TBL~UM OK The following indicates that the I/O table cannot be transferred.
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Inputting, Modifying, and Checking the Program 4-7 Section 4-7 Inputting, Modifying, and Checking the Program Once a program is written in mnemonic code, it can be input directly into the PC from a Programming Console. Mnemonic code is keyed into Program Memory addresses from the Programming Console. Checking the program involves a syntax check to see that the program has been written according to syntax rules.
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Section 4-7 Inputting, Modifying, and Checking the Program Example If the following mnemonic code has already been input into Program Memory, the key inputs below would produce the displays shown.
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Section 4-7 Inputting, Modifying, and Checking the Program Inputting SV for Counters and Timers The SV (set value) for a timer or counter is generally entered as a constant, although inputting the address of a word that holds the SV is also possible. When inputting an SV as a constant, CONT/# is not required; just input the numeric value and press WRITE. To designate a word, press CLR and then input the word address as described above.
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Section 4-7 Inputting, Modifying, and Checking the Program Example The following program can be entered using the key inputs shown below. Displays will appear as indicated.
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Section 4-7 Inputting, Modifying, and Checking the Program Error Messages The following error messages may appear when inputting a program. Correct the error as indicated and continue with the input operation. The asterisks in the displays shown below will be replaced with numeric data, normally an address, in the actual display. Message Cause and correction ****REPL ROM An attempt was made to write to write-protected RAM or EEPROM. Ensure that the write-protect switch is set to OFF.
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Inputting, Modifying, and Checking the Program Section 4-7 Many of the following errors are for instructions that have not yet been described yet. Refer to 4-8 Controlling Bit Status or to Section 5 Instruction Set for details on these. Type Type A Message ????? NO END INSTR CIRCUIT ERR LOCN ERR Type B The number of logic blocks and logic block instructions does not agree, i.e.
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Section 4-7 Inputting, Modifying, and Checking the Program Example The following example shows some of the displays that can appear as a result of a program check. 00000 00000PROG CHK CHKLVL (0-2)? 00064PROG CHK Display #1 Halts program check 00699CHK ABORTD Display #2 Check continues until END(01) 02000PROG CHK END (01)(02.
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Inputting, Modifying, and Checking the Program Section 4-7 4-7-5 Program Searches The program can be searched for occurrences of any designated instruction or data area address used in an instruction. Searches can be performed from any currently displayed address or from a cleared display. To designate a bit address, press SHIFT, press CONT/#, then input the address, including any data area designation required, and press SRCH.
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Section 4-7 Inputting, Modifying, and Checking the Program Example: Instruction Search 00000 00000 LD 00000 00200SRCH LD 00000 00202 LD 00000 02000SRCH END (01)(02.7KW) 00000 00100 00100 TIM 001 00203SRCH TIM 001 00203 TIM DATA #0123 Example: Bit Search 00000 00000CONT SRCH CONT 00005 00200CONT SRCH LD 00005 00203CONT SRCH AND 00005 02000 END (01)(02.
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Section 4-7 Inputting, Modifying, and Checking the Program To delete an instruction, display the instruction word of the instruction to be deleted and then press DEL and the up key. All the words for the designated instruction will be deleted. ! Caution Be careful not to inadvertently delete instructions; there is no way to recover them without reinputting them completely.
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Section 4-7 Inputting, Modifying, and Checking the Program Inserting an Instruction 00000 00000 OUT 00000 00000 OUT 00201 00207SRCH OUT 00201 00206READ AND NOT 00104 00206 AND 00000 00206 AND 00105 Find the address prior to the insertion point Program After Insertion Address Instruction 00000 00001 00002 00003 00004 00005 00006 00007 00008 00009 LD AND LD AND NOT OR LD AND AND AND NOT OUT END(01) Operands 00100 00101 00201 00102 –– 00103 00105 00104 00201 –– 00206INSERT? AND 00105 00207INSER
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Section 4-7 Inputting, Modifying, and Checking the Program 4-7-7 Branching Instruction Lines When an instruction line branches into two or more lines, it is sometimes necessary to use either interlocks or TR bits to maintain the execution condition that existed at a branching point. This is because instruction lines are executed across to a right-hand instruction before returning to the branching point to execute instructions on a branch line.
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Section 4-7 Inputting, Modifying, and Checking the Program The previous diagram B can be written as shown below to ensure correct execution. In mnemonic code, the execution condition is stored at the branching point using the TR bit as the operand of the OUTPUT instruction.
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Section 4-7 Inputting, Modifying, and Checking the Program When drawing a ladder diagram, be careful not to use TR bits unless necessary. Often the number of instructions required for a program can be reduced and ease of understanding a program increased by redrawing a diagram that would otherwise required TR bits. In both of the following pairs of diagrams, the bottom versions require fewer instructions and do not require TR bits.
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Section 4-7 Inputting, Modifying, and Checking the Program When an INTERLOCK instruction is placed before a section of a ladder program, the execution condition for the INTERLOCK instruction will control the execution of all instruction up to the next INTERLOCK CLEAR instruction.
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Section 4-7 Inputting, Modifying, and Checking the Program If IR 00000 in the above diagram is OFF (i.e., if the execution condition for the first INTERLOCK instruction is OFF), instructions 1 through 4 would be executed with OFF execution conditions and execution would move to the instruction following the INTERLOCK CLEAR instruction.
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Section 4-8 Controlling Bit Status The other type of jump is created with a jump number of 00. As many jumps as desired can be created using jump number 00 and JUMP instructions using 00 can be used consecutively without a JUMP END using 00 between them. It is even possible for all JUMP 00 instructions to move program execution to the same JUMP END 00, i.e., only one JUMP END 00 instruction is required for all JUMP 00 instruction in the program.
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Section 4-8 Controlling Bit Status 4-8-1 DIFFERENTIATE UP and DIFFERENTIATE DOWN DIFFERENTIATE UP and DIFFERENTIATE DOWN instructions are used to turn the operand bit ON for one cycle at a time. The DIFFERENTIATE UP instruction turns ON the operand bit for one cycle after the execution condition for it goes from OFF to ON; the DIFFERENTIATE DOWN instruction turns ON the operand bit for one cycle after the execution condition for it goes from ON to OFF.
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Section 4-9 Work Bits To create a self-maintaining bit, the operand bit of an OUTPUT instruction is used as a condition for the same OUTPUT instruction in an OR setup so that the operand bit of the OUTPUT instruction will remain ON or OFF until changes occur in other bits. At least one other condition is used just before the OUTPUT instruction to function as a reset. Without this reset, there would be no way to control the operand bit of the OUTPUT instruction.
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Section 4-9 Work Bits Work bits can be used to simplify programming when a certain combination of conditions is repeatedly used in combination with other conditions. In the following example, IR 00000, IR 00001, IR 00002, and IR 00003 are combined in a logic block that stores the resulting execution condition as the status of IR 24600. IR 24600 is then combined with various other conditions to determine output conditions for IR 00100, IR 00101, and IR 00102, i.e.
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Section 4-10 Programming Precautions This action is easily programmed by using IR 22500 as a work bit as the operand of the DIFFERENTIATE UP instruction (DIFU(13)). When IR 00000 turns ON, IR 22500 will be turned ON for one cycle and then be turned OFF the next cycle by DIFU(13). Assuming the other conditions controlling IR 00100 are not keeping it ON, the work bit IR 22500 will turn IR 00100 ON for one cycle only.
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Section 4-10 Programming Precautions Except for instructions for which conditions are not allowed (e.g., INTERLOCK CLEAR and JUMP END, see below), every instruction line must also have at least one condition on it to determine the execution condition for the instruction at the right. Again, diagram A , below, must be drawn as diagram B. If an instruction must be continuously executed (e.g.
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Section 4-11 Program Execution 4-11 Program Execution When program execution is started, the CPU cycles the program from top to bottom, checking all conditions and executing all instructions accordingly as it moves down the bus bar. It is important that instructions be placed in the proper order so that, for example, the desired data is moved to a word before that word is used as the operand for an instruction.
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SECTION 5 Instruction Set The C200HS PC has a large programming instruction set that allows for easy programming of complicated control processes. This section explains instructions individually and provides the ladder diagram symbol, data areas, and flags used with each. The C200HS can process more than 100 instructions that require function codes, but only 100 function codes (00 to 99) are available.
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5-16-2 MOVE NOT – MVN(22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16-3 BLOCK SET – BSET(71) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16-4 BLOCK TRANSFER – XFER(70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16-5 DATA EXCHANGE – XCHG(73) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16-6 SINGLE WORD DISTRIBUTE – DIST(80) . . . . . . . . . . . . . . . . . . . . 5-16-7 DATA COLLECT – COLL(81) . . . . . . . . . . . . . . .
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5-20-9 5-20-10 SIGNED BINARY DIVIDE – DBS(––) . . . . . . . . . . . . . . . . . . . . . . . . DOUBLE SIGNED BINARY DIVIDE – DBSL(––) . . . . . . . . . . . . . . 231 232 5-21 Special Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21-1 FIND MAXIMUM – MAX(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21-2 FIND MINIMUM – MIN(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21-3 AVERAGE VALUE – AVG(––) . . .
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Data Areas, Definer Values, and Flags 5-1 Section 5-3 Notation In the remainder of this manual, all instructions will be referred to by their mnemonics. For example, the Output instruction will be called OUT; the AND Load instruction, AND LD. If you’re not sure of the instruction a mnemonic is used for, refer to Appendix B Programming Instructions. If an instruction is assigned a function code, it will be given in parentheses after the mnemonic.
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Section 5-4 Differentiated Instructions ! Caution The IR and SR areas are considered as separate data areas. If an operand has access to one area, it doesn’t necessarily mean that the same operand will have access to the other area. The border between the IR and SR areas can, however, be crossed for a single operand, i.e., the last bit in the IR area may be specified for an operand that requires more than one word as long as the SR area is also allowed for that operand.
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Section 5-5 Expansion Instructions A non-differentiated instruction is executed each time it is cycled as long as its execution condition is ON. A differentiated instruction is executed only once after its execution condition goes from OFF to ON. If the execution condition has not changed or has changed from ON to OFF since the last time the instruction was cycled, the instruction will not be executed.
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Section 5-5 Expansion Instructions Code Mnemonic Name Page 17 (@)ASFT ASYNCHRONOUS SHIFT REGISTER 157 18 (@)SCAN CYCLE TIME 276 19 (@)MCMP MULTI-WORD COMPARE 169 47 (@)LMSG 32-CHARACTER MESSAGE 279 48 (@)TERM TERMINAL MODE 280 60 CMPL DOUBLE COMPARE 172 61 (@)MPRF GROUP-2 HIGH-DENSITY I/O REFRESH 282 62 (@)XFRB TRANSFER BITS 168 63 (@)LINE COLUMN TO LINE 200 64 (@)COLM LINE TO COLUMN 201 65 (@)SEC HOURS TO SECONDS 183 66 (@)HMS SECONDS TO HOURS 184 67 (@
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Coding Right-hand Instructions 5-6 Section 5-6 Coding Right-hand Instructions Writing mnemonic code for ladder instructions is described in Section 4 Writing and Inputting the Program. Converting the information in the ladder diagram symbol for all other instructions follows the same pattern, as described below, and is not specified for each instruction individually. The first word of any instruction defines the instruction and provides any definers.
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Section 5-6 Coding Right-hand Instructions The following diagram and corresponding mnemonic code illustrates the points described above.
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Section 5-6 Coding Right-hand Instructions Multiple Instruction Lines 00000 If a right-hand instruction requires multiple instruction lines (such as KEEP(11)), all of the lines for the instruction are entered before the right-hand instruction. Each of the lines for the instruction is coded, starting with LD or LD NOT, to form ‘logic blocks’ that are combined by the right-hand instruction. An example of this for SFT(10) is shown below.
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Section 5-7 Instruction Set Lists 5-7 Instruction Set Lists This section provides tables of the instructions available in the C200HS. The first table can be used to find instructions by function code. The second table can be used to find instruction by mnemonic. In both tables, the @ symbol indicates instructions with differentiated variations. Note Refer to 5-5 Expansion Instructions for a list of the expansion instructions.
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Section 5-7 Instruction Set Lists Mnemonic Code Words Name Page ASL (@) 25 2 ARITHMETIC SHIFT LEFT 154 ASR (@) 26 2 ARITHMETIC SHIFT RIGHT 154 AVG (@) –– 4 AVERAGE VALUE 235 BCD (@) 24 3 BINARY TO BCD 181 BCDL (@) 59 3 DOUBLE BINARY-TO-DOUBLE BCD 182 BCMP (@) 68 4 BLOCK COMPARE 174 BCNT (@) 67 4 BIT COUNTER 283 BIN (@) 23 3 BCD-TO-BINARY 180 BINL (@) 58 3 DOUBLE BCD-TO-DOUBLE BINARY 181 BSET (@) 71 4 BLOCK SET 160 CLC (@) 41 1 CLEAR CARRY 205 CMP
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Section 5-7 Instruction Set Lists Mnemonic Code Words Name Page LD NOT None 1 LOAD NOT 129 LINE (@) 63 4 COLUMN TO LINE 200 LMSG (@) 47 4 32-CHARACTER MESSAGE 279 MAX (@) –– 4 FIND MAXIMUM 233 MBS (@) –– 4 SIGNED BINARY MULTIPLY 229 MBSL (@) –– 4 DOUBLE SIGNED BINARY MULTIPLY 230 MCMP (@) 19 4 MULTI-WORD COMPARE 169 MCRO (@) 99 4 MACRO 260 MIN (@) –– 4 FIND MINIMUM 234 MLB (@) 52 4 BINARY MULTIPLY 224 MLPX (@) 76 4 4-TO-16 DECODER 185 MOV (@) 21
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Section 5-7 Instruction Set Lists Mnemonic Code Words Name Page SLD (@) 74 3 ONE DIGIT SHIFT LEFT 156 SNXT 09 2 STEP START 266 SRCH (@) –– 4 DATA SEARCH 289 SRD (@) 75 3 ONE DIGIT SHIFT RIGHT 156 STC (@) 40 1 SET CARRY 205 STEP 08 2 STEP DEFINE 266 SUB (@) 31 4 BCD SUBTRACT 207 SUBL (@) 55 4 DOUBLE BCD SUBTRACT 209 SUM (@) –– 4 SUM CALCULATION 237 TCMP (@) 85 4 TABLE COMPARE 175 TERM (@) 48 4 TERMINAL MODE 280 TIM None 2 TIMER 139 TIMH 15 3
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Section 5-8 Ladder Diagram Instructions 5-8 Ladder Diagram Instructions Ladder Diagram instructions include Ladder instructions and Logic Block instructions and correspond to the conditions on the ladder diagram. Logic block instructions are used to relate more complex parts.
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Section 5-9 Bit Control Instructions 5-8-2 AND LOAD and OR LOAD AND LOAD – AND LD Ladder Symbol 00000 00002 00001 00003 OR LOAD – OR LD 00000 00001 00002 00003 Ladder Symbol Description When instructions are combined into blocks that cannot be logically combined using only OR and AND operations, AND LD and OR LD are used.
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Section 5-9 Bit Control Instructions OUT turns ON the designated bit for an ON execution condition, and turns OFF the designated bit for an OFF execution condition. With a TR bit, OUT appears at a branching point rather than at the end of an instruction line. Refer to 4-7-7 Branching Instruction Lines for details. OUT NOT turns ON the designated bit for a OFF execution condition, and turns OFF the designated bit for an ON execution condition.
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Section 5-9 Bit Control Instructions Precautions DIFU(13) and DIFD(14) operation can be uncertain when the instructions are programmed between IL and ILC, between JMP and JME, or in subroutines. Refer to 5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03), 5-11 JUMP and JUMP END – JMP(04) and JME(05), and 5-23 Subroutines and Interrupt Control for details.
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Section 5-9 Bit Control Instructions 5-9-3 SET and RESET – SET and RSET Ladder Symbols Operand Data Areas B: Bit SET B IR, SR, AR, HR, LR B: Bit RSET B IR, SR, AR, HR, LR Description SET turns the operand bit ON when the execution condition is ON, and does not affect the status of the operand bit when the execution condition is OFF. RSET turns the operand bit OFF when the execution condition is ON, and does not affect the status of the operand bit when the execution condition is OFF.
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Section 5-9 Bit Control Instructions Description KEEP(11) is used to maintain the status of the designated bit based on two execution conditions. These execution conditions are labeled S and R. S is the set input; R, the reset input. KEEP(11) operates like a latching relay that is set by S and reset by R. When S turns ON, the designated bit will go ON and stay ON until reset, regardless of whether S stays ON or goes OFF.
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Section 5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) Example If a HR bit or an AR bit is used, bit status will be retained even during a power interruption. KEEP(11) can thus be used to program bits that will maintain status after restarting the PC following a power interruption. An example of this that can be used to produce a warning display following a system shutdown for an emergency situation is shown below. Bits 00002, 00003, and 00004 would be turned ON to indicate some type of error.
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Section 5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) IL(02) and ILC(03) do not necessarily have to be used in pairs. IL(02) can be used several times in a row, with each IL(02) creating an interlocked section through the next ILC(03). ILC(03) cannot be used unless there is at least one IL(02) between it and any previous ILC(03).
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Section 5-11 JUMP and JUMP END – JMP(04) and JME(05) Example The following diagram shows IL(02) being used twice with one ILC(03). Address 00000 IL(02) 00001 TIM TIM511 511 #0015 001.
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Section 5-14 Timer and Counter Instructions If the jump number for JMP(04) is 00, the CPU will look for the next JME(05) with a jump number of 00. To do so, it must search through the program, causing a longer cycle time (when the execution condition is OFF) than for other jumps. The status of timers, counters, bits used in OUT, bits used in OUT NOT, and all other status controlled by the instructions between JMP(04) 00 and JMP(05) 00 will not be changed.
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Section 5-14 Timer and Counter Instructions Any one TC number cannot be defined twice, i.e., once it has been used as the definer in any of the timer or counter instructions, it cannot be used again. Once defined, TC numbers can be used as many times as required as operands in instructions other than timer and counter instructions. TC numbers run from 000 through 511. No prefix is required when using a TC number as a definer in a timer or counter instruction.
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Section 5-14 Timer and Counter Instructions If the execution condition remains ON long enough for TIM to time down to zero, the Completion Flag for the TC number used will turn ON and will remain ON until TIM is reset (i.e., until its execution condition is goes OFF). The following figure illustrates the relationship between the execution condition for TIM and the Completion Flag assigned to it.
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Section 5-14 Timer and Counter Instructions Example 2: Extended Timers There are two ways to achieve timers that operate for longer than 999.9 seconds. One method is to program consecutive timers, with the Completion Flag of each timer used to activate the next timer. A simple example with two 900.0-second (15-minute) timers combined to functionally form a 30-minute timer. 00000 Address TIM 001 #9000 900.
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Section 5-14 Timer and Counter Instructions Example 4: One-Shot Bits 01000 The length of time that a bit is kept ON or OFF can be controlled by combining TIM with OUT or OUT NO. The following diagram demonstrates how this is possible. In this example, 00204 would remain ON for 1.5 seconds after 00000 goes ON regardless of the time 00000 stays ON. This is achieved by using 01000 as a self-maintaining bit activated by 00000 and turning ON 00204 through it. When TIM 001 comes ON (i.e.
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Section 5-14 Timer and Counter Instructions Bits can be programmed to turn ON and OFF at regular intervals while a designated execution condition is ON by using TIM twice. One TIM functions to turn ON and OFF a specified bit, i.e., the Completion Flag of this TIM turns the specified bit ON and OFF. The other TIM functions to control the operation of the first TIM, i.e.
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Section 5-14 Timer and Counter Instructions Each TC number can be used as the definer in only one TIMER or COUNTER instruction. If the cycle time is greater than 10 ms, use TC 000 through TC 015. Description TIMH(15) operates in the same way as TIM except that TIMH measures in units of 0.01 second. The cycle time affects TIMH(15) accuracy if TC 016 through TC 511 are used. If the cycle time is greater than 10 ms, use TC 000 through TC 015. Refer to 5-14-1 TIMER – TIM for operational details and examples.
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Section 5-14 Timer and Counter Instructions Precautions The PVs of totalizing timers in interlocked program sections are maintained when the execution condition for IL(02) is OFF. Unlike timers and high-speed timers, totalizing timers in jumped program sections do not continue timing, but maintain the PV. Power interruptions will reset timers. Totalizing timers will not restart after timing out unless the PV is changed to a value below the SV or the reset input is turned ON.
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Section 5-14 Timer and Counter Instructions Limitations Each TC number can be used as the definer in only one TIMER or COUNTER instruction. Description CNT is used to count down from SV when the execution condition on the count pulse, CP, goes from OFF to ON, i.e., the present value (PV) will be decremented by one whenever CNT is executed with an ON execution condition for CP and the execution condition was OFF for the last execution.
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Section 5-14 Timer and Counter Instructions The above CNT can be modified to restart from SV each time power is turned ON to the PC. This is done by using the First Cycle Flag in the SR area (25315) to reset CNT as shown below.
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Section 5-14 Timer and Counter Instructions tween when the Completion Flag for TIM 001 goes ON and TIM 001 is reset by its Completion Flag). TIM 001 is also reset by the Completion Flag for CNT 002 so that the extended timer would not start again until CNT 002 was reset by 00001, which serves as the reset for the entire extended timer. Because in this example the SV for TIM 001 is 5.0 seconds and the SV for CNT 002 is 100, the Completion Flag for CNT 002 turns ON when 5 seconds x 100 times, i.e.
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Section 5-14 Timer and Counter Instructions Limitations Each TC number can be used as the definer in only one TIMER or COUNTER instruction. Description The CNTR(12) is a reversible, up/down circular counter, i.e., it is used to count between zero and SV according to changes in two execution conditions, those in the increment input (II) and those in the decrement input (DI).
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Section 5-15 Data Shifting 5-15 Data Shifting All of the instructions described in this section are used to shift data, but in differing amounts and directions. The first shift instruction, SFT(10), shifts an execution condition into a shift register; the rest of the instructions shift data that is already in memory.
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Section 5-15 Data Shifting Example 1: Basic Application The following example uses the 1-second clock pulse bit (25502) so that the execution condition produced by 00005 is shifted into a 3-word register between IR 010 and IR 012 every second.
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Section 5-15 Data Shifting The program is set up so that a rotary encoder (00000) controls execution of SFT(10) through a DIFU(13), the rotary encoder is set up to turn ON and OFF each time a product passes the first sensor. Another sensor (00002) is used to detect faulty products in the shoot so that the pusher output and HR 0003 of the shift register can be reset as required.
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Section 5-15 Data Shifting Description SFTR(84) is used to create a single- or multiple-word shift register that can shift data to either the right or the left. To create a single-word register, designate the same word for St and E. The control word provides the shift direction, the status to be put into the register, the shift pulse, and the reset input. The control word is allocated as follows: 15 14 13 12 Not used.
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Section 5-15 Data Shifting 5-15-3 ARITHMETIC SHIFT LEFT – ASL(25) Ladder Symbols Description Operand Data Areas ASL(25) @ASL(25) Wd Wd Wd: Shift word IR, SR, AR, DM, HR, LR When the execution condition is OFF, ASL(25) is not executed. When the execution condition is ON, ASL(25) shifts a 0 into bit 00 of Wd, shifts the bits of Wd one bit to the left, and shifts the status of bit 15 into CY.
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Section 5-15 Data Shifting 5-15-5 ROTATE LEFT – ROL(27) Ladder Symbols Description Operand Data Areas ROL(27) @ROL(27) Wd Wd Wd: Rotate word IR, SR, AR, DM, HR, LR When the execution condition is OFF, ROL(27) is not executed. When the execution condition is ON, ROL(27) shifts all Wd bits one bit to the left, shifting CY into bit 00 of Wd and shifting bit 15 of Wd into CY.
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Section 5-15 Data Shifting 5-15-7 ONE DIGIT SHIFT LEFT – SLD(74) Ladder Symbols Operand Data Areas St: Starting word SLD(74) @SLD(74) St St E E IR, SR, AR, DM, HR, LR E: End word IR, SR, AR, DM, HR, LR Limitations St and E must be in the same data area, and St must be less than or equal to E. Description When the execution condition is OFF, SLD(74) is not executed. When the execution condition is ON, SLD(74) shifts data between St and E (inclusive) by one digit (four bits) to the left.
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Section 5-15 Data Shifting Precautions If a power failure occurs during a shift operation across more than 50 words, the shift operation might not be completed. Set the range between E and St to a maximum of 50 words. Flags ER: The St and E words are in different areas, or St is less than E. Indirectly addressed DM word is non-existent. (Content of ∗DM word is not BCD, or the DM area boundary has been exceeded.
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Section 5-16 Data Movement Description Control Word Flags Example When the execution condition is OFF, ASFT(17) does nothing and the program moves to the next instruction. When the execution condition is ON, ASFT(17) is used to create and control a reversible asynchronous word shift register between St and E. This register only shifts words when the next word in the register is zero, e.g., if no words in the register contain zero, nothing is shifted.
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Section 5-16 Data Movement 5-16-1 MOVE – MOV(21) Ladder Symbols Operand Data Areas S: Source word MOV(21) @MOV(21) S S D D IR, SR, AR, DM, HR, TC, LR, # D: Destination word Description IR, SR, AR, DM, HR, LR When the execution condition is OFF, MOV(21) is not executed. When the execution condition is ON, MOV(21) copies the content of S to D. Source word Destination word Bit status not changed. Precautions TC numbers cannot be designated as D to change the PV of the timer or counter.
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Section 5-16 Data Movement 5-16-3 BLOCK SET – BSET(71) Operand Data Areas S: Source data Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # BSET(71) @BSET(71) S S St St E E St: Starting word IR, SR, AR, DM, HR, TC, LR E: End Word IR, SR, AR, DM, HR, TC, LR Limitations St must be less than or equal to E, and St and E must be in the same data area. Description When the execution condition is OFF, BSET(71) is not executed.
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Section 5-16 Data Movement Example 00003 The following example shows how to use BSET(71) to change the PV of a timer depending on the status of IR 00003 and IR 00004. When IR 00003 is ON, TIM 010 will operate as a 50-second timer; when IR 00004 is ON, TIM 010 will operate as a 30-second timer.
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Section 5-16 Data Movement Flags ER: N is not BCD between 0000 and 2000. S and S+N or D and D+N are not in the same data area. Indirectly addressed DM word is non-existent. (Content of ∗DM word is not BCD, or the DM area boundary has been exceeded.
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Data Movement Section 5-16 Stack Operation (C=9000 to 9999) When the execution condition is OFF, DIST(80) is not executed. When the execution condition is ON, DIST(80) operates a stack from DBs to DBs+C–9000. DBs is the stack pointer, so S is copied to the word indicated by DBs and DBs is incremented by 1. Digits of C: 3 2 1 0 Specifies the stack length (000 to 999). A value of 9 indicates stack operation. Data can be added to the stack until it is full.
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Section 5-16 Data Movement 5-16-7 DATA COLLECT – COLL(81) Operand Data Areas SBs: Source base word Ladder Symbols IR, SR, AR, DM, HR, TC, LR COLL(81) @COLL(81) SBs SBs C C D D C: Offset data (BCD) IR, SR, AR, DM, HR, TC, LR, # D: Destination word IR, SR, AR, DM, HR, TC, LR Limitations C must be a BCD. If C≤6655, SBs must be in the same data area as SBs+C. If the leftmost digit of C is 8 or 9, DBs must be in the same data area as SBs+N (N=the 3 rightmost digits of C).
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Section 5-16 Data Movement Example In the following example, the content of C (HR 00) is 9010, and COLL(81) is used to copy the oldest entries from a10-word stack (IR 001 to IR 010) to LR 20.
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Section 5-16 Data Movement Example In the following example, the content of C (HR 00) is 8010, and COLL(81) is used to copy the most recent entries from a 10-word stack (IR 001 to IR 010) to LR 20.
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Section 5-16 Data Movement Description When the execution condition is OFF, MOVB(82) is not executed. When the execution condition is ON, MOVB(82) copies the specified bit of S to the specified bit in D. The bits in S and D are specified by Bi. The rightmost two digits of Bi designate the source bit; the leftmost two bits designate the destination bit.
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Data Movement Section 5-16 Digit Designator The following show examples of the data movements for various values of Di. Di: 0010 Di: 0030 S D S D 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 S D S D 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 Di: 0031 Flags ER: Di: 0023 At least one of the rightmost three digits of Di is not between 0 and 3. Indirectly addressed DM word is non-existent. (Content of ∗DM word is not BCD, or the DM area boundary has been exceeded.
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Section 5-17 Data Comparison Example In the following example, XFRB(62) is used to transfer 5 bits from IR 020 to LR 21 when IR 00001 is ON. The starting bit in IR 020 is 0, and the starting bit in LR 21 is 4, so IR 02000 to IR 02004 are copied to LR 2104 to LR 2108.
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Section 5-17 Data Comparison Example The following example shows the comparisons made and the results provided for MCMP(19). Here, the comparison is made during each cycle when 00000 is ON.
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Section 5-17 Data Comparison Flags ER: Indirectly addressed DM word is non-existent. (Content of ∗DM word is not BCD, or the DM area boundary has been exceeded.) EQ: ON if Cp1 equals Cp2. LE: ON if Cp1 is less than Cp2. GR: ON if Cp1 is greater than Cp2. Flag C1 < C2 C1 = C2 C1 > C2 GR 25505 OFF OFF ON EQ 25506 OFF ON OFF LE 25507 ON OFF OFF The following example shows how to save the comparison result immediately.
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Section 5-17 Data Comparison The branching structure of this diagram is important in order to ensure that 00200, 00201, and 00202 are controlled properly as the timer counts down. Because all of the comparisons here use to the timer’s PV as reference, the other operand for each CMP(20) must be in 4-digit BCD. 00000 TIM 010 #5000 500.0 s CMP(20) TIM 010 #4000 25507 00200 Output at 100 s. 00200 CMP(20) TIM 010 #3000 25507 00201 Output at 200 s. 00201 CMP(20) TIM 010 #2000 25507 00202 Output at 300 s.
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Section 5-17 Data Comparison Limitations Cp1 and Cp1+1 must be in the same data area, as must Cp2 and Cp2+1. Description When the execution condition is OFF, CMPL(60) is not executed. When the execution condition is ON, CMPL(60) joins the 4-digit hexadecimal content of Cp1+1 with that of Cp1, and that of Cp2+1 with that of Cp2 to create two 8-digit hexadecimal numbers, Cp+1,Cp1 and Cp2+1,Cp2. The two 8-digit numbers are then compared and the result is output to the GR, EQ, and LE flags in the SR area.
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Section 5-17 Data Comparison 5-17-4 BLOCK COMPARE – BCMP(68) Operand Data Areas CD: Compare data Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # BCMP(68) @BCMP(68) CD CD CB CB R R CB: First comparison block word IR, DM, HR, TC, LR R: Result word IR, SR, AR, DM, HR, TC, LR Limitations Each lower limit word in the comparison block must be less than or equal to the upper limit. Description When the execution condition is OFF, BCMP(68) is not executed.
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Section 5-17 Data Comparison Example The following example shows the comparisons made and the results provided for BCMP(68). Here, the comparison is made during each cycle when 00000 is ON. 00000 BCMP(68) Address Instruction 00000 00001 LD BCMP(68) 001 HR 10 Operands 00000 HR 05 HR HR CD 001 001 Lower limits 0210 HR 10 HR 12 HR 14 HR 16 HR 18 HR 20 HR 22 HR 24 HR 26 HR 28 HR 30 HR 32 HR 34 HR 36 HR 38 HR 40 Compare data in IR 001 (which contains 0210) with the given ranges.
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Section 5-17 Data Comparison Example The following example shows the comparisons made and the results provided for TCMP(85). Here, the comparison is made during each cycle when 00000 is ON. 00000 TCMP(85) 001 Address Instruction 00000 00001 LD TCMP(85) Operands 00000 HR 10 HR 05 CD: 001 001 Upper limits 0210 Compare the data in IR 001 with the given ranges.
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Section 5-17 Data Comparison Precautions Placing other instructions between ZCP(88) and the operation which accesses the EQ, LE, and GR flags may change the status of these flags. Be sure to access them before the desired status is changed. Flags ER: Indirectly addressed DM word is non-existent. (Content of ∗DM word is not BCD, or the DM area boundary has been exceeded.) EQ: ON if LL ≤ CD ≤ UL LE: ON if CD < LL. GR: ON if CD > UL. LL is greater than UL.
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Section 5-17 Data Comparison Description When the execution condition is OFF, ZCPL(––) is not executed. When the execution condition is ON, ZCPL(––) compares the 8-digit value in CD, CD+1 to the range defined by lower limit LL+1,LL and upper limit UL+1,UL and outputs the result to the GR, EQ, and LE flags in the SR area. The resulting flag status is shown in the following table.
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Section 5-17 Data Comparison Flags ER: Indirectly addressed DM word is non-existent. (Content of ∗DM word is not BCD, or the DM area boundary has been exceeded.) EQ: ON if Cp1 equals Cp2. LE: ON if Cp1 is less than Cp2. GR: ON if Cp1 is greater than Cp2.
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Section 5-18 Data Conversion 5-18 Data Conversion The conversion instructions convert word data that is in one format into another format and output the converted data to specified result word(s). Conversions are available to convert between binary (hexadecimal) and BCD, to 7-segment display data, to ASCII, and between multiplexed and non-multiplexed data. All of these instructions change only the content of the words to which converted data is being moved, i.e.
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Section 5-18 Data Conversion 5-18-2 DOUBLE BCD-TO-DOUBLE BINARY – BINL(58) Ladder Symbols Operand Data Areas S: First source word (BCD) BINL(58) @BINL(58) S S R R IR, SR, AR, DM, HR, TC, LR R: First result word Description Flags IR, SR, AR, DM, HR, LR When the execution condition is OFF, BINL(58) is not executed. When the execution condition is ON, BINL(58) converts an eight-digit number in S and S+1 into 32-bit binary data, and outputs the converted data to R and R+1.
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Section 5-18 Data Conversion Signed Binary Data BCD(24) cannot be used to convert signed binary data directly to BCD. To convert signed binary data, first determine whether the data is positive or negative. If it is positive, BCD(24) can be used to convert the data to BCD. If it is negative, use the 2’s COMPLEMENT – NEG(––) instruction to convert the data to unsigned binary before executing BCD(24). Refer to page 29 for details on signed binary data. Flags ER: S is greater than 270F.
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Section 5-18 Data Conversion 5-18-5 HOURS-TO-SECONDS – SEC(65) Operand Data Areas S: Beginning source word (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR SEC(65) @SEC(65) S S R R --- --- R: Beginning result word (BCD) IR, SR, AR, DM, HR, TC, LR ---: Not used. Limitations S and S+1 must be within the same data area. R and R+1 must be within the same data area. S and S+1 must be BCD and must be in the proper hours/minutes/seconds format.
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Section 5-18 Data Conversion 5-18-6 SECONDS-TO-HOURS – HMS(66) Operand Data Areas S: Beginning source word (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR HMS(66) @HMS(66) S S R R --- --- R: Beginning result word (BCD) IR, SR, AR, DM, HR, TC, LR ---: Not used. Limitations S and S+1 must be within the same data area. R and R+1 must be within the same data area. S and S+1 must be BCD and must be between 0 and 35,999,999 seconds.
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Section 5-18 Data Conversion 5-18-7 4-TO-16 DECODER – MLPX(76) Operand Data Areas S: Source word Ladder Symbols IR, SR, AR, DM, HR, TC, LR MLPX(76) @MLPX(76) S S C C R R C: Control word Limitations IR, SR, AR, DM, HR, TC, LR, # R: First result word IR, SR, AR, DM, HR, LR When the leftmost digit of C is 0, the rightmost two digits of C must each be between 0 and 3. When the leftmost digit of C is 1, the rightmost two digits of C must each be between 0 and 1.
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Section 5-18 Data Conversion Some example C values and the digit-to-word conversions that they produce are shown below. C: 0010 C: 0030 S S 0 R 0 R 1 R+1 1 R+1 2 2 R+2 3 3 R+3 C: 0031 C: 0023 S S 0 R 0 R 1 R+1 1 R+1 2 R+2 2 R+2 3 R+3 3 The following is an example of a one-digit decode operation from digit number 1 of S, i.e., here C would be 0001. Source word C Bit C (i.e., bit number 12) turned ON.
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Section 5-18 Data Conversion The 4 possible C values and the conversions that they produce are shown below. (In S, 0 indicates the rightmost byte and 1 indicates the leftmost byte.) C: 1000 C: 1001 S S 0 R to R+15 0 R to R+15 1 R+16 to R+31 1 R+16 to R+31 C: 1010 C: 1011 S S 0 R to R+15 0 R to R+15 1 R+16 to R+31 1 R+16 to R+31 The following is an example of a one-byte decode operation from the rightmost byte of S (C would be 1000 in this case).
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Section 5-18 Data Conversion The following program converts three digits of data from LR 20 to bit positions and turns ON the corresponding bits in three consecutive words starting with HR 10.
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Section 5-18 Data Conversion 16-bit to 4-bit encoder DMPX(77) operates as a 16-bit to 4-bit encoder when the leftmost digit of C is 0. When the execution condition is OFF, DMPX(77) is not executed. When the execution condition is ON, DMPX(77) determines the position of the highest ON bit in S, encodes it into single-digit hexadecimal value corresponding to the bit number, then transfers the hexadecimal value to the specified digit in R.
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Section 5-18 Data Conversion 256-bit to 8-bit Encoder DMPX(77) operates as a 256-bit to 8-bit encoder when the leftmost digit of C is set to 1. When the execution condition is OFF, DMPX(77) is not executed.
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Section 5-18 Data Conversion When 00000 is ON, the following diagram encodes IR words 010 and 011 to the first two digits of HR 20 and then encodes LR 10 and 11 to the last two digits of HR 20. Although the status of each source word bit is not shown, it is assumed that the bit with status 1 (ON) shown is the highest bit that is ON in the word.
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Section 5-18 Data Conversion Any or all of the digits in S may be converted in sequence from the designated first digit. The first digit, the number of digits to be converted, and the half of D to receive the first 7-segment display code (rightmost or leftmost 8 bits) are designated in Di. If multiple digits are designated, they will be placed in order starting from the designated half of D, each requiring two digits.
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Section 5-18 Data Conversion Example The following example shows the data to produce an 8. The lower case letters show which bits correspond to which segments of the 7-segment display. The table underneath shows the original data and converted code for all hexadecimal digits.
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Section 5-18 Data Conversion 5-18-10 ASCII CONVERT – ASC(86) Operand Data Areas S: Source word Ladder Symbols IR, SR, AR, DM, HR, TC, LR ASC(86) @ASC(86) S S Di Di D D Di: Digit designator IR, SR, AR, DM, HR, TC, LR, # D: First destination word IR, SR, AR, DM, HR, LR Limitations Di must be within the values given below All destination words must be in the same data area. Description When the execution condition is OFF, ASC(86) is not executed.
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Section 5-18 Data Conversion Some examples of Di values and the 4-bit binary to 8-bit ASCII conversions that they produce are shown below.
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Section 5-18 Data Conversion Limitations Di must be within the values given below. All source words must be in the same data area. Bytes in the source words must contain the ASCII code equivalent of hexadecimal values, i.e., 30 to 39 (0 to 9), 41 to 46 (A to F), or 61 to 66 (a to f). Description When the execution condition is OFF, HEX(––) is not executed.
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Section 5-18 Data Conversion Some examples of Di values and the 8-bit ASCII to 4-bit hexadecimal conversions that they produce are shown below.
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Section 5-18 Data Conversion Flags ER: Incorrect digit designator, or data area for destination exceeded. Indirectly addressed DM word is non-existent. (Content of ∗DM word is not BCD, or the DM area boundary has been exceeded.) In the following example, the 2nd byte of LR 10 and the 1st byte of LR 11 are converted to hexadecimal values and those values are written to the first and second bytes of IR 010.
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Section 5-18 Data Conversion The following table shows the functions and ranges of the parameter words: Parameter Function Range Comments P1 BCD point #1 (AY) 0000 to 9999 --- P1+1 Hex. point #1 (AX) 0000 to FFFF Do not set P1+1=P1+3. P1+2 BCD point #2 (BY) 0000 to 9999 --- P1+3 Hex. point #2 (BX) 0000 to FFFF Do not set P1+3=P1+1. The following diagram shows the source word, S, converted to D according to the line defined by points (AY, AX) and (BY, BX).
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Section 5-18 Data Conversion 5-18-13 COLUMN TO LINE – LINE(63) Operand Data Areas S: First word of 16 word source set Ladder Symbols IR, SR, AR, DM, HR, TC, LR LINE(63) @LINE(63) S S C C D D C: Column bit designator (BCD) Limitations IR, SR, AR, DM, HR, TC, LR, # D: Destination word IR, SR, AR, DM, HR, TC, LR S and S+15 must be in the same data area. C must be between #0000 and #0015. Description When the execution condition is OFF, LINE(63) is not executed.
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Section 5-18 Data Conversion 5-18-14 LINE TO COLUMN – COLM(64) Operand Data Areas S: Source word Ladder Symbols IR, SR, AR, DM, HR, TC, LR COLM(64) @COLM(64) S S D D C C D: First word of the destination set Limitations IR, AR, DM, HR, TC, LR C: Column bit designator (BCD) IR, SR, AR, DM, HR, TC, LR, # D and D+15 must be in the same data area. C must be between #0000 and #0015. Description When the execution condition is OFF, COLM(64) is not executed.
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Section 5-18 Data Conversion 5-18-15 2’S COMPLEMENT – NEG(––) Ladder Symbols Description Operand Data Areas NEG(––) @NEG(––) S: Source word S S IR, SR, AR, DM, HR, TC, LR, # R R R: Result word --- --- IR, SR, AR, DM, HR, LR Converts the four-digit hexadecimal content of the source word (S) to its 2’s complement and outputs the result to the result word (R). This operation is effectively the same as subtracting S from 0000 and outputting the result to R.
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Section 5-18 Data Conversion 5-18-16 DOUBLE 2’S COMPLEMENT – NEGL(––) Ladder Symbols Operand Data Areas NEGL(––) @NEGL(––) S: First source word S S IR, SR, AR, DM, HR, TC, LR R R R: First result word --- --- IR, SR, AR, DM, HR, LR Limitations S and S+1 must be in the same data area, as must R and R+1. Description Converts the eight-digit hexadecimal content of the source words (S and S+1) to its 2’s complement and outputs the result to the result words (R and R+1).
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Section 5-19 BCD Calculations 5-19 BCD Calculations The BCD calculation instructions – INC(38), DEC(39), ADD(30), ADDL(54), SUB(31), SUBL(55), MUL(32), MULL(56), DIV(33), DIVL(57), FDIV(79), and ROOT(72) – all perform arithmetic operations on BCD data. For INC(38) and DEC(39) the source and result words are the same. That is, the content of the source word is overwritten with the instruction result. All other instructions change only the content of the words in which results are placed, i.e.
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Section 5-19 BCD Calculations 5-19-3 SET CARRY – STC(40) Ladder Symbols STC(40) @STC(40) When the execution condition is OFF, STC(40) is not executed.When the execution condition is ON, STC(40) turns ON CY (SR 25504). Note Refer to Appendix C Error and Arithmetic Flag Operation for a table listing the instructions that affect CY. 5-19-4 CLEAR CARRY – CLC(41) Ladder Symbols CLC(41) @CLC(41) When the execution condition is OFF, CLC(41) is not executed.
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Section 5-19 BCD Calculations Example If 00002 is ON, the program represented by the following diagram clears CY with CLC(41), adds the content of LR 25 to a constant (6103), places the result in DM 0100, and then moves either all zeros or 0001 into DM 0101 depending on the status of CY (25504). This ensures that any carry from the last digit is preserved in R+1 so that the entire result can be later handled as eight-digit data.
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Section 5-19 BCD Calculations Flags ER: Au and/or Ad is not BCD. Indirectly addressed DM word is non-existent. (Content of ∗DM word is not BCD, or the DM area boundary has been exceeded.) Example CY: ON when there is a carry in the result. EQ: ON when the result is 0. When 00000 is ON, the following program adds two 12-digit numbers, the first contained in LR 20 through LR 22 and the second in DM 0012. The result is placed in LR 10 through HR 13.
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Section 5-19 BCD Calculations Flags ER: Mi and/or Su is not BCD. Indirectly addressed DM word is non-existent. (Content of ∗DM word is not BCD, or the DM area boundary has been exceeded.) ! Caution CY: ON when the result is negative, i.e., when Mi is less than Su plus CY. EQ: ON when the result is 0. Be sure to clear the carry flag with CLC(41) before executing SUB(31) if its previous status is not required, and check the status of CY after doing a subtraction with SUB(31).
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Section 5-19 BCD Calculations Note The actual SUB(31) operation involves subtracting Su and CY from 10,000 plus Mi. For positive results the leftmost digit is truncated. For negative results the 10s complement is obtained. The procedure for establishing the correct answer is given below.
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Section 5-19 BCD Calculations Flags ER: Mi, M+1,Su, or Su+1 are not BCD. Indirectly addressed DM word is non-existent. (Content of ∗DM word is not BCD, or the DM area boundary has been exceeded.) CY: ON when the result is negative, i.e., when Mi is less than Su. EQ: ON when the result is 0. The following example works much like that for single-word subtraction.
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Section 5-19 BCD Calculations 5-19-9 BCD MULTIPLY – MUL(32) Operand Data Areas Md: Multiplicand (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # MUL(32) @MUL(32) Md Md Mr Mr R R Mr: Multiplier (BCD) IR, SR, AR, DM, HR, TC, LR, # R: First result word IR, SR, AR, DM, HR LR Limitations R and R+1 must be in the same data area. Description When the execution condition is OFF, MUL(32) is not executed.
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Section 5-19 BCD Calculations 5-19-10 DOUBLE BCD MULTIPLY – MULL(56) Operand Data Areas Md: First multiplicand word (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR MULL(56) @MULL(56) Md Md Mr Mr R R Mr: First multiplier word (BCD) Limitations IR, SR, AR, DM, HR, TC, LR R: First result word IR, SR, AR, DM, HR LR Md and Md+1 must be in the same data area, as must Mr and Mr+1. R and R+3 must be in the same data area. Description When the execution condition is OFF, MULL(56) is not executed.
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Section 5-19 BCD Calculations Description When the execution condition is OFF, DIV(33) is not executed and the program moves to the next instruction. When the execution condition is ON, Dd is divided by Dr and the result is placed in R and R + 1: the quotient in R and the remainder in R + 1. Remainder Quotient R+1 R Dr Flags ER: Dd Dd or Dr is not in BCD. Indirectly addressed DM word is non-existent. (Content of ∗DM word is not BCD, or the DM area boundary has been exceeded.
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Section 5-19 BCD Calculations Description When the execution condition is OFF, DIVL(57) is not executed. When the execution condition is ON, DIVL(57) the eight-digit content of Dd and D+1 is divided by the content of Dr and Dr+1 and the result is placed in R to R+3: the quotient in R and R+1, the remainder in R+2 and R+3. Remainder R+3 R+2 Dr+1 Flags ER: Dr Quotient R+1 R Dd+1 Dd Dr and Dr+1 contain 0. Dd, Dd+1, Dr, or Dr+1 is not BCD. Indirectly addressed DM word is non-existent.
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Section 5-19 BCD Calculations To represent the floating point values, the rightmost seven digits are used for the mantissa and the leftmost digit is used for the exponent, as shown below. The mantissa is expressed as a value less than one, i.e., to seven decimal places.
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Section 5-19 BCD Calculations 00000 @MOV(21) HR 01 #0000 HR 00 0 0 0 0 HR 00 @MOV(21) 0000 #0000 HR 02 @MOV(21) HR 01 4 0 0 0 #4000 HR 00 0 0 0 0 HR 01 @MOV(21) 4000 #4000 HR 03 DM 0000 3 4 5 2 @MOVD(83) DM 0000 #0021 HR 01 4 3 4 5 HR 01 @MOVD(83) 0 HR 00 0 0 0 DM 0000 3 4 5 2 DM 0000 #0300 HR 00 @MOVD(83) HR 01 4 3 4 5 2 HR 00 0 0 0 HR 01 4 3 4 5 2 HR 00 0 0 0 HR 03 4 0 0 7 9 HR 02 0 0 0 DM 0003 2 4 3 6 9 DM 0002 6 2 0 DM 0001 #0021 HR 03 @MOVD(83) DM 0001 #0300
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Section 5-19 BCD Calculations 5-19-14 SQUARE ROOT – ROOT(72) Ladder Symbols Operand Data Areas Sq: First source word (BCD) ROOT(72) @ROOT(72) Sq Sq R R IR, SR, AR, DM, HR, TC, LR R: Result word IR, SR, AR, DM, HR, LR, Limitations Sq and Sq+1 must be in the same data area. Description When the execution condition is OFF, ROOT(72) is not executed. When the execution condition is ON, ROOT(72) computes the square root of the eight-digit content of Sq and Sq+1 and places the result in R.
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Section 5-19 BCD Calculations In this example, √6017 = 77.56, and 77.56 is rounded off to 78. 00000 @BSET(71) DM 0101 0 0 0 #0000 0 0 DM 0100 0 0 0 DM 0100 DM 0101 0000 010 6 0 1 @MOV(21) 010 0000 7 DM 0101 DM 0101 6 0 1 7 @ROOT(72) 0 DM 0100 0 0 0 DM 0100 60170000= 7756.
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Section 5-20 Binary Calculations 5-20 Binary Calculations Binary calculation instructions — ADB(50), SBB(51), MLB(52), DVB(53), ADBL(––), SBBL(––), MBS(––), MBSL(––), DBS(––), and DBSL(––) — perform arithmetic operations on hexadecimal data. Four of these instructions (ADB(50), SBB(51), ADBL(––), and SBBL(––)) can act on both normal and signed data, two (MLB(52) and DVB(53)) act only on normal data, and four (MBS(––), MBSL(––), DBS(––), and DBSL(––)) act only on signed binary data.
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Section 5-20 Binary Calculations Example 1: Adding Normal Data The following example shows a four-digit addition with CY used to place either #0000 or #0001 into R+1 to ensure that any carry is preserved.
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Section 5-20 Binary Calculations In the case below, 25,321 +(–13,253) = 12,068 (62E9 + CC3B = 2F24). Neither OF nor UF are turned ON. 6 + Au: LR 20 2 E 9 Ad: DM 0010 C C 3 B 2 Ad: DM 0010 F 2 4 Note The status of the CY flag can be ignored when adding signed binary data since it is relevant only in the addition of normal hexadecimal values.
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Section 5-20 Binary Calculations Example 1: Normal Data The following example shows a four-digit subtraction with CY used to place either #0000 or #0001 into R+1 to ensure that any carry is preserved.
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Section 5-20 Binary Calculations Example 2: Signed Binary Data In the following example, SBB(51) is used to subtract one 16-bit signed binary value from another. (The 2’s complement is used to express negative values). The effective range for 16-bit signed binary values is –32,768 (8000) to +32,767 (7FFF). The overflow flag (OF: SR 25404) is turned ON if the result exceeds +32,767 (7FFF) and the underflow flag (UF: SR 25405) is turned ON if the result falls below –32,768 (8000).
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Section 5-20 Binary Calculations 5-20-3 BINARY MULTIPLY – MLB(52) Operand Data Areas Md: Multiplicand word (binary) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # MLB(52) @MLB(52) Md Md Mr Mr R R Mr: Multiplier word (binary) IR, SR, AR, DM, HR, TC, LR, # R: First result word IR, SR, AR, DM, HR LR Limitations R and R+1 must be in the same data area. Description When the execution condition is OFF, MLB(52) is not executed.
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Section 5-20 Binary Calculations Precautions DVB(53) cannot be used to divide signed binary data. Use DBS(––) instead. Refer to 5-20-9 SIGNED BINARY DIVIDE – DBS(––) for details. Flags ER: Dr contains 0. Indirectly addressed DM word is non-existent. (Content of :DM word is not BCD, or the DM area boundary has been exceeded.) EQ: ON when the result is 0.
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Section 5-20 Binary Calculations ADBL(––) can also be used to add signed binary data. The underflow and overflow flags (SR 25404 and SR 25405) indicate whether the result has exceeded the lower or upper limits of the 32-bit signed binary data range. Refer to page 29 for details on signed binary data. Flags Example 1: Normal Data ER: Indirectly addressed DM word is non-existent. (Content of :DM word is not BCD, or the DM area boundary has been exceeded.
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Section 5-20 Binary Calculations In the case below, 1,799,100,099 + (–282,751,929) = 1,516,348,100 (6B3C167D + EF258C47 = 5A61A2C4). Neither OF nor UF are turned ON.
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Section 5-20 Binary Calculations Flags Example 1: Normal Data ER: Indirectly addressed DM word is non-existent. (Content of :DM word is not BCD, or the DM area boundary has been exceeded.) CY: ON when the result is negative, i.e., when Mi is less than Su plus CY. EQ: ON when the result is 0. OF: ON when the result exceeds +2,147,483,647 (7FFF FFFF). UF: ON when the result is below –2,147,483,648 (8000 0000).
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Section 5-20 Binary Calculations In the case below, 1,799,100,099 – (–282,751,929) = 2,081,851,958 (6B3C 167D – {EF25 8C47 – 1 0000 0000} = 7C16 8A36). Neither OF nor UF are turned ON.
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Section 5-20 Binary Calculations Example In the following example, MBS(––) is used to multiply the signed binary contents of IR 001 with the signed binary contents of DM 0020 and output the result to LR 21 and LR 22.
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Section 5-20 Binary Calculations Example In the following example, MBSL(––) is used to multiply the signed binary contents of IR 101 and IR 100 with the signed binary contents of DM 0021 and DM 0020 and output the result to LR 24 through LR 21.
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Section 5-20 Binary Calculations Example In the following example, DBS(––) is used to divide the signed binary contents of IR 001 with the signed binary contents of DM 0020 and output the result to LR 21 and LR 22.
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Section 5-21 Special Math Instructions Example In the following example, DBSL(––) is used to divide the signed binary contents of IR 002 and IR 001 with the signed binary contents of DM 0021 and DM 0020 and output the result to LR 24 through LR 21.
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Section 5-21 Special Math Instructions If bit 15 of C is ON and more than one address contains the same maximum value, the position of the lowest of the addresses will be output to D+1. The number of words within the range (N) is contained in the 3 rightmost digits of C, which must be BCD between 001 and 999. When bit 15 of C is OFF, data within the range is treated as normal binary and when it is ON the data is treated as signed binary.
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Section 5-21 Special Math Instructions If bit 14 of C is ON and more than one address contains the same minimum value, the position of the lowest of the addresses will be output to D+1. The number of words within the range (N) is contained in the 3 rightmost digits of C, which must be BCD between 001 and 999. When bit 15 of C is OFF, data within the range is treated as unsigned binary and when it is ON the data is treated as signed binary. Refer to page 29 for details on signed binary data.
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Section 5-21 Special Math Instructions On the Nth cycle, the previous value of S is written to last word in the range D+2 to D+N+1. The average value of the previous values stored in D+2 to D+N+1 is calculated and written to D, bit 15 of D+1 is turned ON, and the previous value pointer (the first 2 digits of D+1) is reset to zero. Each time that AVG(––) is executed, the previous value of S overwrites the content of the word indicated by the pointer and the new average value is calculated and written to D.
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Section 5-21 Special Math Instructions Example In the following example, the content of IR 040 is set to #0000 and then incremented by 1 each cycle. For the first two cycles, AVG(––) moves the content of IR 040 to DM 1002 and DM 1003. The contents of DM 1001 will also change (which can be used to confirm that the results of AVG(––) has changed). On the third and later cycles AVG(––) calculates the average value of the contents of DM 1002 to DM 1004 and writes that average value to DM 1000.
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Section 5-21 Special Math Instructions Description When the execution condition is OFF, SUM(––) is not executed. When the execution condition is ON, SUM(––) adds either the contents of words R1 to R1+N–1 or the bytes in words R1 to R1+N/2–1 and outputs that value to the destination words (D and D+1). The data can be summed as binary or BCD and will be output in the same form. Binary data can be either signed or unsigned.
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Section 5-21 Special Math Instructions Example In the following example, the BCD contents of the 8 words from DM 0000 to DM 0007 are added when IR 00001 is ON and the result is written to DM 0010 and DM 0011.
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Section 5-21 Special Math Instructions Examples Sine Function The following example demonstrates the use of the APR(69) sine function to calculate the sine of 30°. The sine function is specified when C is #0000. Address 00000 APR(69) #0000 00000 00001 Instruction 00000 DM 0000 # DM DM DM 0100 Input data, x 0 0 S: DM 0000 101 100 3 0 10–1 0 Cosine Function 10–1 5 D: DM 0100 10–2 10–3 0 0 10–4 0 Result data has four significant digits, fifth and higher digits are ignored.
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Section 5-21 Special Math Instructions Enter the coordinates of the m+1 end-points, which define the m line segments, as shown in the following table. Enter all coordinates in BIN form. Always enter the coordinates from the lowest X value (X1) to the highest (Xm). X0 is 0000, and does not have to be entered. Y Word Ym Coordinate C+1 Xm (max.
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Section 5-21 Special Math Instructions In this case, the input data word, IR 010, contains #0014, and f(0014) = #0726 is output to R, IR 011. Y $1F20 $0F00 (x,y) $0726 $0402 (0,0) $0005 $0014 $001A X $05F0 5-21-6 PID CONTROL – PID(––) Operand Data Areas Ladder Symbol S: Input word PID(––) IR, SR, AR, DM, HR, LR, S C: First parameter word C IR, SR, DM, HR, LR D D: Output word IR, SR, AR, DM, HR, LR Limitations C and C+32 must be within the same data area.
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Section 5-21 Special Math Instructions Parameter Settings Item Contents Setting range Set value (SV) This is the target value of the process being controlled. Binary data (of the same number of bits as specified for the input range) Proportional band This is the parameter for P control expressing the proportional control range/total control range. 0001 to 9999 (4 digits BCD); (0.1% to 999.9%, in units of 0.1%) Tik This is a constant expressing the strength of the integral operation.
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Section 5-21 Special Math Instructions When overshooting is prevented with simple PID control, stabilization of disturbances is slowed (1). If stabilization of disturbances is speeded up, on the other hand, overshooting occurs and response toward the target value is slowed (2). With feed-forward PID control, there is no overshooting, and response toward the target value and stabilization of disturbances can both be speeded up (3).
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Section 5-21 Special Math Instructions integral time is too short, the correction will be too strong and will cause hunting to occur. Integral Operation Step response Deviation 0 Operation 0 amount PI Operation and Integral Time Step response Deviation Operation amount 0 PI operation I operation P operation 0 Ti: Integral time Derivative Operation (D) Proportional operation and integral operation both make corrections with respect to the control results, so there is inevitably a response delay.
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Section 5-21 Special Math Instructions without hunting, integral operation to automatically correct any offset, and derivative operation to speed up the response to disturbances.
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Section 5-21 Special Math Instructions hunting will be reduced if the integral time is increased or the proportional band is enlarged. Control by measured PID (when loose hunting occurs) SV Enlarge I or P. • If the period is short and hunting occurs, it may be that the control system response is quick and the derivative operation is too strong. In that case, set the derivative operation lower. Control by measured PID (when hunting occurs in a short period) SV Lower D.
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Section 5-21 Special Math Instructions Creating the Program 1, 2, 3... Follow the procedure outlined below in creating the program. 1. Set the target value (binary 0000 to 0FFF) in DM 0000. 2. Input the PV of the temperature sensing element (binary 000 to 0FFF) in bits 0 to 11 of word 101. 3. Output the operation amount of the heater to bits 0 to 11 of word 110 by means of the first PID(––) instruction in the following program. 4.
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Section 5-22 Logic Instructions Note When using PID(––) or SCL(––), make the data settings in advance with a Peripheral Device such as the Programming Console or LSS.
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Section 5-22 Logic Instructions 5-22-2 LOGICAL AND – ANDW(34) Operand Data Areas Ladder Symbols I1: Input 1 IR, SR, AR, DM, HR, TC, LR, # Description ANDW(34) @ANDW(34) I1 I1 I2 I2 R R I2: Input 2 IR, SR, AR, DM, HR, TC, LR, # R: Result word IR, SR, AR, DM, HR, LR When the execution condition is OFF, ANDW(34) is not executed. When the execution condition is ON, ANDW(34) logically AND’s the contents of I1 and I2 bit-by-bit and places the result in R.
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Section 5-22 Logic Instructions 5-22-3 LOGICAL OR – ORW(35) Operand Data Areas I1: Input 1 Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # Description ORW(35) @ORW(35) I1 I1 I2 I2 R R I2: Input 2 IR, SR, AR, DM, HR, TC, LR, # R: Result word IR, SR, AR, DM, HR, LR When the execution condition is OFF, ORW(35) is not executed. When the execution condition is ON, ORW(35) logically OR’s the contents of I1 and I2 bit-by-bit and places the result in R.
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Section 5-22 Logic Instructions 5-22-4 EXCLUSIVE OR – XORW(36) Operand Data Areas I1: Input 1 Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # Description XORW(36) @XORW(36) I1 I1 I2 I2 R R I2: Input 2 IR, SR, AR, DM, HR, TC, LR, # R: Result word IR, SR, AR, DM, HR, LR When the execution condition is OFF, XORW(36) is not executed. When the execution condition is ON, XORW(36) exclusively OR’s the contents of I1 and I2 bit-by-bit and places the result in R.
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Section 5-23 Subroutines and Interrupt Control 5-22-5 EXCLUSIVE NOR – XNRW(37) Operand Data Areas I1: Input 1 Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # XNRW(37) @XNRW(37) I1 I1 I2 I2 R R I2: Input 2 Description IR, SR, AR, DM, HR, TC, LR, # R: Result word IR, SR, AR, DM, HR, LR When the execution condition is OFF, XNRW(37) is not executed. When the execution condition is ON, XNRW(37) exclusively NOR’s the contents of I1 and I2 bit-by-bit and places the result in R.
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Section 5-23 Subroutines and Interrupt Control INT(89) is used to control the interrupt signals received from the Interrupt Input Unit, and also to control the scheduling of the scheduled interrupt. INT(89) provides such functions as masking of interrupts (so that they are recorded but ignored) and clearing of interrupts. Refer to 5-23-2 Interrupts for more details on interrupts.
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Section 5-23 Subroutines and Interrupt Control The following setting is used for normal interrupt mode. Normal Interrupt Mode (C200H Compatible) DM 6620 0 0 0 0 In normal interrupt mode, the following processing will be completed once started even if an interrupt occurs The interrupt will be processed as soon as the current process is completed.
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Section 5-23 Subroutines and Interrupt Control The PC Setup for the C200HS contains settings in DM 6620 that disable refreshing in the normal cycle for specific Special I/O Units. This settings are as shown below. DM6620 12 Bit 15 00 1 0 0 * * * * Interrupt mode (1 = high-speed) * * * * * * Unit #0 Unit #1 . . . Unit #9 Note Disabling special I/O refreshing in the normal cycle to refresh special I/O in an interrupt subroutine is necessary only in the high-speed mode.
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Section 5-23 Subroutines and Interrupt Control If you must handle the same data both in the main program and in an interrupt subroutine, use programming such as that shown below to be sure that data concurrence is preserved, i.e., mask interrupts while read/writing data that is also handled in an interrupt subroutine. Masks all interrupts. (@)INT(89) 100 000 000 Reading and writing common data words Unmasks all interrupts.
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Section 5-23 Subroutines and Interrupt Control Description A subroutine can be executed by placing SBS(91) in the main program at the point where the subroutine is desired. The subroutine number used in SBS(91) indicates the desired subroutine. When SBS(91) is executed (i.e.
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Section 5-23 Subroutines and Interrupt Control The following diagram illustrates program execution flow for various execution conditions for two SBS(91).
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Section 5-23 Subroutines and Interrupt Control All subroutines must be programmed at the end of the main program. When one or more subroutines have been programmed, the main program will be executed up to the first SBN(92) before returning to address 00000 for the next cycle. Subroutines will not be executed unless called by SBS(91). END(01) must be placed at the end of the last subroutine program, i.e., after the last RET(93). It is not required at any other point in the program.
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Section 5-23 Subroutines and Interrupt Control In the following example, the contents of DM 0010 through DM 0013 are copied to SR 290 through SR 293, the contents of DM 0020 through DM 0023 are copied to SR 294 through SR 297, and subroutine 10 is called and executed. When the subroutine is completed, the contents of SR 294 through SR 297 are copied back to DM 0020 to DM 0023. Main program MCRO(99) 10 DM 0010 DM 0020 Main program SBN(92) 10 Subroutine RET(93) END(01) Note 1.
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Section 5-23 Subroutines and Interrupt Control Example The following examples shows the use of four MCRO(99) instructions that access the same subroutine. The program section on the left shows the same program without the use of MCRO(99).
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Section 5-23 Subroutines and Interrupt Control Description INT(89) is used to control interrupts and performs one of 8 functions depending on the values of C and N. As shown in the following tables, three of the functions act on input interrupts, three act on the scheduled interrupt, and the other two mask or unmask all interrupts.
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Section 5-23 Subroutines and Interrupt Control Flags ER: Indirectly addressed DM word is non-existent. (Content of :DM word is not BCD, or the DM area boundary has been exceeded.) C, and/or N are not within specified values. Example 1: Input Interrupt This example shows how to unmask a particular interrupt input. Input interrupt subroutines will be executed when the CPU receives the corresponding interrupt input, regardless of the location in the CPU’s cycle.
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Section 5-23 Subroutines and Interrupt Control The scheduled interrupt is disabled at the start of operation (the scheduled interrupt interval is 0), so the time to the first interrupt and scheduled interrupt interval must be set using INT(89) with N=004 and C=001/000. In the following diagram, the subroutine would be executed every 20 ms if the scheduled interrupt time unit is set to 10 ms in DM 6622 of the PC Setup. Main program First Cycle Flag Sets the time to first interrupt to 20 ms.
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Section 5-24 Step Instructions 5-24 Step Instructions The step instructions STEP(08) and SNXT(09) are used in conjunction to set up breakpoints between sections in a large program so that the sections can be executed as units and reset upon completion. A section of program will usually be defined to correspond to an actual process in the application. (Refer to the application examples later in this section.) A step is like a normal programming code, except that certain instructions (e.g.
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Section 5-24 Step Instructions Execution of a step is completed either by execution of the next SNXT(09) or by turning OFF the control bit for the step (see example 3 below). When the step is completed, all of the IR and HR bits in the step are turned OFF. All timers in the step except TTIM(––) are reset to their SVs. TTIM(––), counters, shift registers, bits set or reset with SET or RSET, and bits used in KEEP(11) maintain status. Two simple steps are shown below.
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Section 5-24 Step Instructions Flags 25407: Step Start Flag; turns ON for one cycle when STEP(08) is executed and can be used to reset counters in steps as shown below if necessary.
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Section 5-24 Step Instructions The following diagram demonstrates the flow of processing and the switches that are used for execution control.
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Section 5-24 Step Instructions The program for this process, shown below, utilizes the most basic type of step programming: each step is completed by a unique SNXT(09) that starts the next step. Each step starts when the switch that indicates the previous step has been completed turns ON. 00001 (SW1) SNXT(09) 12800 Process A started. STEP(08) 12800 Process A 00002 (SW2) SNXT(09) 12801 Process A reset. Process B started. STEP(08) 12801 Process B 00003 (SW3) SNXT(09) 12802 Process B reset.
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Section 5-24 Step Instructions Example 2: Branching Execution The following process requires that a product is processed in one of two ways, depending on its weight, before it is printed. The printing process is the same regardless of which of the first processes is used. Various sensors are positioned to signal when processes are to start and end.
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Section 5-24 Step Instructions The program for this process, shown below, starts with two SNXT(09) instructions that start processes A and B. Because of the way 00001 (SW A1) and 00002 (SB B1) are programmed, only one of these will be executed to start either process A or process B. Both of the steps for these processes end with a SNXT(09) that starts the step for process C. 00001 (SW A1) 00002 (SW B2) SNXT(09) HR 0000 00001 (SW A1) 00002 (SW B2) SNXT(09) HR 0001 STEP(08) HR 0000 Process A started.
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Step Instructions Section 5-24 Example 3: Parallel Execution The following process requires that two parts of a product pass simultaneously through two processes each before they are joined together in a fifth process. Various sensors are positioned to signal when processes are to start and end. SW1 Process A SW5 SW3 SW7 Process B Process E Process D Process C SW2 SW4 SW6 The following diagram demonstrates the flow of processing and the switches that are used for execution control.
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Section 5-24 Step Instructions 00001 (SW1 and SW2)) SNXT(09) LR 0000 Process A started. Process C started. SNXT(09) LR 0002 STEP(08) LR 0000 Process A 00002 (SW3) SNXT(09) LR 0001 Process A reset. Process B started. STEP(08) LR 0001 Process B 01101 LR 0003 Used to turn off process D. 00004 (SW5 and SW6) SNXT(09) LR 0004 Process E started. STEP(08) LR 0002 Process C 00003 (SW4) SNXT(09) LR 0003 Process C reset. Process D started.
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Section 5-25 Special Instructions Address Instruction 00000 00001 00002 00003 LD SNXT(09) SNXT(09) STEP(08) Operands 00001 0000 0002 0000 LR LR LR LD SNXT(09) STEP(08) Instruction 00102 STEP(08) 00002 0001 0001 LR LR Operands LR 0002 LR LR 00003 0003 0003 LR 0004 LR 00005 0005 --- Process C 00200 00201 00202 Process A 00100 00101 00102 Address LD SNXT(09) STEP(08) Process D 00300 STEP(08) Process B Process E 00100 00101 0003 00101 00101 LD OUT 01101 LR AND SNXT(09) 00004 0004
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Section 5-25 Special Instructions FAL(06) produces a non-fatal error and FAL(07) produces a fatal error. When FAL(06) is executed with an ON execution condition, the ALARM/ERROR indicator on the front of the CPU will flash, but PC operation will continue. When FALS(07) is executed with an ON execution condition, the ALARM/ERROR indicator will light and PC operation will stop. The system also generates error codes to the FAL area.
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Section 5-25 Special Instructions 5-25-3 TRACE MEMORY SAMPLING – TRSM(45) Data tracing can be used to facilitate debugging programs. To set up and use data tracing it is necessary to have a host computer running LSS; no data tracing is possible from a Programming Console. Data tracing is described in detail in the LSS Operation Manual. This section shows the ladder symbol for TRSM(45) and gives an example program.
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Section 5-25 Special Instructions The sampled data is written to trace memory, jumping to the beginning of the memory area once the end has been reached and continuing up to the start marker. This might mean that previously recorded data (i.e., data from this sample that falls before the start marker) is overwritten (this is especially true if the delay is positive). The negative delay cannot be such that the required data was executed before sampling was started.
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Section 5-25 Special Instructions In handling indirectly addressed messages (i.e. :DM), those with the lowest DM address values have higher priority. Clearing Messages To clear a message, execute FAL(06) 00 or clear it via a Programming Console using the procedure in 4-6-5 Clearing Error Messages. If the message data changes while the message is being displayed, the display will also change. Flags ER: Indirectly addressed DM word is non-existent.
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Section 5-25 Special Instructions Description LMSG(47) is used to output a 32-character message to a Programming Console. The message to be output must be in ASCII beginning in word S and ending in S+15, unless a shorter message is desired. A shorter message can be produced by placing a null character (00) into the string; no characters from the null character on will be output. To output to the Programming Console, it must be set in TERMINAL mode.
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Section 5-25 Special Instructions Example In the following example, TERM(48) is used to switch the Programming Console to TERMINAL mode when 00000 is ON. Be sure that pin 6 of the CPU’s DIP switch is OFF.
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Section 5-25 Special Instructions To refresh I/O words allocated to Special I/O Units (IR 100 to IR 199), indicate the unit numbers of the Units by designating IR 040 to IR 049 (see note). IR 040 to IR 049 correspond to Special I/O Units 0 to 9. For example, set St to IR 043 and E to IR 045 to refresh the I/O words allocated to Special I/O Units 3, 4, and 5. The I/O words allocated to those Units (IR 130 to IR 159) will be refreshed when IORF(97) is executed.
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Section 5-25 Special Instructions Refer to 6-1 Cycle Time for a table showing I/O refresh times for Group-2 High-density I/O Units. Flags ER: St or E is not BCD between #0000 and #0009. St is greater than E.
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Section 5-25 Special Instructions The function of bits in C are shown in the following diagram and explained in more detail below. C: 15 14 13 12 11 00 Number of items in range (N, BCD) 001 to 999 words or bytes First byte (when bit 13 is ON) 1 (ON): Rightmost 0 (OFF): Leftmost Calculation units 1 (ON): Bytes 0 (OFF): Words Not used. Set to zero. Number of Items in Range The number of items within the range (N) is contained in the 3 rightmost digits of C, which must be BCD between 001 and 999.
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Section 5-25 Special Instructions Example When IR 00000 is ON in the following example, the frame checksum (0008) is calculated for the 8 words from DM 0000 to DM 0007 and the ASCII equivalent (30 30 30 38) is written to DM 0011 and DM 0010.
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Section 5-25 Special Instructions When the execution condition is OFF, FPD(––) is not executed. When the execution condition is ON, FPD(––) monitors the time until the logic diagnostics condition goes ON, turning ON the diagnostic output. If this time exceeds T, the following will occur: 1, 2, 3... 1. An FAL(06) error is generated with the FAL number specified in the first two digits of C. If 00 is specified, however, an error will not be generated. 2.
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Section 5-25 Special Instructions D+1 contains the bit address code of the input condition, as shown below. The word addresses, bit numbers, and TC numbers are in binary.
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Section 5-25 Special Instructions Example In the following example, the FPD(––) is set to display the bit address and message (“ABC”) when a monitoring time of 123.4 s is exceeded.
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Section 5-25 Special Instructions 5-25-13 DATA SEARCH – SRCH(––) Ladder Symbols Operand Data Areas N: Number of words SRCH(––) @SRCH(––) N N R1 R1 C C IR, SR, AR, DM, HR, TC, LR, # R1: First word in range IR, SR, AR, DM, HR, TC, LR C: Comparison data, result word IR, SR, AR, DM, HR, LR Limitations N must be BCD between 0001 to 6656. R1 and R1+N–1 must be in the same data area. Description When the execution condition is OFF, SRCH(––) is not executed.
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Section 5-25 Special Instructions Example In the following example, the 10 word range from DM 0010 to DM 0019 is searched for addresses that contain the same data as DM 0000 (#FFFF). Since DM 0012 contains the same data, the EQ Flag (SR 25506) is turned ON and #0012 is written to DM 0001.
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Section 5-26 Network Instructions Example In the following example, the 100 word range from DM 7000 through DM 7099 is copied to DM 0010 through DM 0109 when IR 00001 is ON.
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Section 5-26 Network Instructions The status of bit 15 of C+1 determines whether the instruction is for a SYSMAC NET Link System or a SYSMAC LINK System. Control Data SYSMAC NET Link Systems The destination port number is always set to 0. Set the destination node number to 0 to send the data to all nodes. Set the network number to 0 to send data to a node on the same Subsystem (i.e., network). Refer to the SYSMAC NET Link System Manual for details.
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Section 5-26 Network Instructions Flags ER: The specified node number is greater than 126 in a SYSMAC NET Link System or greater than 62 in a SYSMAC LINK System. The sent data overruns the data area boundaries. Indirectly addressed DM word is non-existent. (Content of :DM word is not BCD, or the DM area boundary has been exceeded.) There is no SYSMAC NET Link/SYSMAC LINK Unit.
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Section 5-26 Network Instructions Refer to the SYSMAC LINK System Manual for details. SYSMAC LINK Systems Word C Bits 00 to 07 Bits 08 to 15 Number of words (0 to 256 in 4-digit hexadecimal, i.e., 0000hex to 0100hex) C+1 Response time limit (0.1 and 25.4 seconds in 2-digit hexadecimal without decimal point, i.e., 00hex to FFhex) Note: The response time will be 2 seconds if the limit is set to 0hex. There will be no time limit if the time limit is set to FFhex.
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Section 5-26 Network Instructions 5-26-3 About Network Communications SEND(90) and RECV(98) are based on command/response processing. That is, the transmission is not complete until the sending node receives and acknowledges a response from the destination node. Note that the SEND(90)/RECV(98) Enable Flag is not turned ON until the first END(01) after the transmission is completed. Refer to the SYSMAC NET Link System Manual or SYSMAC LINK System Manual for details about command/response operations.
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Section 5-26 Network Instructions SEND(90)/RECV(98) Enable Flag 00000 25204 12802 S KEEP(11) 12801 12800 prevents execution of SEND(90) until RECV(98) (below) has completed. IR 00000 is turned ON to start transmission. 12800 R 12800 @MOV(21) #000A DM 0000 @MOV(21) #0000 DM 0001 @MOV(21) #0003 DM 0002 Data is placed into control data words to specify the 10 words to be transmitted to node 3 in operating level 1 of network 00 (NSB).
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Section 5-27 Serial Communications Instructions Address Instruction 00000 00001 00002 00003 00004 00005 00006 LD AND AND NOT LD KEEP(11) LD @MOV(21) 00007 00008 00009 Operands 00000 25204 12802 12801 12800 12800 # DM 000A 0000 # DM 0000 0001 # DM 0003 00002 Operands AND NOT LD KEEP(11) LD AND AND NOT XFER(70) 12800 12803 12802 12802 25204 25203 # DM 00026 00027 LD @MOV(21) @MOV(21) 00028 0010 000 0002 00029 LD AND OUT LD AND DIFU(13) LD AND 0010 0020 0000 12800 25203 00200 12800 25204
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Section 5-27 Serial Communications Instructions Note RXD(––) is required to receive data via the peripheral port or RS-232C port only. Transmission sent from a host computer to a Host Link Unit are processed automatically and do not need to be programmed. ! Caution The PC will be incapable of receiving more data once 256 bytes have been received if received data is not read using RXD(––). Read data as soon as possible after the Reception Completed Flag is turned ON (SR 26414 for peripheral port).
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Section 5-27 Serial Communications Instructions 5-27-2 TRANSMIT – TXD(––) Operand Data Areas Ladder Symbols S: First source word TXD(––) @TXD(––) S S C C N N IR, SR, AR, DM, HR, TC, LR C: Control word IR, SR, AR, DM, HR, TC, LR, # N: Number of bytes IR, SR, AR, DM, HR, TC, LR, # Limitations S and S+(N÷2)–1 must be in the same data area. N must be BCD from #0000 to #0256. (#0000 to #0061 in host link mode) Description When the execution condition is OFF, TXD(––) is not executed.
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Section 5-27 Serial Communications Instructions The following diagram shows the format for host link command (TXD) sent from the C200HS. The C200HS automatically attaches the prefixes and suffixes, such as the node number, header, and FCS. @ X X Node number X X X X ......... X Header Data (122 ASCII characters max.) code (EX) X X FCS ∗ CR Terminator RS-232C Mode N must be BCD from #0000 to #0256.
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Section 5-28 Advanced I/O Instructions 5-28 Advanced I/O Instructions Advanced I/O instructions enable control, with a single instruction, of previously complex operations involving external I/O devices (digital switches, 7-segment displays, etc.). There are five advanced I/O instructions, as shown in the following table. All of these are expansion instructions and must be assigned to function codes before they can be used.
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Section 5-28 Advanced I/O Instructions If there are 8 digits of source data, they are placed in S and S+1, with the most significant digits placed in S+1. If there are 4 digits of source data, they are placed in S. 7SEG(––) displays the 4 or 8-digit data in 12 cycles, and then starts over and continues displaying the data. The 7-segment display must provide four data lines and one latch signal line for each display digit. Note 1.
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Section 5-28 Advanced I/O Instructions 2. The 7-segment display may require either positive or negative logic, depending on the model. 3. The 7-segment display must have 4 data signal lines and 1 latch signal line for each digit. Using the Instruction If the first word holding the data to be displayed is specified at S, and the output word is specified at O, and the SV taken from the table below is specified at C, then operation will proceed as shown below when the program is executed.
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Section 5-28 Advanced I/O Instructions 5-28-2 DIGITAL SWITCH INPUT – DSW(––) Ladder Symbols Operand Data Areas IW: Input word DSW(––) IR, SR, AR, HR, LR IW OW: Output word OW R IR, SR, AR, HR, LR R: First result word IR, SR, AR, DM, HR, LR Overview DSW(––) is used to read the value set on a digital switch connected to I/O Units. When the execution condition is OFF, DSW(––) is not executed.
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Section 5-28 Advanced I/O Instructions Hardware With this instruction, 8-digit BCD set values are read from a digital switch. DSW(––) utilizes 5 output bits and 8 input bits. Connect the digital switch and the Input and Output Units as shown in the diagram below. Output point 5 will be turned ON when one round of data is read, but there is no need to connect output point 5 unless required for the application.
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Section 5-28 Advanced I/O Instructions The following example illustrates connections for an A7B Thumbwheel Switch. ID212 Input Unit 0 1 2 3 4 5 6 7 8 9 A7B Thumbwheel Switch 10 11 12 8 4 2 1 13 14 OD212 15 COM COM Switch no. 8 7 6 5 4 3 2 1 C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Output Unit 15 DC COM Note The data read signal is not required in the example.
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Section 5-28 Advanced I/O Instructions Using the Instruction If the input word for connecting the digital switch is specified at for word A, and the output word is specified for word B, then operation will proceed as shown below when the program is executed. IW Four digits: 00 to 03 100 101 102 Input data Leftmost 4 digits 103 Eight digits: 00 to 03, 04 to 07 Wd 0 D+1 Rightmost 4 digits D 00 When only 4 digits are read, only word D is used.
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Section 5-28 Advanced I/O Instructions 5-28-3 HEXADECIMAL KEY INPUT – HKY(––) Ladder Symbols Operand Data Areas IW: Input word HKY(––) IR, SR, AR, HR, LR IW OW: Control signal output word OW D IR, SR, AR, HR, LR D: First register word IR, SR, AR, DM, HR, LR Limitations D and D+2 must be in the same data area. Overview When the execution condition is OFF, HKY(––) is not executed.
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Section 5-28 Advanced I/O Instructions Hardware This instruction inputs 8 digits in hexadecimal from a hexadecimal keyboard. It utilizes 5 output bits and 4 input bits. Prepare the hexadecimal keyboard, and connect the 0 to F numeric key switches, as shown below, to input points 0 through 3 and output points 0 through 3. Output point 4 will be turned ON while any key is being pressed, but there is no need to connect it unless required by the application.
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Section 5-28 Advanced I/O Instructions Using the Instruction If the input word for connecting the hexadecimal keyboard is specified at word A, and the output word is specified at word B, then operation will proceed as shown below when the program is executed. IW 00 01 02 03 16-key 0 to 9 to F 16-key selection control signals Status of 16 keys D+2 00 to 09 to 15 OW 04 Turn ON flags corresponding to input keys (The flags remain ON until the next input.) ON for a 12-cycle period if a key is pressed.
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Section 5-28 Advanced I/O Instructions 5-28-4 TEN KEY INPUT – TKY(––) Ladder Symbols Operand Data Areas IW: Input word TKY(––) IR, SR, AR, HR, LR IW D1: First register word D1 IR, SR, AR, DM, HR, LR D2 D2: Key input word IR, SR, AR, DM, HR, LR Limitations D1 and D1+1 must be in the same data area. Overview When the execution condition is OFF, TKY(––) is not executed. When the execution condition is ON, TKY(––) inputs data from a ten-key keypad connected to the input indicated by IW.
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Section 5-28 Advanced I/O Instructions Using the Instruction If the input word for connecting the 10-key keypad is specified for IW, then operation will proceed as shown below when the program is executed. IW D1+1 00 Before execution 01 02 D1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Input from 10-key to (1) 09 “1” key input D2 (2) 00 0 0 0 0 0 01 Turn ON flags corresponding to 10-key inputs (The flags remain ON until the next input.
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Section 5-28 Advanced I/O Instructions 5-28-5 MATRIX INPUT – MTR(––) Ladder Symbols Operand Data Areas IW: Input word MTR(––) IR, SR, AR, HR, LR IW OW: Output word OW IR, SR, AR, HR, LR D D: First destination word IR, SR, AR, DM, HR, LR Limitations D and D+3 must be in the same data area. Overview When the execution condition is OFF, MTR(––) is not executed. When the execution condition is ON, MTR(––) inputs data from an 8 × 8 matrix and records that data in D to D+3.
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Section 5-28 Advanced I/O Instructions Hardware This instruction inputs up to 64 signals from an 8 x 8 matrix using 8 input points and 8 output points. Any 8 x 8 matrix can be used. The inputs must be connected through a DC Input Unit with 8 or more points and the outputs must be connected through a Transistor Output Unit with 8 or more points. The basic wiring and timing diagrams for MTR(––) are shown below.
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Section 5-28 Advanced I/O Instructions Example The following examples shows programming MTR(––) in a scheduled subroutine, where IORF(97) is programmed to ensure that the I/O words used by MTR(––) are refreshed each time MTR(––) is executed. INT(89) 001 004 # 0002 INT(89) 000 004 # 0002 SBN(92) 99 MTR(––) S D1 D2 IORF(97) D1 D2 RET(93) END(01) Flags ER: Indirectly addressed DM word is non-existent. (Content of :DM word is not BCD, or the DM area boundary has been exceeded.
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SECTION 6 Program Execution Timing The timing of various operations must be considered both when writing and debugging a program. The time required to execute the program and perform other CPU operations is important, as is the timing of each signal coming into and leaving the PC in order to achieve the desired control action at the right time. This section explains the cycle and shows how to calculate the cycle time and I/O response times. 6-1 6-2 6-3 6-4 Cycle Time . . . . . . . . . . . . . . . . . . .
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Cycle Time 6-1 Section 6-1 Cycle Time To aid in PC operation, the average, maximum, and minimum cycle times can be displayed on the Programming Console or any other Programming Device and the maximum cycle time and current cycle time values are held in AR 26 and AR 27. Understanding the operations that occur during the cycle and the elements that affect cycle time is, however, essential to effective programming and PC operations.
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Section 6-1 Cycle Time Flowchart of CPU Operation Power application Clears IR area and resets all timers Initialization on power-up Checks I/O Unit connections Resets watchdog timer Checks hardware and Program Memory Overseeing processes NO Check OK? YES Resets watchdog timer and program address counter Sets error flags and turns ON or flashes indicator ERROR (Solid ON) Program execution Executes user program ALARM/ERROR ALARM (Flashing) End of program? Note A minimum cycle time can be set ei
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Section 6-1 Cycle Time The first three operations immediately after power application are performed only once each time the PC is turned on. The rest of the operations are performed in cyclic fashion. The cycle time is the time that is required for the CPU to complete one of these cycles. This cycle includes basically eight types of operation. 1, 2, 3... 1. Overseeing 2. Program execution 3. Cycle time calculation 4. I/O refreshing 5. Host Link Unit servicing 6. RS-232C port servicing 7.
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Section 6-1 Cycle Time PC Link Unit I/O Refresh I/O pts to refresh Time required (ms) Special I/O Unit Refresh 512 7.4 256 4.1 128 2.7 64 1.
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Section 6-2 Calculating Cycle Time Even if the cycle time does not exceed the set value of the watchdog timer, a long cycle time can adversely affect the accuracy of system operations as shown in the following table. Cycle time (ms) Online Editing ! Caution 6-2 Possible adverse affects 10 or greater TIMH(15) inaccurate when TC 016 through TC 511 are used. (Accuracy when using TC 000 through TC 0015 not affected.) 20 or greater 0.02-second clock pulse (SR 25401) not accurately readable.
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Section 6-2 Calculating Cycle Time Calculations The equation for the cycle time from above is as follows: Cycle time = Overseeing time + Program execution time + I/O refresh time + Peripheral device servicing time Process Calculation With Peripheral Device Without Peripheral Device Overseeing Fixed 0.7 ms 0.7 ms Program execution 0.47 µs/instruction × 5,000 instructions 2.35 ms 2.35 ms I/O refresh See below. 0.34 ms 0.34 ms Peripheral device servicing Minimum time 0.26 ms 0.
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Section 6-3 Instruction Execution Times Calculations The equation for the cycle time is as follows: Cycle time = Overseeing time + Program execution time + I/O refreshing time + Host Link Unit servicing time + Peripheral device servicing time Process Calculation With Peripheral Device Without Peripheral Device Overseeing Fixed 0.7 ms 0.7 ms Program execution 0.47 µs/instruction × 5,000 instructions 2.35 ms 2.35 ms I/O refresh See below. 2.58 ms 2.58 ms Host Link servicing Fixed 6.
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Section 6-3 Instruction Execution Times ON execution time (µs) OFF execution time (µs) AND LD --- 0.375 0.375 OR LD --- 0.375 0.375 OUT For IR and SR 23600 to SR 25515 0.563 0.563 For SR 25600 to SR 51115 0.938 0.563 For IR and SR 23600 to SR 25515 0.563 0.563 For SR 25600 to SR 51115 0.938 0.563 Constant for SV 1.125 R: 1.125 IL: 1.125 JMP: 1.125 R: 39.0875 Instruction OUT NOT TIM Conditions :DM for SV For designated words 256 to 511 CNT Constant for SV 1.
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Section 6-3 Instruction Execution Times Instruction SFT(10) Conditions With 1-word shift register With 100-word shift register With 250-word shift register KEEP(11) CNTR(12) DIFD(14) TIMH(15) MVN(22) 326 800.00 0.938 Constant for SV 38.20 --- --- Interrupt Constant for SV Normal cycle MOV(21) 340.00 0.563 Interrupt :DM for SV CMP(20) R: For SR 25600 to SR 51115 Normal cycle WSFT(16) OFF execution time (µs) 47.
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Section 6-3 Instruction Execution Times ON execution time (µs) OFF execution time (µs) When converting a word to a word 40.40 1.125 When converting :DM to :DM 74.80 When converting a word to a word 38.40 When converting :DM to :DM 72.80 When shifting a word 21.20 When shifting :DM 38.20 When shifting a word 21.20 When shifting :DM 38.20 When rotating a word 21.80 When rotating :DM 39.00 When rotating a word 21.80 When rotating :DM 39.00 When inverting a word 21.
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Section 6-3 Instruction Execution Times ON execution time (µs) OFF execution time (µs) Constant + word → word 43.20 1.5 Word + word → word 45.80 :DM + :DM → :DM 97.40 Constant – word → word 43.20 Word – word → word 45.80 :DM – :DM → :DM 97.40 Constant x word → word 36.00 Word x word → word 38.50 :DM x :DM → :DM 91.10 Word ÷ constant → word 36.70 Word ÷ word → word 39.30 :DM ÷ :DM → :DM 90.80 Word + word → word 45.50 :DM + :DM → :DM 99.00 Word – word → word 45.
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Section 6-3 Instruction Execution Times ON execution time (µs) OFF execution time (µs) When encoding a word to a word 48.90 1.5 When encoding :DM to :DM 185.90 When decoding a word to a word 53.20 When decoding 2 digits :DM to :DM 113.60 When decoding 4 digits :DM to :DM 126.00 Word ÷ word → word (equals 0) 118.20 Word ÷ word → word (doesn’t equal 0) 357.20 :DM ÷ :DM → :DM 409.20 Constant → (word + (word)) 49.00 :DM → (:DM + (:DM)) 106.70 (Word + (word)) → word 52.
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Section 6-3 Instruction Execution Times ON execution time (µs) OFF execution time (µs) TERM(––) Default code: (48) --- 16.40 1.5 CMPL(––) When comparing words to words 51.40 1.5 Default code: (60) When comparing :DM to :DM 85.90 MPRF(––) 1 Unit 33.70 Default code: (61) 10 Units 74.20 XFRB(––) Sending 1 bit from word to word 45.50 Default code: (62) Sending FF bits from :DM to :DM 241.90 LINE(––) Default code: (63) When transferring from words to a constant 102.
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Section 6-3 Instruction Execution Times Instruction FPD(––) SRCH(––) MAX(––) MIN(––) SUM(––) FCS(––) HEX(––) AVG(––) PID(––) XDMR(––) MTR(––) ADBL(––) SBBL(––) MBS(––) DBS(––) MBSL(––) DBSL(––) CPS(––) CPSL(––) Conditions ON execution time (µs) :DM-designated 4 digits 66.60 to 72.80 Word-designated 8 digits 56.70 to 64.80 :DM-designated 8 digits 74.20 to 82.30 Word designation, code output 121.00 to 147.50 :DM designation, message output 170.50 to 228.80 Constant for SV 78.
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Section 6-3 Instruction Execution Times ON execution time (µs) OFF execution time (µs) When converting a constant to a word 34.90 1.5 When converting a word to a word 37.50 When converting :DM to :DM 72.10 When converting a word to a word 47.00 When converting :DM to :DM 81.90 When comparing two words 71.90 When comparing two :DM 123.10 Word for SV 98.20 :DM for SV 150.00 When designating a word 55.7 When designating :DM 72.9 DM CS output 60.20 DM RD output 61.
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Section 6-4 I/O Response Time 6-4 I/O Response Time The I/O response time is the time it takes for the PC to output a control signal after it has received an input signal. The time it takes to respond depends on the cycle time and when the CPU receives the input signal relative to the input refresh period.
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Section 6-4 I/O Response Time Maximum I/O Response Time The PC takes longest to respond when it receives the input signal just after the I/O refresh phase of the cycle. In this case the CPU does not recognize the input signal until the end of the next cycle. The maximum response time is thus one cycle longer than the minimum I/O response time, except that the I/O refresh time would not need to be added in because the input comes just after it rather than before it.
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Section 6-4 I/O Response Time In looking at the following timing charts, it is important to remember the sequence in which processing occurs during the PC scan, particular that inputs will not produce programmed actions until the program has been executed. When calculating the response times involving inputs and outputs from another CPU connected by an I/O Link Unit, the cycle time of the controlling CPU and the cycle time of the PC to which the I/O Link Unit is mounted must both be considered.
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Section 6-4 I/O Response Time Example Calculations Calculations would be as shown below for an input ON delay of 1.5 ms, an output ON delay of 15 ms, and a cycle time of 20 ms. Minimum I/O Response Time Time = 1.5 ms + (20 ms x 3) + 15 ms = 76.5 ms Maximum I/O Response Time Time = 1.5 ms + (20 ms x 4) + 15 ms = 96.5 ms Note 1. The cycle time may be less than or equal to the remote I/O transmission time when there are Special I/O Units on Slave Racks.
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Section 6-4 I/O Response Time 6-4-4 PC Link Systems The processing that determines and the methods for calculating maximum and minimum response times from input to output are provided in this subsection. The following System and I/O program steps will be used in all examples below. This System contains eight PC Link Units.
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Section 6-4 I/O Response Time Inserting the following values into this equation produces a minimum I/O response time of 149.3 ms. Input ON delay: 1.5 ms Output ON delay: 15 ms Cycle time for PC of Unit 0: 20 ms Cycle time for PC of Unit 7: 50 ms Maximum Response Time The following diagram illustrates the data flow that will produce the maximum response time. Delays occur because signals or data is received just after they would be processed or because data is sent during processing.
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Section 6-4 I/O Response Time Induction sequence processing: 15 ms x (8 PCs – 8 PCs) = 0 ms Reducing Response Time I/O refresh bits for Unit 0 256 I/O refresh bits for Unit 7 256 IORF(97) can be used in programming to shorten the I/O response time greater than is possible by setting a high number of refresh bits. (Remember, increasing the number of refresh bits set on the back-panel LED shortens response time, but increases the cycle time of the PC.
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Section 6-4 I/O Response Time The minimum and maximum I/O response times are shown here, using as an example the following instructions executed at the master and the slave. In this example, communications proceed from the master to the slave. Output (LR) Input (LR) Input Output The following conditions are taken as examples for calculating the I/O response times.
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Section 6-4 I/O Response Time 3. Communications are completed just after the slave executes communications servicing. Input point I/O refresh Input ON delay Overseeing, communications, etc.
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Section 6-4 I/O Response Time Scheduled Interrupts Scheduled interrupt interval Hardware time clock Scheduled interrupt subroutine execution t3 t3 t3 t3 t3 = Software interrupt response time Total interrupt response time = t3 (software interrupt response time) The software interrupt response time depends on the interrupt response parameter setting in DM 6620 of the PC Setup. If the DM 6620 is set for the C200Hcompatible mode (0000), the software interrupt response time is less than 10 ms.
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Section 6-4 I/O Response Time Note Interrupt Input Pulse Width 1. If there are several elements that can cause interrupts or if the interrupt period is shorted than the average interrupt processing time, the interrupt subroutine will be executed and the main program will not be executed. This will cause the cycle monitoring time to be exceeded and an FALS 9F error will be generated, stopping PC operation. 2. The maximum interrupt program execution time is contained in SR 262 and SR 263.
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SECTION 7 Program Monitoring and Execution This section provides the procedures for monitoring and controlling the PC through a Programming Console. Refer to the LSS Operation Manual for LSS procedures if you are using a computer running LSS. 7-1 Monitoring Operation and Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1-1 Bit/Word Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1-2 Forced Set/Reset . . . . . . . . . . . . . . . . . .
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Monitoring Operation and Modifying Data 7-1 Section 7-1 Monitoring Operation and Modifying Data The simplest form of operation monitoring is to display the address whose operand bit status is to be monitored using the Program Read or one of the search operations. As long as the operation is performed in RUN or MONITOR mode, the status of any bit displayed will be indicated.
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Section 7-1 Monitoring Operation and Modifying Data Key Sequence Clears leftmost address Cancels monitor operation Examples The following examples show various applications of this monitor operation.
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Section 7-1 Monitoring Operation and Modifying Data Bit Monitor 00000 00000 LD 00001 00001 ^ ON 00000 CONT 00001 Note The status of TR bits SR flags SR 25503 to 25507 (e.g., the arithmetic flags), cleared when END(01) is executed, cannot be monitored.
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Section 7-1 Monitoring Operation and Modifying Data +Multiple Address Monitoring 00000 00000 TIM 000 T000 0100 00000 T000 0100 00001 T000 0100 00001 T000 OFF 0100 D000000001 T000 ^OFF 0100 D000000001 T000 10FF^ OFF 0100 T000D000000001 0100 10FF^ OFF D000000001 10FF^ OFF Cancels monitoring of leftmost address 00001 ^ OFF 00000 CONT 00001 00000 CHANNEL DM 0000 Monitor operation is cancelled 0000000001 S ONR OFF Indicates Force Reset in operation. Indicates Force Set in operation.
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Section 7-1 Monitoring Operation and Modifying Data Bit status will remain ON or OFF only as long as the key is held down; the original status will return as soon as the key is released. If a timer is started, the completion flag for it will be turned ON when SV has been reached. SHIFT and PLAY/SET or SHIFT and REC/RESET can be pressed to maintain the status of the bit after the key is released.
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Section 7-1 Monitoring Operation and Modifying Data The following displays show what happens when TIM 000 is set with 00100 OFF (i.e., 00500 is turned ON) and what happens when TIM 000 is reset with 00100 ON (i.e., timer starts operation, turning OFF 00500, which is turned back ON when the timer has finished counting down the SV). (This example is performed in MONITOR mode.) 0010000500 ^ OFF^ OFF Monitoring 00100 and 00500. 0010000500 = ON^ OFF Force set bit status.
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Section 7-1 Monitoring Operation and Modifying Data Example The following example shows the displays that appear when Restore Status is carried out normally. 00000 00000 00000FORCE RELE? 00000FORCE RELE END 7-1-4 Hexadecimal/BCD Data Modification When the Bit/Digit Monitor operation is being performed and a BCD or hexadecimal value is leftmost on the display, CHG can be input to change the value. SR words cannot be changed.
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Section 7-1 Monitoring Operation and Modifying Data Example The following example shows the effects of changing the PV of a timer. This example is in MONITOR mode 00000 00000 TIM 000 Monitor status of timer PV that will be changed. T000 0122 Timing PRES VAL? T000 0119 ???? PV decrementing Timing PRES VAL? T000 0100 0200 Timing T000 0199 PV changed. Timer/counter PVs can be changed even when the timer/counter is operating.
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Section 7-1 Monitoring Operation and Modifying Data 7-1-5 Hex/ASCII Display Change This operation converts DM data displays from 4-digit hexadecimal data to ASCII and vice versa. Key Sequence Word currently displayed. Example 00000 00000 CH DM 0000 Monitor the desired DM word. D0000 4412 354 D0000 ”AB” Press TR to change the display to ASCII code. D0000 4142 Press TR again to return the display to hexadecimal.
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Section 7-1 Monitoring Operation and Modifying Data 7-1-6 4-digit Hex/Decimal Display Change This operation converts data displays from normal or signed 4-digit hexadecimal data to decimal and vice versa. Decimal values from 0 to 65,535 are valid when inputting normal 4-digit hexadecimal data, and decimal values from –32,768 to +32,767 are valid when inputting signed 4-digit hexadecimal data. Key Sequence Single word or 3-word monitor currently displayed. [New data] TR TR Clear new input data.
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Section 7-1 Monitoring Operation and Modifying Data 7-1-7 8-digit Hex/Decimal Display Change This operation converts data displays from normal or signed, 4 or 8-digit hexadecimal data to decimal and vice versa. Decimal values from 0 to 4,294,967,295 are valid when inputting normal 8-digit hexadecimal data, and decimal values from –2,147,483,648 to +2,147,483,647 are valid when inputting signed 8-digit hexadecimal data. Key Sequence 3-word monitor currently displayed.
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Section 7-1 Monitoring Operation and Modifying Data 7-1-8 Differentiation Monitor This operation can be used to monitor the up or down differentiation status of bits in the IR, SR, AR, LR, HR, and TC areas. To monitor up or down differentiation status, display the desired bit leftmost on the bit monitor display, and then press SHIFT and the Up or Down Arrow Key. A CLR entry changes the Differentiation Monitor operation back to a normal bit monitor display.
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Section 7-1 Monitoring Operation and Modifying Data 7-1-9 3-word Monitor To monitor three consecutive words together, specify the lowest numbered word, press MONTR, and then press EXT to display the data contents of the specified word and the two words that follow it. A CLR entry changes the Three-word Monitor operation to a single-word display. Key Sequence Single-word monitor in progress Example 00000 00000 CHANNEL DM 0000 Specify the first of the 3 words you want to monitor.
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Section 7-1 Monitoring Operation and Modifying Data Example D0002D0001D0000 0123 4567 89AB 3-word Monitor in progress. D0002 3CH CHG? =0123 4567 89AB Stops in the middle of monitoring. D0002 3CH CHG? 0001 4567 89AB Input new data. D0002 3CH CHG? 0001=4567 89AB D0002 3CH CHG? 0001=2345 89AB D0002D0001D0000 0001 2345 89AB D0002D0001D0000 0001 4567 89AB 7-1-11 Resumes previous monitoring.
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Section 7-1 Monitoring Operation and Modifying Data Example 00000 00000 CHANNEL 000 c000 MONTR 0000000000001111 c001 MONTR 0000010101010100 00000 CHANNEL 001 00000 00000 CHANNEL DM 0000 D0000 FFFF D0000 MONTR 1111111111111111 D0000 FFFF 00000 CHANNEL DM 0000 0000S0100R0110SR Indicates Force Reset in effect Indicates Force Set in effect 360
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Monitoring Operation and Modifying Data Section 7-1 7-1-12 Binary Data Modification This operation assigns a new 16-digit binary value to an IR, HR, AR, LR, or DM word. The cursor, which can be shifted to the left with the up key and to the right with the down key, indicates the position of the bit that can be changed. After positioning to the desired bit, a 0 or a 1 can then be entered as the new bit value. The bit can also be Force Set or Force Reset by pressing SHIFT and either PLAY/SET or REC/RESET.
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Section 7-1 Monitoring Operation and Modifying Data Example 00000 00000 CHANNEL 000 00000 CHANNEL 001 c001 MONTR 0000010101010101 c001 CHG? =000010101010101 c001 CHG? 1=00010101010101 c001 CHG? 10=0010101010101 c001 CHG? 100=010101010101 c001 CHG? 100S=10101010101 c001 CHG? 100=010101010101 c001 CHG? 10=S010101010101 c001 CHG? 1=RS010101010101 c001 MONTR 10RS010101010101 IR bit 00115 IR bit 00100 7-1-13 Changing Timer/Counter SV There are two ways to change the SV of a timer or counter.
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Section 7-1 Monitoring Operation and Modifying Data Key Sequence Example Inputting New SV and Changing to Word Designation The following examples show inputting a new constant, changing from a constant to an address, and incrementing to a new constant.
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Section 7-1 Monitoring Operation and Modifying Data Incrementing and Decrementing 00000 00000 TIM 000 00201SRCH TIM 000 00201 TIM DATA #0123 00201 TIM DATA T000 #0123 #???? 00201DATA ? U/D T000 #0123 #0123 Current SV (during change operation) SV before the change 00201DATA ? T000 #0123 #0122 00201DATA ? T000 #0123 #0123 00201DATA ? T000 #0123 #0124 00201DATA ? T000 #0124 #???? 00201 TIM DATA #0124 364 Returns to original display with new SV
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Section 7-1 Monitoring Operation and Modifying Data 7-1-14 Expansion Instruction Function Code Assignments This operation is used to read or change the function codes assigned to expansion instructions. There are 18 function codes that can be assigned to expansion instructions: 17, 18, 19, 47, 48, 60 to 69, and 87 to 89. More than one function code can be assigned to an expansion instruction. Note Function Code Assignments can be read in any mode, but can be changed in PROGRAM mode only.
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Section 7-1 Monitoring Operation and Modifying Data 7-1-15 UM Area Allocation This operation is used to allocate part of the UM Area for use as expansion DM. It can be performed in PROGRAM mode only. Memory allocated to expansion DM is deducted from the ladder program area. The amount of memory available for the ladder program depends on the amount of RAM in the CPU. About 15.2 KW of memory is available with the16-KW RAM and about 31.2 KW is available with the 32-KW RAM.
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Section 7-1 Monitoring Operation and Modifying Data 7-1-16 Reading and Setting the Clock This operation is used to read or set the CPU’s clock. The clock can be read in any mode, but it can be set in MONITOR or PROGRAM mode only. The CPU will reject entries outside of the acceptable range, i.e., 01 to 12 for the month, 01 to 31 for the day of the month, 00 to 06 for the day of the week, or 00 to 60 for the seconds, but it will not recognize non-existent dates, such as 2/31.
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Section 7-1 Monitoring Operation and Modifying Data Expansion TERMINAL Mode PROGRAM The Programming Console can be put into Expansion TERMINAL mode by turning ON AR 0709. Pin 6 of the CPU’s DIP switch must be ON. BZ CONSOLE mode NO MESSAGE PROGRAM Switch the Programming Console to Expansion TERMINAL mode by turning AR 0709 ON. BZ Turn AR 0709 OFF to return to CONSOLE mode. 7-1-18 Keyboard Mapping The C200HS supports the expansion keyboard mapping as well as normal keyboard mapping.
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Section 7-1 Monitoring Operation and Modifying Data All bits from SR 27700 through SR 27909 will be turned OFF when AR 0708 is turned ON. Expansion keyboard mapping inputs are disabled when AR 0708 is ON. In addition to the keyboard mapping function, expansion TERMINAL mode allows messages output by MSG(46) and LMSG(47) to be displayed on the Programming Console. These messages will be erased if the Programming Console is switch back to CONSOLE mode.
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Section 7-1 Monitoring Operation and Modifying Data SR word 277 Bit 12 13 14 15 278 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 279 00 01 02 370 Corresponding key(s)
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Section 7-1 Monitoring Operation and Modifying Data SR word 279 Bit Corresponding key(s) 03 04 05 *3 06 07 VER 08 09 371
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SECTION 8 Communications This section provides an overview of the communications features provided by the C200HS. 8-1 8-2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameters for Host Link and RS-232C Communications . . . . . . . . . . . . . . . . . . 8-2-1 Standard Communications Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 8-2-2 Specific Communications Parameters . . . . . . . . . . . . . . . . . . . . . . . .
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Parameters for Host Link and RS-232C Communications 8-1 Section 8-2 Introduction The C200HS supports the following types of communications. • Communications with Programming Devices (e.g., Programming Console, LSS, or SSS.) • Host Link communications with personal computers and other external devices. • RS-232C (no-protocol) communications with personal computers and other external devices. • One-to-one link communications with another C200HS CPU or a CQM1 CPU.
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Parameters for Host Link and RS-232C Communications Section 8-2 8-2-1 Standard Communications Parameters The settings in DM 6645 and DM 6650 determine the main communications parameters, as shown in the following diagram. The settings in bits 00 through 07 and bits 12 through 15 are valid only when pin 5 on the CPU’s DIP switch is OFF. Bits 08 though 11 are valid only in a PC set as the master for a 1:1 link.
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Parameters for Host Link and RS-232C Communications Section 8-2 8-2-2 Specific Communications Parameters The following settings are valid only when pin 5 on the CPU’s DIP switch is turned OFF and DM 6645 and DM 6655 are set to specify using the settings in words DM 6646 and DM 6656. Be sure to set the communications parameters to the same settings for both ends of the communications. Bit 15 0 DM 6646: RS-232C port DM 6651: Peripheral port Transmission Frame Format (See table below.
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Parameters for Host Link and RS-232C Communications Section 8-2 8-2-3 Wiring Ports Use the wiring diagram shown below as a guide in wiring the port to the external device. Refer to documentation provided with the computer or other external device for wire details for it. The connections between the C200HS and a personal computer are illustrated below as an example. C200HS Personal computer Signal Pin No. Pin No.
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Parameters for Host Link and RS-232C Communications PC Setup Section 8-2 The following parameter in the PC Setup is used only when the Host Link communications mode is being used. Host Link Node Number A node number must be set for host link communications to differentiate between nodes when multiple nodes are participating in communications. Set the node number to 00 unless multiple nodes are connected in a network.
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Parameters for Host Link and RS-232C Communications Section 8-2 TXD(––) instruction. In all other cases, data transmission based on a TXD(––) instruction will be given first priority. Application Example This example shows a program for using the RS-232C port in the Host Link mode to transmit 10 bytes of data (DM 0000 to DM 0004) to a computer. From DM 0000 to DM 0004, “1234” is stored in every word. The default values are assumed for all of the PC Setup (i.e.
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Parameters for Host Link and RS-232C Communications PC Setup Section 8-2 Start and end codes or the amount of data to be received can be set as shown in the following diagrams if required for RS-232C communications. This setting is required only for RS-232C communications. The following settings are valid only with pin 5 on the CPU’s DIP switch is turned OFF.
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Parameters for Host Link and RS-232C Communications Section 8-2 Start and end codes are not included when the number of bytes to be transmitted is specified. The largest transmission that can be sent with or without start and end codes in 256 bytes, i.e., N will be between 254 and 256 depending on the designations for start and end codes. If the number of bytes to be sent is set to 0000, only the start and end codes will be sent. 256 bytes max. Start code Data End code To reset the RS-232C port (i.e.
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Parameters for Host Link and RS-232C Communications Application Example Section 8-2 This example shows a program for using the RS-232C port in the RS-232C mode to transmit 10 bytes of data (DM 0100 to DM 0104) to the computer, and to store the data received from the computer in the DM area beginning with DM 0200. Before executing the program, the following PC Setup setting must be made.
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Parameters for Host Link and RS-232C Communications Section 8-2 Plug: XM2A-0901 (OMRON) or equivalent Hood: XM2S-0901 (OMRON) or equivalent C200HS C200HS Signal Abb. Pin No. Pin No. Signal Abb. FG 1 1 FG SD 2 2 SD RD 3 3 RD RS 4 4 RS CS 5 5 CS – 6 6 – – 7 7 – – 8 8 – SG 9 9 SG Note Ground the FG terminals the C200HS to a resistance of 100 Ω or less. PC Setup To use a 1:1 link, the only settings necessary are the communications mode and the link words.
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Parameters for Host Link and RS-232C Communications Section 8-2 When the program is executed at both the master and the slave, the status of IR 001 of each Unit will be reflected in IR 100 of the other Unit. IR 001 is an input word and IR 100 is an output word.
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SECTION 9 Memory Cassette Operations This section describes how to manage both UM Area and IOM data via Memory Cassettes. mounted in the CPU. 9-1 9-2 9-3 9-4 Memory Cassettes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Cassette Settings and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UM Area Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM Area Data .
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Section 9-2 Memory Cassette Settings and Flags 9-1 Memory Cassettes The C200HS comes equipped with a built-in RAM for the user’s program so programs can be created even without installing a Memory Cassette. An optional Memory Cassette, however, can provide flexibility in handling program data, PC Setup data, DM data, I/O comment data, and other IOM Area data. Memory Cassettes can be used for the following purposes. • Saving, retrieving, and comparing data in the UM Area.
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Section 9-3 UM Area Data Word SR 270 Bit(s) 00 Save UM to Cassette Bit 01 Load UM from Cassette Bit 02 03 04 to 11 12 Collation Execution Flag Collation NG Flag Reserved by system (not accessible by user) Transfer Error Flag: Not Data will not be transferred from UM to the Memory PROGRAM mode Cassette if an error occurs ((except for Board Checksum E Error).
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Section 9-4 IOM Area Data 4. Turn on the CPU. 5. If the desired program or UM Area data is not already in the CPU, write the data or transfer it to the CPU. 6. Switch the C200HS to PROGRAM mode. 7. Turn ON SR 27000 from the LSS or a Programming Console. The UM Area data will be written to the Memory Card and SR 27000 will be turned OFF automatically. Reading Data The following procedures are used to read UM Area data from a Memory Cassette mounted in the C200HS CPU to the CPU.
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Section 9-4 IOM Area Data Note The data inside the Memory Cassette should be protected by turning on the write-protect switch whenever you are not planning to write to the Cassette. Writing Data The following procedure is used to write IOM data from the C200HS CPU to a Memory Cassette mounted in the CPU. 1, 2, 3... Reading Data 1. 2. 3. 4. 5. 6. Turn off the write-protect switch on the Memory Cassette to write-enable it. Make sure that power to the C200HS CPU is turned OFF.
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SECTION 10 Troubleshooting The C200HS provides self-diagnostic functions to identify many types of abnormal system conditions. These functions minimize downtime and enable quick, smooth error correction. This section provides information on hardware and software errors that occur during PC operation. Program input errors are described in 4-7 Inputting, Modifying, and Checking the Program.
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Section 10-4 Error Messages 10-1 Alarm Indicators The ALM/ERR indicator on the front of the CPU provides visual indication of an abnormality in the PC. When the indicator is ON (ERROR), a fatal error (i.e., ones that will stop PC operation) has occurred; when the indicator is flashing (ALARM), a nonfatal error has occurred. This indicator is shown in 2-1-1 CPU Indicators.
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Section 10-4 Error Messages The type of error can be quickly determined from the indicators on the CPU, as described below for the three types of errors. If the status of an indicator is not mentioned in the description, it makes no difference whether it is lit or not. After eliminating the cause of an error, clear the error message from memory before resuming operation. Asterisks in the error messages in the following tables indicate variable numeric data. An actual number would appear on the display.
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Section 10-4 Error Messages Error and message FAL no. Probable cause Possible correction 9A An error occurred in data transfer between a High-density I/O Unit and the CPU. Check AR 0205 to AR 0214 to identify the Unit with a problem, replace the Unit, and restart the PC. 9B An error has been detected in the PC Setup. This error will be generated when the setting is read or used for the first time. Check an correct PC Setup settings.
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Section 10-4 Error Messages Fatal Operating Errors The following error messages appear for errors that occur after program execution has been started. PC operation and program execution will stop and all outputs from the PC will be turned OFF when any of the following errors occur. No CPU indicators will be lit for the power interruption error. For all other fatal operating errors, the POWER and ALM/ERR indicators will be lit. The RUN output will be OFF. Error and message FAL no.
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Section 10-4 Error Messages Error and message Too many Units FAL no. E1 I/O UNIT OVER Probable cause Two or more Special I/O Units are set to the same unit number Two or more Group-2 High-density I/O Units are set to the same I/O number or I/O word. The I/O number of a 64-pt Group-2 High-density I/O Unit is set to 9. Two SYSMAC NET Link or SYSMAC LINK Units share the same operating level. Possible correction Perform the I/O Table Read operation to check unit numbers, and eliminate duplications.
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Section 10-5 Error Flags 10-5 Error Flags The following table lists the flags and other information provided in the SR and AR areas that can be used in troubleshooting. Details are provided in 3-4 SR Area and 3-5 AR Area.
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Section 10-5 Error Flags AR Area Address(es) 0000 to 0009 0010 0011 0012 0013 0014 0015 0200 to 0204 0205 to 0215 0215 0300 to 0315 0400 to 0415 0500 to 0515 0600 to 0615 0710 to 0712 0713 to 0715 1114 1115 1514 1515 398 Function Special I/O or PC Link Unit Error Flags SYSMAC LINK/SYSMAC NET Link Level 1 System Error Flags SYSMAC LINK/SYSMAC NET Link Level 0 System Error Flags Rack-mounting Host Link Unit Level 1 Error Flag Rack-mounting Host Link Unit Level 0 Error Flag Remote I/O Master Unit 1 Error Fl
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Section 10-6 Host Link Errors 10-6 Host Link Errors These error codes are received as the response code (end code) when a command received by the C200HS from a host computer cannot be processed. The error code format is as shown below. @ X X Node no. X X Header code X X End code X X FCS : ↵ Terminator The header code will vary according to the command and can contain a subcode (for composite commands).
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SECTION 11 Host Link Commands This section explains the methods and procedures for using host link commands, which can be used for host link communications via the C200HS ports. 11-1 Communications Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 11-2 Command and Response Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2-1 Commands from the Host Computer . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section 11-1 Communications Procedure 11-1 Communications Procedure Command Chart The commands listed in the chart below can be used for host link communications with the C200HS. These commands are all sent from the host computer to the PC.
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Section 11-1 Communications Procedure Host link communications are executed by means an exchange of commands and responses between the host computer and the PC. With the C200HS, there are two communications methods that can be used. One is the normal method, in which commands are issued from the host computer to the PC. The other method allows commands to be issued from the PC to the host computer.
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Command and Response Formats Section 11-2 When commands are issued to the host computer, the data is transmitted in one direction from the PC to the host computer. If a response to a command is required use a host link communications command to write the response from the host computer to the PC. 11-2 Command and Response Formats This section explains the formats for the commands and responses that are exchanged in host link communications.
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Command and Response Formats Long Transmissions Section 11-2 The largest block of data that can be transmitted as a single frame is 131 characters. A command or response of 132 characters or more must therefore be divided into more than one frame before transmission. When a transmission is split, the ends of the first and intermediate frames are marked by a delimiter instead of a terminator. As each frame is transmitted, the receiving node waits for the delimiter to be transmitted.
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Command and Response Formats Section 11-2 time a frame is received and checking the result against the FCS that is included in the frame makes it possible to check for data errors in the frame. @ 1 0 Node no. R R 0 0 Header code 0 Text 1 4 2 FCS : ↵ Terminator FCS calculation range ASCII code Example Program for FCS @ 40 1 31 0 30 R 52 1 Calculation result 31 0011 0100 ↓ 4 0000 0001 0000 0010 0001 0010 ↓ Converted to hexadecimal. 2 Handled as ASCII characters.
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Host Link Commands Section 11-3 Reception Format When TXD(––) is executed, the data stored in the words beginning with the first send word is converted to ASCII and output to the host computer as a host link command in the format shown below. The “@” symbol, node number, header code, FCS, and delimiter are all added automatically when the transmission is sent. At the host computer, it is necessary to prepare in advance a program for interpreting and processing this format. @ E Node no.
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Host Link Commands Section 11-3 Response Format @ x 101 x 100 Node no. R L Header code x 161 x 160 x 163 x 162 x 161 x 160 End code Read data (1 word) : FCS ↵ Terminator Read data (for number of words read) Parameters Read Data (Response) The contents of the number of words specified by the command are returned in hexadecimal as a response. The words are returned in order, starting with the specified beginning word.
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Host Link Commands Section 11-3 cimal as a response. The PVs are returned in order, starting with the specified beginning timer/counter. 11-3-5 TC STATUS READ –– RG Reads the status of the Completion Flags of the specified number of timers/ counters, starting from the specified timer/counter. Command Format @ x 101 x 100 R Node no. G Header code x 103 x 102 x 101 x 100 x 103 x 102 x 101 x 100 Beginning timer/counter (0000 to 0511) No.
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Host Link Commands Section 11-3 11-3-7 AR AREA READ –– RJ Reads the contents of the specified number of AR words, starting from the specified word. Command Format @ x 101 x 100 Node no. R J Header code x 103 x 102 x 101 x 100 x 103 x 102 x 101 x 100 Beginning word (0000 to 0027) No. of words (0001 to 0028) : FCS ↵ Terminator Response Format @ x 101 x 100 Node no.
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Host Link Commands Section 11-3 11-3-9 LR AREA WRITE –– WL Writes data to the LR area, starting from the specified word. Writing is done word by word. Command Format @ x 101 x 100 Node no. W L Header code x 103 x 102 x 101 x 100 x 163 x 162 x 161 x 160 Beginning word (0000 to 0063) : Write data (1 word) FCS ↵ Terminator Write data (for number of words to write ) Response Format @ x 101 x 100 Node no.
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Host Link Commands Section 11-3 11-3-11 PV WRITE –– WC Writes the PVs (present values) of timers/counters starting from the specified timer/counter. Command Format @ x 101 x 100 Node no. W x 103 x 102 x 101 x 100 x 163 x 162 x 161 x 160 C Header code Beginning timer/counter (0000 to 0511) ↵ : Write data (1 timer/counter) Terminator FCS Write data (for no. of PV to write) Response Format @ x 101 x 100 Node no.
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Host Link Commands Section 11-3 Note If data is specified for writing which exceeds the allowable range, an error will be generated and the writing operation will not be executed. If, for example, 510 is specified as the beginning word for writing, and three words of data are specified, then 512 will become the last word for writing data, and the command will not be executed because TC 512 is beyond area boundary. 11-3-13 DM AREA WRITE –– WD Writes data to the DM area, starting from the specified word.
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Host Link Commands Section 11-3 Parameters Write Data (Command) Specify in order the contents of the number of words to be written to the AR area in hexadecimal, starting with the specified beginning word. Note If data is specified for writing which exceeds the allowable range, an error will be generated and the writing operation will not be executed.
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Host Link Commands Section 11-3 11-3-16 SV READ 2 –– R$ Reads the constant SV or the word address where the SV is stored. The SV that is read is a 4-digit decimal number (BCD) written as the second operand for the TIM, TIMH(15), CNT, CNTR(12), or TTIM(87) instruction at the specified program address in the user’s program. This can only be done with a program of less than 10K. Command Format @ x 101 x 100 Node no.
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Host Link Commands Section 11-3 11-3-17 SV READ 3 –– R% Reads the constant SV or the word address where the SV is stored. The SV that is read is a 4-digit decimal number (BCD) written in the second word of the TIM, TIMH(15), CNT, CNTR(12), or TTIM(87) instruction at the specified program address in the user’s program. With this command, program addresses can be specified for a program of 10K or more. Command Format @ x 101 x 100 Node no.
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Host Link Commands Section 11-3 11-3-18 SV CHANGE 1 –– W# Searches for the first instance of the specified TIM, TIMH(15), CNT, CNTR(12), or TTIM(87) instruction in the user’s program and changes the SV to new constant SV specified in the second word of the instruction. The program is searched from the beginning, and it may therefore take approximately 10 seconds to produce a response. Command Format x 101 x 100 @ Node no.
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Host Link Commands Section 11-3 Parameters Name, TC Number (Command) In “Name”, specify the name of the instruction, in four characters, for changing the SV. In “TC number”, specify the timer/counter number used for the instruction.
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Host Link Commands Section 11-3 Parameters Name, TC Number (Command) In “Name”, specify the name of the instruction, in four characters, for changing the SV. In “TC number”, specify the timer/counter number used for the instruction.
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Host Link Commands Section 11-3 Parameters Status Data, Message (Response) “Status data” consists of four digits (two bytes) hexadecimal. The leftmost byte indicates CPU operation mode, and the rightmost byte indicates the size of the program area.
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Host Link Commands Section 11-3 Parameters Mode Data (Command) “Mode data” consists of two digits (one byte) hexadecimal. With the leftmost two bits, specify the PC operating mode. Set all of the remaining bits to “0”. x 161 x 160 Bit 7 6 5 4 3 2 0 0 0 0 0 0 1 0 Bit Operation mode 1 0 0 0 PROGRAM mode 1 0 MONITOR mode 1 1 RUN mode This area is different from that of STATUS READ. 11-3-23 ERROR READ –– MF Reads and clears errors in the PC.
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Host Link Commands Section 11-3 Error Information (Response) The error information comes in two words.
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Host Link Commands Section 11-3 Parameters Name, Word address, Bit (Command) In “Name”, specify the area (i.e., IR, SR, LR, HR, AR, or TC) that is to be forced set. Specify the name in four characters. In “Word address”, specify the address of the word, and in “Bit” the number of the bit that is to be forced set.
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Host Link Commands Section 11-3 Note 1. The area specified under “Name” must be in four characters. Fill any gaps with spaces to make a total of four characters. 2. Words 253 to 255 cannot be set when the CIO Area is specified. 11-3-26 MULTIPLE FORCED SET/RESET –– FK Force sets, force resets, or cancels the status of the bits in one word in the IR, SR, LR, HR, AR, or TC area. Command Format @ x 101 x 100 Node no.
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Host Link Commands Section 11-3 Forced set/reset/cancel Data (Command) A separate hexadecimal digit is used to specify the desired process for each bit in the specified word, bits 00 to bit 5. The bits that are merely set or reset may change status the next time the program is executed, but bits that are force-set or force-reset will maintain the forced status until it is cleared.
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Host Link Commands Parameters Section 11-3 Model Code “Model code” indicates the PC model in two digits hexadecimal. Model code Model 01 C250 02 C500 03 C120 0E C2000 10 C1000H 11 C2000H/CQM1 12 C20H/C28H/C40H/C200H/C200HS 20 CV500 21 CV1000 22 CV2000 40 CVM1-CPU01-E 41 CVM1-CPU11-E 11-3-29 TEST–– TS Returns, unaltered, one block of data transmitted from the host computer. Command Format @ x 101 x 100 Node no. T 122 characters max.
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Host Link Commands Parameters Section 11-3 Program (Response) The program is read from the entire program area. Note To stop this operation in progress, execute the ABORT (XZ) command. 11-3-31 PROGRAM WRITE –– WP Writes to the PC user’s program area the machine language (object code) program transmitted from the host computer. The contents are written as a block, from the beginning. Command Format @ x 101 x 100 W Node no.
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Host Link Commands Section 11-3 Command Format @ x 101 x 100 Node no. Q Q Header code M R OP1 OP2 OP3 OP4 x 103 x 102 x 101 x 100 OP1 OP2 Sub-header code Read area Read word address Data format , Data break Single read information Total read information (128 max.) , OP1 OP2 OP3 OP4 x 103 x 102 x 101 x 100 OP1 OP2 Data break Read area Read word address Data format ↵ : FCS Terminator Single read information Total read information (128 max.
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Host Link Commands Section 11-3 Data Break (Command) The read information is specified one item at a time separated by a break code (,). The maximum number of items that can be specified is 128. (When the PV of a timer/counter is specified, however, the status of the Completion Flag is also returned, and must therefore be counted as two items.) Batch Reading The bit, word, and timer/counter status is read as a batch according to the read information that was registered with QQ.
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Host Link Commands Section 11-3 11-3-35 INITIALIZE –– :: Initializes the transmission control procedure of all the PCs connected to the host computer. The INITIALIZE command does not use node numbers or FCS, and does not receive a response. Command Format @ : : ↵ 11-3-36 Undefined Command –– IC This response is returned if the header code of a command cannot be decoded. Check the header code. Response Format @ x 101 x 100 Node no.
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Host Link Errors Section 11-4 11-4 Host Link Errors These error codes are received as the response code (end code) when a command received by the C200HS from a host computer cannot be processed. The error code format is as shown below. @ X X Node no. X X Header code X X End code X X FCS : ↵ Terminator The header code will vary according to the command and can contain a subcode (for composite commands).
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Appendix A Standard Models C200HS Racks Name Backplane ((same for all Racks)) CPU Rack CPU Specifications 10 slots 8 slots 5 slots 3 slots C200H-BC101-V2 C200H-BC081-V2 C200H-BC051-V2 C200H-BC031-V2 100 to 120/200 to 240 VAC w/built-in ––– power supply Conforms to EC directives (see note) C200HS-CPU01-E 24 VDC w/built-in power supply Memory Cassette Expansion I/O Racks R k I/O Power Supply y U i Unit I/O Connecting g C bl (max.
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Appendix A Standard Models C200H Standard I/O Units Name Input Units Specifications AC Input Unit DC Input Unit AC/DC Input Unit Interrupt Input Output Units Unit1 Relay Output Unit Triac Output Unit Transistor Output U i Unit Analog Timer Unit Variable Resistor Connector Standard B7A Interface Units Model number 8 pts 100 to 120 VAC C200H-IA121 16 pts 100 to 120 VAC C200H-IA122/122V 8 pts 200 to 240 VAC C200H-IA221 16 pts 200 to 240 VAC C200H-IA222/222V 8 pts No-voltage contact; N
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Appendix A Standard Models C200H Group-2 High-density I/O Units Name DC Input Unit Transistor Output Unit Specifications 32 pts. 24 VDC 64 pts. 24 VDC 32 pts. 16 mA 4.5 VDC to 100 mA 26.4 VDC 0.5 A (5A/Unit) 24 VDC 16 mA 4.5 VDC to 100 mA 26.4 VDC 64 pts. Model number C200H-ID216 C200H-ID218 C200H-ID217 C200H-ID219 C200H-OD218 C200H-OD21B C200H-OD219 C200H Group-2 B7A Interface Units Name Group-2 B7A Interface Units Specifications Connects to B7A Link T Terminals.
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Appendix A Standard Models Name Heat/Cool Temperature Control Unit Thermocouple Pt resistance thermometer PID Control Unit Position Control Unit Specifications Transistor output Model number C200H-TV001 Voltage output Current output Transistor output C200H-TV002 C200H-TV003 C200H-TV101 Voltage output C200H-TV102 Current output Transistor output Voltage output Current output 1 axis Pulse output; speeds: 1 to 99,990 pps 1 axis Directly connectable to servomotor driver; compatible with line driver;
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Appendix A Standard Models SYSMAC LINK Unit/SYSMAC NET Link Unit The SYSMAC LINK Units and SYSMAC NET Link Unit can only be used with the C200HS-CPU31-E and C200HSCPU33-E CPUs. Name SYSMAC LINK Unit Specifications Model number Wired via coaxial cable. Bus Connection Unit required separately. One C1000H-CE001 F Adapter included. C200HS-SLK22 C200HS-SLK12 Terminator Wired via optical fiber cable. Bus Connection Unit required separately.
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Appendix A Standard Models Mounting Rails and Accessories Name Specifications Model number DIN Track Mounting Bracket 1 set (2 included) C200H-DIN01 DIN Track Length: 50 cm; height: 7.3 mm PFP-50N Length: 1 m; height: 7.
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Appendix A Standard Models Name Specifications Model number All Plastic Optical Fiber Cable Set 1-m cable with an Optical Connector A connected to each end 3G5A2-PF101 Optical Fiber Processing Kit 3G2A9-TL101 Accessory: 125-mm nipper (Muromoto Tekko’s 550M) for APF H-PCF Name Optical Fiber Cable SYSMAC BUS BUS, SYSMAC WAY Specifications 10 m, black Two-core cable S3200-HCCB101 50 m, black S3200-HCCB501 100 m, black S3200-HCCB102 500 m, black S3200-HCCB502 1000 m, black S3200-HCCB103 10
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Appendix A Standard Models Optical Power Tester Name Specifications Optical Power Tester (see note) (provided with a connector adapter, light source unit, small single-head plug, hard case, and AC adapter) Head Unit SYSMAC BUS: C200H-RM001-PV1 C200H-RT001/RT002-P C500-RM001-(P)V1 C500-RT001/RT002-(P)V1 S3200-CAT2822 (provided with the Tester) Model number S3200-CAT2820 Note: There is no difference between the light source unit and connector adapter for the Head Unit and those for the Optical Power T
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Appendix A Standard Models An Optical Fiber Cable Bracket must be used to support an optical fiber cable connected to the C200HS-SNT32 SYSMAC NET Link Unit or C200HS-SLK12 SYSMAC LINK Unit. User optical fiber cables with both tension members and power supply lines. The following half-lock connector is used and connects to the C200HS SYSMAC LINK and SYSMAC NET Link Units: S3200-COCF2511.
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Appendix B Programming Instructions A PC instruction is input either by pressing the corresponding Programming Console key(s) (e.g., LD, AND, OR, NOT) or by using function codes. To input an instruction with its function code, press FUN, the function code, and then WRITE. Refer to the pages listed programming and instruction details.
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Appendix B Programming Instructions Code Mnemonic Name 13 DIFU DIFFERENTIATE UP 14 DIFD 15 TIMH DIFFERENTIATE DOWN HIGH-SPEED TIMER (@)16 WSFT WORD SHIFT 17 to 19 For expansion instructions.
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Appendix B Programming Instructions Code Mnemonic Name Function Page (@)52 MLB BINARY MULTIPLY Multiplies two four-digit hexadecimal values and outputs result to specified result words. 224 (@)53 DVB BINARY DIVIDE Divides four-digit hexadecimal dividend by four-digit hexa- 224 decimal divisor and outputs result to specified result words. (@)54 ADDL DOUBLE BCD ADD Adds two eight-digit values (2 words each) and content of CY, and outputs result to specified result words.
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Appendix B Programming Instructions Code Mnemonic Name (@)86 ASC ASCII CONVERT 87 to 89 For expansion instructions. (@)90 SEND (@)91 SBS 92 SBN 93 RET (@)94 WDT (@)97 IORF WATCHDOG TIMER REFRESH I/O REFRESH (@)98 RECV (@)99 MCRO Function Page Converts hexadecimal values from the source word to eight-bit ASCII code starting at leftmost or rightmost half of starting destination word.
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Appendix B Programming Instructions Code Mnemonic Name Function Page 89 (@)INT INTERRUPT CONTROL Performs interrupt control, such as masking and unmasking the interrupt bits for I/O interrupts. 262 --- 7SEG 7-SEGMENT DISPLAY OUTPUT Converts 4- or 8-digit BCD data to 7-segment display format and then outputs the converted data. 301 --- (@)ADBL DOUBLE BINARY ADD Adds two 8-digit binary values (normal or signed data) and outputs the result to R and R+1.
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Appendix B Programming Instructions Code Mnemonic Name Function Page --- (@)XDMR EXPANSION DM READ The contents of the designated number of words of the fixed expansion DM data are read and output to the destination word on the PC side. 290 --- ZCPL DOUBLE AREA RANGE COMPARE Compares an 8-digit value to a range defined by lower and upper limits and outputs the result to the GR, EQ, and LE flags.
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Appendix C Error and Arithmetic Flag Operation The following table shows the instructions that affect the ER, CY, GR, LE and EQ flags. In general, ER indicates that operand data is not within requirements. CY indicates arithmetic or data shift results. GT indicates that a compared value is larger than some standard, LT that it is smaller, and EQ, that it is the same. EQ also indicates a result of zero for arithmetic operations. Refer to Section 5 Instruction Set for details.
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Appendix C Error and Arithmetic Flag Operation Instructions MLB(52) 25503 (ER) 25504 (CY) Unaffected DVB(53) 25505 (GR) Unaffected Unaffected ADDL(54) 25506 (EQ) 25507 (LE) Page 224 Unaffected Unaffected Unaffected 224 Unaffected Unaffected 206 Unaffected Unaffected SUBL(55) 209 MULL(56) Unaffected 212 DIVL(57) 213 BINL(58) 181 BCDL(59) 182 XFER(70) Unaffected Unaffected ROOT(72) Unaffected Unaffected XCHG(73) Unaffected Unaffected Unaffected Unaffected BSET(71) 1
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Appendix C Error and Arithmetic Flag Operation Instructions 25503 (ER) 25504 (CY) FPD(––) 25505 (GR) 25506 (EQ) 25507 (LE) Page Unaffected Unaffected Unaffected 285 HEX(––) Unaffected Unaffected Unaffected Unaffected 195 HMS(66) Unaffected Unaffected Unaffected 184 INT(89) Unaffected Unaffected Unaffected 262 LINE(63) Unaffected Unaffected Unaffected 200 LMSG(47) Unaffected Unaffected Unaffected 279 MAX(––) Unaffected Unaffected Unaffected 233 Unaffected Unaffecte
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Appendix C Error and Arithmetic Flag Operation Instructions END(01) SR 25404 (OF ) OFF SR 25405 (UF) OFF Page 138 ADB(50) 219 SBB(51) 221 ADBL(––) 225 SBBL(––) NEG(––) NEGL(––) 227 Unaffected 202 203 These instructions also affect the ER, CY, and EQ Flags. Refer to the previous tables in this appendix for details.
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Appendix D Memory Areas Overview The following table shows the data areas in PC memory. Area Size Range Comments I/O Area 480 bits IR 000 to IR 029 Group-2 High-density I/O Unit Area 320 bits IR 030 to IR 049 Can be used as ordinary I/O or, if not used for real I/O, can be used as work bits. SYSMAC BUS Area 800 bits IR 050 to IR 099 Can be used as work bits if not used for real I/O.
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Appendix D Memory Areas SR Area Word(s) 236 Bit(s) 00 to 07 08 to 15 00 to 07 Function Node loop status output area for operating level 0 of SYSMAC NET Link System Node loop status output area for operating level 1 of SYSMAC NET Link System Completion code output area for operating level 0 following execution of SEND(90)/RECV(98) SYSMAC LINK/SYSMAC NET Link System 08 to 15 Completion code output area for operating level 1 following execution of SEND(90)/RECV(98) SYSMAC LINK/SYSMAC NET Link System 238
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Appendix D Memory Areas Word(s) 254 255 256 to 261 262 263 Bit(s) 00 01 02 and 03 04 05 06 07 08 09 10 11 12 13 14 15 00 01 02 03 04 05 06 07 08 to 15 00 to 15 00 to 15 00 to 15 Function 1-minute clock pulse bit 0.02-second clock pulse bit Reserved for function expansion. Do not use.
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Appendix D Memory Areas Word(s) 267 268 269 270 Bit(s) 00 to 04 05 06 to 12 13 14 and 15 00 to 15 00 to 07 08 to 10 Function Reserved by system (not accessible by user) Host Link Level 0 Send Ready Flag Reserved by system (not accessible by user) Host Link Level 1 Send Ready Flag Reserved by system (not accessible by user) Reserved by system (not accessible by user) Memory Cassette Contents 00: Nothing; 01: UM; 02: IOM (03: HIS) Memory Cassette Capacity 0: 0 KW (no cassette); 3: 16 KW 11 to 13 14 15 0
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Appendix D Memory Areas Word(s) 273 Bit(s) 00 01 02 to 11 12 13 14 274 275 276 277 to 279 280 to 289 290 to 293 294 to 297 298 to 299 Function Save IOM to Cassette Bit Data transferred to Memory Cassette when Bit is turned ON in PROGRAM mode. Bit will automatically turn OFF. An error will be produced if turned ON in any other Load IOM from Cassette Bit mode.
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Appendix D Memory Areas AR Area Word(s) 00 01 Bit(s) Function 00 to 09 Error Flags for Special I/O Units 0 to 9 (also function as Error Flags for PC Link Units) 10 Error Flag for operating level 1 of SYSMAC LINK or SYSMAC NET Link System 11 Error Flag for operating level 0 of SYSMAC LINK or SYSMAC NET Link System 12 Host Computer to Rack-mounting Host Link Unit Level 1 Error Flag 13 Host Computer to Rack-mounting Host Link Unit Level 0 Error Flag 14 Remote I/O Master Unit 1 Error Flag 15
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Appendix D Memory Areas Word(s) Bit(s) Function 23 00 to 15 Power Off Counter (BCD) 24 00 to 04 Reserved by system. 05 Cycle Time Flag 06 SYSMAC LINK System Network Parameter Flag for operating level 1 07 SYSMAC LINK System Network Parameter Flag for operating level 0 08 SYSMAC/SYSMAC NET Link Unit Level 1 Mounted Flag 09 SYSMAC/SYSMAC NET Link Unit Level 0 Mounted Flag 10 11 and 12 13 Reserved by system.
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Appendix E PC Setup Word(s) Bit(s) Function Default Startup Processing (DM 6600 to DM 6614) The following settings are effective after transfer to the PC only after the PC is restarted. DM 6600 DM 6601 DM 6602 00 to 07 Startup mode (effective when bits 08 to 15 are set to 02).
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Appendix E PC Setup Word(s) Bit(s) Function Default Interrupt/Refresh Processing (DM 6620 to DM 6622) The following settings are effective after transfer to the PC the next time operation is started.
PAGE 468
Appendix E PC Setup Word(s) DM 6648 DM 6649 Bit(s) 00 to 07 Function Default Node number (Host link) 00 to 31 (BCD) 0 08 to 11 Start code enable (RS-232C) 0: Disable; 1: Set Disabled 12 to 15 End code enable (RS-232C) 0: Disable (number of bytes received) 1: Set (specified end code) 2: CR, LF Start code (RS-232C) 00 to FF (binary) Disabled 00 to 07 08 to 15 Not used 12 to 15 of DM 6648 set to 0: Number of bytes received 00: Default setting (256 bytes) 01 to FF: 1 to 255 bytes 12 to 15 of DM
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Appendix E PC Setup Word(s) DM 6654 Bit(s) 00 to 07 08 to 15 Function Start code (RS-232C) 00 to FF (binary) Default 0000 12 to 15 of DM 6653 set to 0: Number of bytes received 00: Default setting (256 bytes) 01 to FF: 1 to 255 bytes 12 to 15 of DM 6653 set to 1: End code (RS-232C) 00 to FF (binary) Error Settings (DM 6655) The following settings are effective after transfer to the PC.
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Appendix F Word Assignment Recording Sheets This appendix contains sheets that can be copied by the programmer to record I/O bit allocations and terminal assignments, as well as details of work bits, data storage areas, timers, and counters.
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I/O Bits Programmer: Word: Bit Program: Unit: Field device Date: Word: Notes Bit 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 10 10 11 11 12 12 13 13 14 14 15 15 Word: Bit Unit: Field device Bit 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 10 10 11 11 12 12 13 13 14 14 15 15 466 Field device Word: Notes Page: Unit: Notes Unit: Field device Notes
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Work Bits Programmer: Program: Area: Bit Word: Usage Date: Notes Bit 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 10 10 11 11 12 12 13 13 14 14 15 15 Area: Bit Word: Usage Page: Area: Word: Usage Area: Notes Bit 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 10 10 11 11 12 12 13 13 14 14 15 15 Notes Word: Usage Notes 467
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Data Storage Programmer: Word 468 Program: Contents Notes Date: Word Page: Contents Notes
PAGE 474
Timers and Counters Programmer: TC address Program: T or C Set value Notes Date: TC address T or C Page: Set value Notes 469
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Appendix G Program Coding Sheet The following page can be copied for use in coding ladder diagram programs. It is designed for flexibility, allowing the user to input all required addresses and instructions. When coding programs, be sure to specify all function codes for instructions and data areas (or # for constant) for operands. These will be necessary when inputting programs though a Programming Console or other Peripheral Device.
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Program Coding Sheet Programmer: Address 472 Instruction Program: Operand(s) Address Date: Instruction Operand(s) Page: Address Instruction Operand(s)
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Appendix H Data Conversion Tables Normal Data Decimal BCD Hex Binary 00 00000000 00 00000000 01 00000001 01 00000001 02 00000010 02 00000010 03 00000011 03 00000011 04 00000100 04 00000100 05 00000101 05 00000101 06 00000110 06 00000110 07 00000111 07 00000111 08 00001000 08 00001000 09 00001001 09 00001001 10 00010000 0A 00001010 11 00010001 0B 00001011 12 00010010 0C 00001100 13 00010011 0D 00001101 14 00010100 0E 00001110 15 00010101 0F 0
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Appendix H Data Conversion Tables Signed Binary Data Decimal 2147483647 2147483646 . . . 32768 32767 32766 . . . 5 4 3 2 1 0 –1 –2 –3 –4 –5 . . . –32767 –32768 –32769 . . . –2147483647 –2147483648 474 16-bit Hex ––– ––– . . . ––– 7FFF 7FFE . . . 0005 0004 0003 0002 0001 0000 FFFF FFFE FFFD FFFC FFFB . . . 8001 8000 ––– . . . ––– ––– 32-bit Hex 7FFFFFFF 7FFFFFFE . . . 00008000 00007FFF 00007FFE . . . 00000005 00000004 00000003 00000002 00000001 00000000 FFFFFFFF FFFFFFFE FFFFFFFD FFFFFFFC FFFFFFFB . . .
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Appendix I Extended ASCII Programming Console Displays Bits 0 to 3 BIN Bits 4 to 7 0000 HEX 0001 0010 0011 2 0100 3 0101 4 0110 5 0111 1010 7 A 0 1 0000 0 NUL DLE Space 0 @ P ‘ 6 p 0001 1 SOH DC1 ! 1 A Q a q 0010 2 STX DC2 ” 2 B R b r 0011 3 ETX DC3 # 3 C S c 0100 4 EOT DC4 $ 4 D T d 0101 5 ENQ NAK % 5 E U 0110 6 ACK SYN & 6 F 0111 7 BEL ETB ’ 7 G 1000 8 BS CAN ( 8 1001 9 HT EM ) 9 1010 A LF SUB * 1011
PAGE 480
Glossary address The location in memory where data is stored. For data areas, an address consists of a two-letter data area designation and a number that designates the word and/or bit location. For the UM area, an address designates the instruction location (UM area). In the FM area, the address designates the block location, etc. allocation The process by which the PC assigns certain bits or words in memory for various functions. This includes pairing I/O bits to I/O points on Units.
PAGE 481
Glossary bit designator An operand that is used to designate the bit or bits of a word to be used by an instruction. bit number A number that indicates the location of a bit within a word. Bit 00 is the rightmost (least-significant) bit; bit 15 is the leftmost (most-significant) bit. buffer A temporary storage space for data in a computerized device. building-block PC A PC that is constructed from individual components, or “building blocks”.
PAGE 482
Glossary through a TC bit and used to count the number of times the status of a bit or an execution condition has changed from OFF to ON. CPU An acronym for central processing unit. In a PC System, the CPU executes the program, processes I/O signals, communicates with external devices, etc. CPU Backplane A Backplane which is used to create a CPU Rack. CPU Rack Part of a building-block PC, the CPU Rack contains the CPU, a power supply, and other Units.
PAGE 483
Glossary differentiated instruction An instruction that is executed only once each time its execution condition goes from OFF to ON. Nondifferentiated instructions are executed each cycle as long as the execution condition stays ON. differentiation instruction An instruction used to ensure that the operand bit is never turned ON for more than one cycle after the execution condition goes either from OFF to ON for a Differentiate Up instruction or from ON to OFF for a Differentiate Down instruction.
PAGE 484
Glossary extended timer A timer created in a program by using two or more timers in succession. Such a timer is capable of timing longer than any of the standard timers provided by the individual instructions. Factory Intelligent Terminal A programming device provided with advanced programming and debugging capabilities to facilitate PC operation. The Factory Intelligent Terminal also provides various interfaces for external devices, such as floppy disk drives.
PAGE 485
Glossary initialization error An error that occurs either in hardware or software during the PC System startup, i.e., during initialization. initialize Part of the startup process whereby some memory areas are cleared, system setup is checked, and default values are set. input The signal coming from an external device into the PC. The term input is often used abstractly or collectively to refer to incoming signals. input bit A bit in the IR area that is allocated to hold the status of an input.
PAGE 486
Glossary I/O Control Unit A Unit mounted to the CPU Rack in certain PCs to monitor and control I/O points on Expansion I/O Units. I/O devices The devices to which terminals on I/O Units, Special I/O Units, or Intelligent I/O Units are connected. I/O devices may be either part of the Control System, if they function to help control other devices, or they may be part of the controlled system.
PAGE 487
Glossary Ladder Support Software A software package that provides most of the functions of the Factory Intelligent Terminal on an IBM AT, IBM XT, or compatible computer. LAN An acronym for local area network. leftmost (bit/word) The highest numbered bits of a group of bits, generally of an entire word, or the highest numbered words of a group of words. These bits/words are often called most-significant bits/words.
PAGE 488
Glossary main program All of a program except for the subroutines. masking ‘Covering’ an interrupt signal so that the interrupt is not effective until the mask is removed. Master Short for Remote I/O Master Unit. memory area Any of the areas in the PC used to hold data or programs. mnemonic code A form of a ladder-diagram program that consists of a sequential list of the instructions without using a ladder diagram.
PAGE 489
Glossary NOT A logic operation which inverts the status of the operand. For example, AND NOT indicates an AND operation with the opposite of the actual status of the operand bit. NSB An acronym for Network Service Board. NSU An acronym for Network Service Unit. OFF The status of an input or output when a signal is said not to be present. The OFF state is generally represented by a low voltage or by non-conductivity, but can be defined as the opposite of either.
PAGE 490
Glossary output point The point at which an output leaves the PC System. Output points correspond physically to terminals or connector pins. output signal A signal being sent to an external device. Generally an output signal is said to exist when, for example, a connection point goes from low to high voltage or from a nonconductive to a conductive state. overseeing Part of the processing performed by the CPU that includes general tasks required to operate the PC.
PAGE 491
Glossary grammable Controllers are used to automate control of external devices. Although single-component Programmable Controllers are available, building-block Programmable Controllers are constructed from separate components. Such building-block Programmable Controllers are formed only when enough of these separate components are assembled to form a functional assembly, i.e., no one individual Unit is called a PC.
PAGE 492
Glossary Remote I/O Unit Any of the Units in a Remote I/O System. Remote I/O Units include Masters, Slaves, Optical I/O Units, I/O Link Units, and Remote Terminals. remote I/O word An I/O word allocated to a Unit in a Remote I/O System. reset The process of turning a bit or signal OFF or of changing the present value of a timer or counter to its set value or to zero.
PAGE 493
Glossary slot A position on a Rack (Backplane) to which a Unit can be mounted. software error An error that originates in a software program. software protect A means of protecting data from being changed that uses software as opposed to a physical switch or other hardware setting. source The location from which data is taken for use in an instruction, as opposed to the location to which the result of an instruction is to be written. The latter is called the destination.
PAGE 494
Glossary timer A location in memory accessed through a TC bit and used to time down from the timer’s set value. Timers are turned ON and reset according to their execution conditions. TM area A memory area used to store the results of a trace. transmission distance The distance that a signal can be transmitted. TR area A data area used to store execution conditions so that they can be reloaded later for use with other instructions.
PAGE 495
Glossary served for work words. Parts of other areas not required for special purposes may also be used as work words, e.g., LR words not used in a PC Link or Net Link System.
PAGE 496
Revision History A manual revision code appears as a suffix to the catalog number on the front cover of the manual. Cat. No. W235-E1-05 Revision code The following table outlines the changes made to the manual during each revision. Page numbers refer to the previous version. Revision code Date 1 January 1994 2 August 1994 Revised content Original production Host Link Commands have been added as Section 10. Page 5: Available manuals table undated. Page 16: Paragraph and table added at top of page.
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Revision History Revision code Date Revised content 2A April 1995 The following instructions have been corrected: ASFT(––) to ASFT(17), XFRB(––) to XFRB(62), MCMP(––) to MCMP(19), CMPL(––) to CMPL(60), BCMP(––) to BCMP(68), ZCP(––) to ZCP(88), SEC(––) to SEC(65), HMS(––) to HMS(66), LINE(––) to LINE(63), COLM(––) to COLM(64), APR(––) to APR(69), INT(––) to INT(89), SCAN(––) to SCAN(18), LMSG(––) to LMSG(47), TERM(––) to TERM(48), MPRF(––) to MPRF(61), and BCNT(––) to BCNT(67).
PAGE 498
Revision History Revision code Date Revised content 2B July 1995 2C August 1996 The Precautions section was added after About this Manual. Page 88: Special I/O Unit type “N” corrected from Host Link Unit to Position Control Unit. Page 110: Ladder diagram corrected for the self-maintaining bit example. Page 158: ASFT(17) example changed. Page 191: “Content of the source words is zero” corrected to “Content of a source word is zero” for the ER Flags. Page 226: DVB(53) example changed.
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Index A address tracing. See tracing, data tracing.
PAGE 500
Index converting between hex and ASCII: sec7 354 I/O Unit designations: 4–1 to 4–6 88 Programming Console, English/Japanese switch: 4–1 to 4–6 80 DM area, allocating UM to expansion DM: sec7 366 E ER.
PAGE 501
Index WC: sec11 412 WD: sec11 413 WG: sec11 412 WH: sec11 411 WJ: sec11 413 WL: sec11 411 WP: sec11 427 WR: sec11 410 XZ: sec11 429 host link errors: sec11 431 Host Link Systems, error bits and flags: sec3 40 HR area: sec3 60 I I/O bit definition: sec3 31 limits: sec3 31 I/O numbers: sec3 33 I/O points, refreshing: 5–24 on 284 , 285 I/O response time, one-to-one link communications: 6–4 on 339 I/O response times: 6–4 on 333 I/O status, maintaining: sec3 42 I/O table clearing: 4–1 to 4–6 89 reading: 4–1 to
PAGE 502
Index OR: 4–1 to 4–6 69 ; 5–1 to 5–14 129 combining with AND: 4−1 to 4−6 69 OR LD: 4–1 to 4–6 72 ; 5–1 to 5–14 130 combining with AND LD: 4−1 to 4−6 73 use in logic blocks: 4−1 to 4−6 73 OR NOT: 4–1 to 4–6 69 ; 5–1 to 5–14 129 ORW(35): 5–20 to 5–23 251 OUT: 4–1 to 4–6 70 ; 5–1 to 5–14 130 OUT NOT: 4–1 to 4–6 70 ; 5–1 to 5–14 130 PID(––): 5–20 to 5–23 242 RECV(98): 5–24 on 296 RET(93): 5–20 to 5–23 259 ROL(27): 5–15 to 5–17 155 ROOT(72): 5–18 to 5–19 217 ROR(28): 5–15 to 5–17 155 RSET: 5–1 to 5–14 133 RXD(
PAGE 503
Index memory areas: appD 453 clearing: 4–1 to 4–6 82 definition: sec3 25 Memory Cassette, installing: sec2 21 Memory Cassettes transferring C200H programs: sec1 11 UM Area/IOM data: sec9 386 memory clear: 4–1 to 4–6 84 memory partial clear: 4–1 to 4–6 83 messages, programming: 5–24 on 281 , 282 mnemonic code, converting: 4–1 to 4–6 66–78 models, C200HS: appA 433 modifying data, hex/binary: sec7 352 monitoring binary: sec7 359 differentiation monitoring: sec7 357 monitoring 3 words: sec7 358 mounting Units,
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Index Special I/O Units. See Units SR area: sec3 33–48 stack operation COLL(81): 5–15 to 5–17 164 DIST(80): 5–15 to 5–17 162 STARTUP MODE, PC Setup: sec3 59 STARTUP SETTINGS, PC Setup: sec3 59 status indicators. See CPU indicators step execution, Step flag: sec3 44 step instructions: 5–24 on 269–278 subroutine number: 5–20 to 5–23 259 subroutines: 5–20 to 5–23 253–265 SV accessing via TC area: sec3 60 changing: sec7 362 CNTR(12): 5–1 to 5–14 149 timers and counters: 5–1 to 5–14 139 switches, DIP.