Data Sheet

74VHC112 Dual J-K Flip-Flops with Preset and Clear
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC112 Rev. 1.2 2
Connection Diagram
Pin Description
Truth Table
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Clock Transition
Q
0
(Q
0
) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced
input or output one setup time prior to the HIGH-to-LOW
clock transition.
Logic Diagram
(One Half Shown)
Pin Names Description
J
1
, J
2
, K
1
, K
2
Data Inputs
CLK
1
, CLK
2
Clock Pulse Inputs (Active Falling
Edge)
CLR
1
, CLR
2
Direct Clear Inputs (Active LOW)
PR
1
, PR
2
Direct Preset Inputs (Active LOW)
Q
1
, Q
2
, Q
1
, Q
2
Outputs
Inputs Outputs
PR CLR CP JK Q Q
LHXXXHL
HLXXXLH
LLXXXHH
HH hhQ
0
Q
0
HH lhLH
HH hlHL
HH llQ
0
Q
0