Data Sheet

74VHC112 Dual J-K Flip-Flops with Preset and Clear
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC112 Rev. 1.2 5
AC Electrical Characteristics
Note:
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
I
CC
(opr.) = C
PD
• V
CC
• f
IN
+ I
CC
/ 4 (per F/F), and the total C
PD
when n pcs of the Flip-Flop operate can be calculated
by the following equation: C
PD
(total) = 30 + 14 • n
AC Operating Requirements
Note:
3. V
CC
is 3.3 ± 0.3V or 5.0 ± 0.5V.
Symbol Parameter V
CC
(V) Conditions
T
A
= 25°C
T
A
= –40°C
to +85°C
UnitsMin. Typ. Max. Min. Max.
f
MAX
Maximum Clock
Frequency
3.3 ± 0.3 C
L
= 15pF 110 150 100 MHz
C
L
= 50pF 90 120 80
5.0 ± 0.5 C
L
= 15pF 150 200 135 MHz
C
L
= 50pF 120 185 110
t
PLH
, t
PHL
Propagation Delay Time
(CP to Q
n
or Q
n
)
3.3 ± 0.3 C
L
= 15pF 8.5 11.0 1.0 13.4 ns
C
L
= 50pF 10.0 15.0 1.0 16.5
5.0 ± 0.5 C
L
= 15pF 5.1 7.3 1.0 8.8 ns
C
L
= 50pF 6.3 10.5 1.0 12.0
t
PLH
, t
PHL
Propagation Delay Time
(PR or CLR to Q
n
or Q
n
)
3.3 ± 0.3 C
L
= 15pF 6.7 10.2 1.0 11.7 ns
C
L
= 50pF 9.7 13.5 1.0 15.0
5.0 ± 0.5 C
L
= 15pF 4.6 6.7 1.0 8.0 ns
C
L
= 50pF 6.4 9.5 1.0 11.0
C
IN
Input Capacitance V
CC
= Open 4 10 10 pF
C
PD
Power Dissipation
Capacitance
(2)
18 pF
Symbol Parameter V
CC
(V)
(3)
T
A
= 25°C T
A
= –40°C to +85°C
Units Typ. Guaranteed Minimum
t
W
Minimum Pulse Width
(CP or CLR or PR)
3.3 5.0 5.0 ns
5.0 5.0 5.0
t
S
Minimum Setup Time
(J
n
or K
n
to CP
n
)
3.3 5.0 5.0 ns
5.0 4.0 4.0
t
H
Minimum Hold Time
(J
n
or K
n
to CP
n
)
3.3 1.0 1.0 ns
5.0 1.0 1.0
t
REC
Minimum Recovery Time
(CLR or PR to CP)
3.3 6.0 6.0 ns
5.0 5.0 5.0