Data Sheet

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October-2017, Rev. 2 FAN3229T-F085/D

FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers

FAN3226 / FAN3227 / FAN3228 / FAN3229

Dual 2-A High-Speed, Low-Side Gate Drivers

Features

 Industry-Standard Pinouts

 4.5-V to 18-V Operating Range

 3-A Peak Sink/Source at V

= 12 V

 2.4 A-Sink / 1.6-A Source at V

OUT

= 6 V

 Choice of TTL or CMOS Input Thresholds

 Four Versions of Dual Independent Drivers:

- Dual Inverting + Enable (FAN3226)

- Dual Non-Inverting + Enable (FAN3227)

- Dual Inputs in Tw o Pin-Out Configurations:

o Compatible w ith FAN3225x (FAN3228)

o Compatible w ith TPS2814D (FAN3229)

 Internal Resistors Turn Driver Off If No Inputs

 MillerDrive™ Technology

 12-ns / 9-ns Typical Rise/Fall Times (1-nF Load)

 Under 20-ns Typical Propagation Delay Matched

w ithin 1 ns to the Other Channel

 Double Current Capability by Paralleling Channels

 8-Lead 3x3 mm MLP or 8-Lead SOIC Package

 Rated from –40°C to +125°C Ambient

 Automotive Qualified to AEC-Q100 (F085 Version)

Applications



Sw itch-Mode Pow er Supplies

 High-Efficiency MOSFET Sw itching

 Synchronous Rectifier Circuits

 DC-to-DC Conv erters

 Motor Control

 Servers

 Automotive-Qualified Systems (F085 version)

Description

The FA N3226-29 family of dual 2 A gate drivers is

designed to drive N-channel enhancement-mode

MOSFETs in low -side sw itching applications by

providing high peak current pulses during the short

sw itching intervals. The driver is available w ith either

TTL or CMOS input thresholds. Internal circuitry

provides an under-voltage lockout function by holding

the output low until the supply voltage is w ithin the

operating range. In addition, the drivers feature matched

internal propagation delays betw een A and B channels

for applications requiring dual gate drives w ith critical

timing, such as synchronous rectifiers. This enables

connecting tw o drivers in parallel to effectively double

the current capability driving a single MOSFET.

The FA N322X drivers incorporate MillerDrive™

architecture for the final output stage. This bipolar-

MOSFET combination provides high current during the

Miller plateau stage of the MOSFET turn-on / turn-off

process to minimize sw itching loss, w hile providing rail-

to-rail voltage sw ing and reverse current capability.

The FAN3226 offers two inverting drivers and the

FAN3227 offers tw o non-inverting drivers. Each device

has dual independent enable pins that default to ON if

not connected. In the FAN3228 and FAN3229, each

channel has dual inputs of opposite polarity, w hich

allows configuration as non-inverting or inverting w ith an

optional enable function using the second input. If one

or both inputs are left unconnected, internal resistors

bias the inputs such that the output is pulled low to hold

the pow er MOSFET off.

Related Resources

http://w w w.onsemi.com/pub/Collateral/AN-6069.pdf.pdf

ENA

INA

GND

ENB

VDD

INB

OUTA

OUTB

ENB

VDD

OUTA

OUTB

ENA

INA

GND

INB

INA+

VDD

OUTA

OUTB

INB+

GND

INB

INA

GND

VDD

OUTA

OUTB

INB+

INB

INA

INA+

FAN3226

FAN3227

FAN3228

FAN3229

Figure 1. Pin Configurations

Summary of content (26 pages)

PAGE 1
Features       Description Industry-Standard Pinouts The FA N3226-29 family of dual 2 A gate dr ivers is designed to drive N-channel enhancement- mode MOSFETs in low -side sw itching applications by providing high peak current pulses dur ing the short sw itching intervals. The driver is available w ith either TTL or CMOS input thresholds. Internal circuitry provides an under-voltage lockout function by holding the output low until the supply voltage is w ithin the operating range.
PAGE 2
Package Packing Method Quantity per Reel 3x3 mm MLP-8 Tape & Reel 3,000 SOIC-8 Tape & Reel 2,500 SOIC-8 Tape & Reel 2,500 3x3 mm MLP-8 Tape & Reel 3,000 SOIC-8 Tape & Reel 2,500 FAN3226TMX-F085 SOIC-8 Tape & Reel 2,500 FAN3227CMPX 3x3 mm MLP-8 Tape & Reel 3,000 SOIC-8 Tape & Reel 2,500 SOIC-8 Tape & Reel 2,500 3x3 mm MLP-8 Tape & Reel 3,000 SOIC-8 Tape & Reel 2,500 SOIC-8 Tape & Reel 2,500 CMOS SOIC-8 Tape & Reel 2,500 TTL SOIC-8 Tape & Reel 2,500 3x3 mm MLP-
PAGE 3
1 8 2 7 3 6 4 5 Figure 2. 3x3 m m MLP-8 (Top View ) 1 8 2 7 3 6 4 5 Figure 3. SOIC-8 (Top View ) Thermal Characteristics(2) ΘJL(3) ΘJT(4) ΘJA(5) Ψ JB(6) Ψ JT(7) Unit 8-Lead 3x3 mm Molded Leadless Package (MLP) 1.6 68 43 3.5 0.8 °C/W 8-Pin Small Outline Integrated Circuit (SOIC) 40 31 89 43 3.0 °C/W Package Notes: 2. Estimates derived from thermal simulation; actual values depend on the application. 3.
PAGE 4
1 INA 2 GND 3 INB A B 4 8 ENB 7 OUTA 6 VDD 5 ENA 1 INA 2 GND 3 OUTB INB 4 FAN3226 A B 8 ENB INA- 1 7 OUTA INB+ 2 6 VDD GND 3 OUTB 5 INB- 4 FAN3227 + A + B - 8 INA+ INA+ 7 OUTA INA- 2 6 VDD INB+ 5 INB- OUTB FAN3228 1 + A - 3 + B - 4 8 GND 7 OUTA 6 VDD 5 OUTB FAN3229 Figure 4. Pin Configurations (Repeated) Pin Definitions Name Pin Description ENA Enable Input for Channel A. Pull pin LOW to inhibit driver A.
PAGE 5
VDD VDD 100kΩ 100kΩ ENA 1 8 ENB VDD 100kΩ INA 2 7 OUTA 100kΩ GND 3 UVLO 6 VDD VDD_OK VDD 100kΩ INB 5 4 OUTB 100kΩ Figure 5. FAN3226 Block Diagram VDD VDD 100kΩ 100kΩ ENA 1 8 ENB INA 2 7 OUTA 100kΩ 100kΩ UVLO GND 3 6 VDD VDD_OK INB 4 5 OUTB 100kΩ 100kΩ Figure 6. FAN3227 Block Diagram www.onsemi.
PAGE 6
VDD INA+ 8 100kΩ INA- 1 100kΩ 7 OUTA 6 VDD 5 OUTB 8 GND 7 OUTA 6 VDD 5 OUTB 100kΩ VDD_OK GND 3 UVLO VDD INB+ 2 100kΩ INB- 4 100kΩ 100kΩ Figure 7. FAN3228 Block Diagram VDD INA+ 1 100kΩ INA- 2 100kΩ 100kΩ VDD_OK UVLO VDD INB+ 3 100kΩ INB- 4 100kΩ 100kΩ Figure 8. FAN3229 Block Diagram www.onsemi.
PAGE 7
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit -0.3 20.0 V V DD VDD to PGND V EN ENA and ENB to GND GND - 0.3 V DD + 0.
PAGE 8
Unless otherw ise noted, V DD=12 V, TJ =-40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit 4.5 18.0 V 0.75 1.20 mA Supply V DD Operating Range IDD Supply Current Inputs / EN Not Connected TTL 0.65 1.05 mA V ON Turn-On Voltage INA=ENA=V DD, INB=ENB=0 V 3.5 3.9 4.3 V V OFF Turn-Off Voltage INA=ENA=V DD, INB=ENB=0 V 3.3 3.7 4.
PAGE 9
(Continued) Unless otherw ise noted, V DD=12 V, TJ =-40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max.
PAGE 10
90% 90% Output Output 10% Input 10% VINH Input VINL tD1 VINL tD2 tD2 tD1 t FALL t RISE tRISE tFALL Figure 9. Non-Inverting (EN HIGH or Floating) Figure 10. Inverting (EN HIGH or Floating) HIGH HIGH Input Input LOW LOW 90% 90% Output Output 10% 10% Enable VINH VENH Enable VENL tD3 VENL tD3 tD4 t RISE VENH t FALL Figure 11. Non-Inverting (IN HIGH) tD4 t RISE Figure 12. Inverting (IN LOW) www.onsemi.
PAGE 11
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted. 1.6 1.6 1.2 1.2 1.0 1.0 0.8 0.6 0.4 0.8 0.6 0.4 Inputs and Enables Floating, Outputs 0.2 TTL Input 1.4 FAN3226C, 27C IDD (mA) IDD (mA) 1.4 Inputs and Enables Floating, Outputs Low 0.2 0.0 0.0 4 6 8 10 12 14 16 18 4 6 Supply Voltage (V) 8 10 12 14 16 18 Supply Voltage (V) Figure 13. IDD (Static) vs. Supply Voltage (15) Figure 14. IDD (Static) vs. Supply Voltage (15) 1.
PAGE 12
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted. Figure 18. IDD (1 nF Load) vs. Frequency Figure 19. IDD (1 nF Load) vs. Frequency 1.6 1.4 1.2 1.0 1.0 IDD (mA) 1.2 0.8 0.6 Inputs and Enables Floating, Outputs 0.4 0.2 0.0 -50 -25 0 25 50 75 Tem perature (°C) 100 Figure 20. IDD (Static) vs. Tem perature TTL Input 0.8 0.6 Inputs and Enables Floating, Outputs 0.4 0.2 125 (15) 0.0 -50 -25 0 25 50 75 Tem perature (°C) 1.4 FAN3228C, 29C 1.2 1.0 0.8 0.
PAGE 13
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted. Figure 23. Input Thresholds vs. Supply Voltage Figure 24. Input Thresholds vs. Supply Voltage Figure 25. Input Threshold % vs. Supply Voltage Figure 26. Input Thresholds vs. Tem perature Figure 27. Input Thresholds vs. Tem perature www.onsemi.
PAGE 14
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted. Figure 28. UVLO Thresholds vs. Tem perature Figure 29. UVLO Threshold vs. Tem perature Figure 30. Propagation Delays vs. Supply Voltage Figure 31. Propagation Delays vs. Supply Voltage Figure 32. Propagation Delays vs. Supply Voltage Figure 33. Propagation Delays vs. Supply Voltage www.onsemi.
PAGE 15
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted. Figure 34. Propagation Delays vs. Tem perature Figure 35. Propagation Delays vs. Tem perature Figure 36. Propagation Delays vs. Tem perature Figure 37. Propagation Delays vs. Tem perature Figure 38. Fall Tim e vs. Supply Voltage Figure 39. Rise Tim e vs. Supply Voltage www.onsemi.
PAGE 16
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted. Figure 40. Rise and Fall Tim es vs. Tem perature Figure 41. Rise/Fall Waveform s w ith 1 nF Load Figure 42. Rise/Fall Waveform s w ith 10 nF Load Figure 43. Quasi-Static Source Current w ith V DD=12 V Figure 44. Quasi-Static Sink Current w ith V DD=12 V www.onsemi.
PAGE 17
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted. Figure 45. Quasi-Static Source Current w ith V DD=8 V Figure 46. Quasi-Static Sink Current w ith V DD=8 V Note: 15. For any inverting inputs pulled low , non-inverting inputs pulled high, or outputs driven high, static IDD increases by the current flow ing through the corresponding pull-up/dow n resistor show n in the block diagram. Test Circuit VDD 120µF Al. El. 4.
PAGE 18
Input Thresholds MillerDrive™ Gate Drive Technology Each member of the FA N322x driver family consists of tw o identical channels that may be used independently at rated current or connected in parallel to double the individual current capacity. In the FA N3226 and FA N3227, channels A and B can be enabled or disabled independently using ENA or ENB, respectively. The EN pin has TTL thresholds for parts w ith either CMOS or TTL input thresholds.
PAGE 19
To enable this IC to turn a device on quickly, a local highfrequency bypass capacitor CBYP w ith low ESR and ESL should be connected betw een the VDD and GND pins with minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10 µF to 47 µF commonly found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the r ipple voltage on the V DD supply to ≤5%.
PAGE 20
Operational Waveforms The FAN3228/FA N3229 truth table indicates the operational states using the dual- input configuration. In a non-inverting driver configuration, the IN- pin should be a logic low signal. If the IN- pin is connected to logic high, a disable function is realized, and the driver output remains low regardless of the state of the IN+ pin. At pow er-up, the driver output remains low until the V DD voltage reaches the turn-on threshold.
PAGE 21
Gate dr ivers used to sw itch MOSFETs and IGBTs at high frequencies can dissipate s ignificant amounts of pow er. It is important to deter mine the driver pow er dissipation and the resulting junction temperature in the application to ensure that the part is operating w ithin acceptable temperature limits.
PAGE 22
VIN VIN VOUT FAN3227 1 8 PWMA 2 7 GND 3 6 PWMB 4 5 PWM Timing/ Isolation 1 8 2 7 3 6 4 5 Vbias OUTA VDD OUTB FAN3227 Figure 55. Forw ard Converter w ith Synchronous Rectification Figure 56. Prim ary-Side Dual Driver in a Push-Pull Converter VIN FAN3227 ENB 8 1 ENA PWM-A 2 A 3 GND PWM-B 4 7 VDD 6 B 5 Vbias FAN3227 PWM-C 2 Phase Shift Controller PWM-D ENB 8 1 ENA A 3 GND 4 7 VDD 6 B Vbias 5 Figure 57.
PAGE 23
Type Part Num ber (16) Gate Drive (Sink/Src) Input Threshold Logic Package Single 1 A FAN3111C +1.1 A / -0.9 A CMOS Single Channel of Dual-Input/Single-Output Single 1 A FAN3111E External (17) Single Non-Inverting Channel with External Reference SOT23-5, MLP6 Single 2 A FAN3100C +2.5 A / -1.8 A CMOS Single Channel of Two-Input/One-Output SOT23-5, MLP6 Single 2 A FAN3100T +2.5 A / -1.8 A TTL Single Channel of Two-Input/One-Output SOT23-5, MLP6 Single 2 A FAN3180 +2.4 A / -1.
PAGE 24
2X 2X 0.8 MAX RECOMMENDED LAND PATTERN 0.05 0.00 SEATING PLANE A. CONFORMS TO JEDEC REGISTRATION MO-229, VARIATION VEEC, DATED 11/2001 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. FILENAME: MKT-MLP08Drev2 Figure 58. 3x3 m m , 8-Lead Molded Leadless Package (MLP) Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in any manner without notice.
PAGE 25
(Continued) 5.00 4.80 A 0.65 3.81 5 8 B 6.20 5.80 PIN ONE INDICATOR 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M 1.27 C B A LAND PATTERN RECOMMENDATION SEE DETAIL A 0.25 0.10 1.75 MAX R0.10 0.10 0.51 0.33 0.50 x 45° 0.25 C OPTION A - BEVEL EDGE GAGE PLANE R0.10 8° 0° 0.90 0.406 0.25 0.19 C OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED SEATING PLANE (1.
PAGE 26
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