Data Sheet

ManualsBrandsON SEMICONDUCTOR ManualsPMICsPMIC - gate drivers Inverting High side SOIC 8

Publication Order Number:

FAN7085M-GF085/D

onductor Components Industries, LLC.

September-2017,Rev.2

FAN7085-GF085 High Side Gate Driver with Recharge FET

FAN7085-GF085

High Side Gate Driver with Recharge FET

Features

• Qualified to AEC Q100

• Floating channel designed for bootstrap operation fully oper-

ational up to 300V.

• Tolerance to negative transient voltage on VS pin

• dv/dt immune.

• Gate drive supply range from 4.5V to 20V

• Under-voltage lockout

• CMOS Schmitt-triggered inputs with pull-down and pull-up

• High side output out of phase with input (Inverted input)

• Reset input

• Internal recharge FET for bootstrap refresh

Typical Applications

• Diesel and gasoline injectors/valves

• MOSFET-and IGBT high side driver applications



Description

The FAN7085-GF085 is a high-side gate drive IC with reset

input and built-in recharge FET. It is designed for high voltage

and high speed driving of MOSFET or IGBT, which operates up

to 300V. ON Semiconductor's high-voltage process and

common-mode noise cancellation technique provide stable

operation in the high side driver under high-dV/dt noise

circumstances. Logic input is compatible with standard CMOS

outputs. The UVLO cir-cuits prevent from malfunction when

VCC and VBS are lower than the specified threshold voltage. It

is available with space saving SOIC-8 Package. Minimum

source and sink current capability of output driver is 250mA

and 250mA. Built-in recharge FET to refresh bootstrap circuit is

very useful for circuit topology requiring switches on low and

high side of load.

SOIC-8

Ordering Information

Device Package

Operating

Temp.

FAN7085M-GF085 SOIC-8 -40 C ~ 125 C

FAN7085MX-GF085 SO

IC-8 -40 C ~ 125 C

X : Tape & Reel type

Summary of content (13 pages)

PAGE 1
High Side Gate Driver with Recharge FET Features Description • Qualified to AEC Q100 The FAN7085-GF085 is a high-side gate drive IC with reset input and built-in recharge FET. It is designed for high voltage and high speed driving of MOSFET or IGBT, which operates up to 300V. ON Semiconductor's high-voltage process and common-mode noise cancellation technique provide stable operation in the high side driver under high-dV/dt noise circumstances. Logic input is compatible with standard CMOS outputs.
PAGE 2
VB Under Voltage Reset VB to VS Pulse Filter Flip Flop Brake before make HO Under Voltage Reset VCC to GND RESET- VS Level Shifter ON Logic Pulse Filter IN- Delay Level Shifter OFF GND Pin Assignments 1 2 3 4 VCC VB IN HO GND NC RESET VS 8 7 6 5 Pin Definitions Pin Number Pin Name I/O Pin Function Description 1 VCC P Driver supply voltage, typically 5V 2 IN- I Driver control signal input (Negative Logic) 3 GND P Ground 4 RESET- I Driver enable input signal (Negative L
PAGE 3
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to GND. Parameter Symbol Min. Max. Unit High side floating supply voltage VBS -0.3 25 V High side driver output stage voltage VB -5 325 V Vs -25 300 V High side floating output voltage VHO VS-0.3 VB+0.3 V Supply voltage VCC -0.3 25 V VIN -0.3 Vcc+0.3 V VRES -0.3 Vcc+0.3 V Neg. transient: 0.
PAGE 4
Unless otherwise specified, -40°C <= Ta <= 125°C, VCC = 5V, VBS = 7V, VS = 0V, VRESET = 5V, RL = 50, CL = 2.5nF. Parameter Symbol Conditions Min. Typ. Max. Unit VCC and VBS supply under voltage positive going threshold VCCUV+ VBSUV+ Vcc and VBS rising from 0V - 3.7 4.3 V VCC and VBS supply under voltage negative going threshold VCCUVVBSUV- Vcc and VBS dropping from 5V 2.8 3.4 - V VCC and VBS under voltage hysteresis VCCUVH VBSUVH - 0.02 0.3 - V tduvcc tduvbs VCC: 6.5V->2.
PAGE 5
Unless otherwise specified, -40°C <= Ta <= 125°C, VCC = 5V, VBS = 7V, VS = 0V, VRESET = 5V, RL = 50, CL = 2.5nF. Parameter Symbol Conditions Input-to-output turn-on propagation delay tplh 50% input level to 10% output level, VS = 0V Input-to-output turn-off propagation delay tphl 50% input level to 90% output level VS = 0V RESET-to-output turn-off propagation delay tphl_res RESET-to-output turn-on propagation delay tplh_res tr1 Output rising time Min. Typ. Max. Unit 0.56 1 us - 0.15 0.
PAGE 6
1. Logic Tables VCC VBS RESET- IN- Ho RechFET < VCCUVLOX X X X OFF ON X LOW X OFF ON X X X HIGH OFF ON > VCCUVLO+ > VBSUVLO+ HIGH LOW ON OFF > VCCUVLO+ < VBSUVLO- HIGH LOW OFF OFF Notes: X means independent from signal IN-=LOW indicates that the high side NMOS is ON IN-=HIGH indicates that the high side NMOS is OFF RechFET =ON indicates that the recharge MOSFET is ON RechFET =OFF indicates that the recharge MOSFET is OFF www.onsemi.
PAGE 7
FAN7085-GF085 High Side Gate Driver with Recharge FET Typical Application Circuit 1. Typical Application Circuit Up to 300V D1 VCC VCC VB IN- HO GND NC RESET- VS R1 C3 R2 C2 Load C1 2. Application Example From Charge Pump Voltage Source D5 5V C2 VCC VB IN- HO GND NC RESET- VS R1 S1 C3 R2 C1 Load D3 R3 From LS Driver C4 S2 D4 R4 GND www.onsemi.
PAGE 8
1. Input/Output Timing Diagrams IN- RESET- 90% 90% VS 10% 10% tr VHO tf tphl Recharge tplh Toff_rech Ton_rech Figure.1 Input and Output Timing Diagram and Switching Time Waveform Definition 2. Reset Timing Diagrams IN- RESET- VHO tplh_res tphl_res Figure.2 Reset and Output Timing Diagram www.onsemi.
PAGE 9
Ig INIg RESET- 7V VCC VB IN- HO GND NC RESET- VS 50R VB drop VB-VS 1u 2n5 Brake before make Figure3.b VB Drop Voltage Test Circuit Figure3.a VB Drop Voltage Diagram 4.Recommendation Min. Short Pulse Width Bat2 Bat1 1 2 3 4 VCC VB RESET HO IN N.C COM VS 8 7 6 Tpulse =560nS 0.1uF IN 5 60% FAN7085 Figure 4a.Short Pulse Width Test Circuit and Pulse Width Waveform 142KHz Less than 430nS Pulse Width IN HO Abnormal Output Figure 4b.
PAGE 10
This performance graphs based on ambient temperature -40C ~125C 2.6 3.2 VBS=7V, RL=50, CL=2.5nF VBS=7V, RL=50, CL=2.5nF 2.4 2.8 Vinth- (V) Vinth+ (V) 3.0 2.6 2.2 2.0 2.4 Typ. Typ. 2.2 4.4 4.7 5.0 5.3 5.6 5.9 6.2 1.8 4.4 6.5 4.7 5.0 Figure 5a. Positive IN and RESET Threshold vs VCC Supply 1600 Output Source Cureent (mA) Output Sink Cureent (mA) 5.9 6.2 6.5 500 VCC=5V o -40 C 1200 o 125 C 800 400 5 10 15 VCC=5V, VBS=7V Typ.
PAGE 11
RES-to-Output Turn-off Propagation Delay (ns) RES-to-Output Turn-on Propagation Delay (ns) VCC=5V, VBS=7V, RL=50, CL=2.5nF 650 600 550 Typ. 500 -50 0 50 100 150 250 VCC=5V, VBS=7V, RL=50, CL=2.5nF 200 150 Typ. 100 -50 0 Figure 8a. RES to Output Turn-On Propagation Delay vs Temperature 50 Logic "1" RES Input Current (uA) Logic "0" Input Current (uA) VCC=5V, RL=50, CL=2.5nF 40 Typ. 30 20 10 0 -50 0 50 100 VCC=5V, RL=50, CL=2.5nF 40 30 Typ.
PAGE 12
5.0 4.5 Max. VCC Supply Voltage(V) VCC Supply Voltage(V) 4.5 4.0 Typ. 3.5 Min. 3.0 2.5 2.0 -50 0 50 100 4.0 3.5 Max. Typ. 3.0 Min. 2.5 2.0 -50 150 0 50 o VCC=5v, VBS=7, VRL=50, CL=2.5nF Typ. 6 0 50 100 Figure 12b. VCC Under Voltage Threshold(-) vs Temperature Recharge Gate Turn-off Propagation Delay (ns) Recharge Transistor Turn-on Propagation Delay (us) 10 4 -50 300 VBS=7V VCC=5v, VBS=7V, RL=50, CL=2.5nF 260 220 180 Typ.
PAGE 13
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.