Data Sheet
FDC8878 N-Channel PowerTrench
®
MOSFET
©2012 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com
FDC8878 Rev.1.4
Electrical Characteristics T
J
= 25 °C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Min Typ Max Units
BV
DSS
Drain to Source Breakdown Voltage I
D
= 250 μA, V
GS
= 0 V 30 V
ΔBV
DSS
ΔT
J
Breakdown Voltage Temperature
Coefficient
I
D
= 250 μA, referenced to 25 °C 13 mV/°C
I
DSS
Zero Gate Voltage Drain Current V
DS
= 24 V, V
GS
= 0 V 1 μA
I
GSS
Gate to Source Leakage Current, Forward V
GS
= 20 V, V
DS
= 0 V 100 nA
V
GS(th)
Gate to Source Threshold Voltage V
GS
= V
DS
, I
D
= 250 μA 1.2 1.6 3.0 V
ΔV
GS(th)
ΔT
J
Gate to Source Threshold Voltage
Temperature Coefficient
I
D
= 250 μA, referenced to 25 °C -5 mV/°C
r
DS(on)
Static Drain to Source On Resistance
V
GS
= 10 V, I
D
= 8.0 A 12 16
mΩV
GS
= 4.5 V, I
D
= 7.5 A 14 18
V
GS
= 10 V, I
D
= 8.0 A, T
J
= 125 °C 16 21
g
FS
Forward Transconductance V
DD
= 5 V, I
D
= 8.0 A 43 S
C
iss
Input Capacitance
V
DS
= 15 V, V
GS
= 0 V,
f = 1 MHz
782 1040 pF
C
oss
Output Capacitance 318 425 pF
C
rss
Reverse Transfer Capacitance 40 60 pF
R
g
Gate Resistance 1.2 Ω
t
d(on)
Turn-On Delay Time
V
DD
= 15 V, I
D
= 8 A,
V
GS
= 10 V, R
GEN
= 6 Ω
612ns
t
r
Rise Time 210ns
t
d(off)
Turn-Off Delay Time 17 30 ns
t
f
Fall Time 210ns
Q
g(TOT)
Total Gate Charge V
GS
= 0 V to 10 V
V
DD
= 15 V
I
D
= 8 A
13 18 nC
Total Gate Charge V
GS
= 0 V to 4.5 V 6 9 nC
Q
gs
Total Gate Charge 1.7 nC
Q
gd
Gate to Drain “Miller” Charge 2.0 nC
V
SD
Source to Drain Diode Forward Voltage V
GS
= 0 V, I
S
= 8.0 A (Note 2) 0.8 1.2 V
t
rr
Reverse Recovery Time
I
F
= 8.0 A, di/dt = 100 A/μs
22 35 ns
Q
rr
Reverse Recovery Charge 7 14 nC
a. 78 °C/W when mounted on
a 1 in
2
pad of 2 oz copper
b.175 °C/W when mounted on
a minimum pad of 2 oz copper
NOTES:
1. R
θJA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R
θJC
is guaranteed by design while R
θCA
is determined by the user's board design.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
G
DF
DS
SF
SS
G
DF
DS
SF
SS