Data Sheet

ManualsBrandsON SEMICONDUCTOR ManualsFETsMOSFET 1 N-channel , P-channel

FDG8842CZ Complementary PowerTrench

MOSFET

onductor Components Industries, LLC.

October-2017, Rev.2

Public

ation Order Number:

FDG8842CZ/D

FDG8842CZ

Complementary PowerTrench

MOSFET

Q1:30V,0.75A,0.4Ω; Q2:–25V,–0.41A,1.1Ω

Features

Q1: N-Channel

 Max r

DS(on)

= 0.4Ω at V

= 4.5V, I

= 0.75A

 Max r

DS(on)

= 0.5Ω at V

= 2.7V, I

= 0.67A

Q2: P-Channel

 Max r

DS(on)

= 1.1Ω at V

= –4.5V, I

= –0.41A

 Max r

DS(on)

= 1.5Ω at V

= –2.7V, I

= –0.25A

 Very low level gate drive requirements allowing direct

operation in 3V circuits(V

GS(th)

<1.5V)

 Very small package outline SC70-6

 RoHS Compliant

General Description

These N & P-Channel logic level enhancement mode field

effect transistors are produced using ON Semiconductor’s

proprietary, high cell density, DMOS technology. This very

high density process is especially tailored to minimize

on-state resistance. This device has been designed

especially for low voltage applica-tions as a replacement for

bipolar digital transistors and small signal MOSFETs. Since

bias resistors are not required, this dual digital FET can replace

several different digital transistors, with different bias resistor

values.

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Q1 Q2 Units

Drain to Source Voltage 30 –25 V

Gate to Source Voltage ±12 –8 V

Drain Current -Continuous 0.75 –0.41

-Pulsed

2.2 –1.2

Power Dissipation for Single Operation (Note 1a)

(Note 1b)

0.36

0.30

, T

STG

Operating and Storage Junction Temperature Range –55 to +150 °C

θJA

Thermal Resistance, Junction to Ambient Single operation (Note 1a) 350

°C/W

θJA

Thermal Resistance, Junction to Ambient Single operation (Note 1b) 415

Device Marking Device Reel Size Tape Width Quantity

.42 FDG8842CZ 7” 8mm 3000 units

Pin 1

SC70-6

Summary of content (8 pages)

PAGE 1
Complementary PowerTrench® MOSFET Q1:30V,0.75A,0.4Ω; Q2:–25V,–0.41A,1.1Ω Features General Description Q1: N-Channel These N & P-Channel logic level enhancement mode field Max rDS(on) = 0.4Ω at VGS = 4.5V, ID = 0.75A effect transistors are produced using ON Semiconductor’s Max rDS(on) = 0.5Ω at VGS = 2.7V, ID = 0.67A proprietary, high cell density, DMOS technology. This very high density process is especially Q2: P-Channel on-state resistance.
PAGE 2
Symbol Parameter Test Conditions Type Min 30 –25 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250μA, VGS = 0V ID = –250μA, VGS = 0V Q1 Q2 ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250μA, referenced to 25°C ID = –250μA, referenced to 25°C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 24V, VGS = 0V VDS = –20V, VGS = 0V Q1 Q2 1 –1 μA IGSS Gate to Source Leakage Current VGS = ±12V, VDS= 0V VGS = –8V, VDS= 0V Q1 Q2 ±10 –100 μA nA 1
PAGE 3
Symbol Parameter Test Conditions Type Min Typ Max Units 0.3 –0.3 A 1.2 –1.2 V Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current VSD Source to Drain Diode Forward Voltage VGS = 0V, IS = 0.3A VGS = 0V, IS = –0.3A Q1 Q2 (Note 2) (Note 2) Q1 Q2 0.76 –0.84 Notes: 1.
PAGE 4
2.6 VGS = 4.5V VGS = 2.7V VGS = 2.0V 1.76 ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 2.20 1.32 VGS =1.8V 0.88 PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX 0.44 0.00 0.0 VGS = 1.5V 0.5 1.0 1.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 2.0 VGS = 1.8V 2.2 1.8 VGS = 3.5V 1.4 VGS = 2.7V 1.0 0.6 0.00 0.44 0.88 1.32 1.76 2.20 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 0.8 1.6 rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.6 -50 SOURCE ON-RESISTANCE (Ω) ID =0.
PAGE 5
VGS, GATE TO SOURCE VOLTAGE(V) 5 200 ID = 0.22A Ciss 100 3 VDD = 5V 2 CAPACITANCE (pF) 4 VDD = 10V VDD = 15V Coss 10 1 f = 1MHz VGS = 0V 0 0.0 0.2 0.4 0.6 0.8 1.0 Qg, GATE CHARGE(nC) 1.2 1 0.1 1.4 1 Figure 8. Capacitance vs Drain to Source Voltage 50 4 r DS n) (o ED P(PK), PEAK TRANSIENT POWER (W) 1 T MI LI 100μs 1ms 10ms 0.1 SINGLE PULSE TJ = MAX RATED 100ms RθJA = 415OC/W 0.01 1s DC TA = 25OC 0.005 0.1 1 30 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7.
PAGE 6
5 VGS = -3.5V VGS = -4.5V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE -ID, DRAIN CURRENT (A) 1.2 VGS = -2.7V 0.9 VGS = -2.5V 0.6 VGS = -2.0V PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX 0.3 VGS = -1.5V 0.0 0 1 2 3 4 VGS = -2.0V VGS = -2.7V 2 VGS = -3.5V 1 VGS = -4.5V 0 0.0 0.3 rDS(on), DRAIN TO 1.2 1.0 0.8 -25 0 PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX ID =-0.22A 25 50 75 100 125 SOURCE ON-RESISTANCE (Ω) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.2 4 ID = -0.41A VGS = -4.
PAGE 7
5 200 -VGS, GATE TO SOURCE VOLTAGE(V) ID = -0.41A Ciss 100 VDD = -5V 3 CAPACITANCE (pF) 4 VDD = -10V VDD = -15V 2 Coss 10 Crss 1 f = 1MHz VGS = 0V 0 0.0 0.4 0.8 1.2 1 0.1 1.6 Qg, GATE CHARGE(nC) 20 r DS( ) on IT LIM P(PK), PEAK TRANSIENT POWER (W) -ID, DRAIN CURRENT (A) 3 1 ED 1ms 10ms 0.1 SINGLE PULSE TJ = MAX RATED RθJA = 415oC/W 100ms TA = 25oC 1s DC 1 0.3 50 10 25 10 Figure 20. Capacitance vs Drain to Source Voltage Figure 19. Gate Charge Characteristics 0.
PAGE 8
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.