Data Sheet

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FMS6501A • Rev. 1.0.0 9
FMS6501A — 12x9 Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Applications Information
Input Clamp / Bias Circuitry
The FMS6501A accommodates AC- or DC-coupled
inputs. Internal clamping and bias circuitry are provided
to support AC-coupled inputs. These are selectable
through the CLMP bits via the I
2
C compatible interface.
For DC-coupled inputs, the device should be
programmed to use the bias input configuration. In this
configuration, the input is internally biased to 625 mV
through a 100 k resistor. Distortion is optimized with
the output levels set between 250 mV above ground
and 500 mV below the power supply. These constraints,
along with the desired channel gain, need to be
considered when configuring the input signal levels for
input DC coupling.
With AC-coupled inputs, the FMS6501A uses a simple
clamp rather than a full DC-restore circuit. For video
signals with and without sync (Y, CV, R, G, B); the
lowest voltage at the output pins is clamped to ~300 mV
above ground when the 6dB gain setting is selected.
If symmetric AC-coupled input signals are used
(Chroma, Pb, Pr, Cb, Cr), the bias circuit described
above can be used to center them within the input
common range. The average DC value at the output is
approximately 1.27 V with a 6 dB gain setting. This
value changes, depending upon the selected gain
setting, as shown in Table 5.
Table 5. Common Mode Voltage
Gain Setting Clamp Voltage Bias Voltage
6dB 300 mV 1.27 V
7dB 330 mV 1.43 V
8dB 370 mV 1.60 V
9dB 420 mV 1.80 V
Figure 8 shows the clamp-mode input circuit and the
internally controlled voltage at the input pin for AC-
coupled inputs.
Figure 8. Clamp Mode Input Circuit
Figure 9 shows the bias mode input circuit and internally
controlled voltage at the input pin for AC-coupled inputs.
Figure 9. Bias Mode Input Circuit
Output Configuration
The FMS6501A outputs may be either AC or DC
coupled. Resistive output loads can be as low as 75 ,
representing a dual doubly terminated video load. High
impedance capacitive loads of up to 20 pF can be
driven without loss of signal integrity. For standard 75 
video loads, a 75  matching resistor should be placed
in series to allow for a doubly terminated load. DC-
coupled outputs should be connected as shown in
Figure 10.
Figure 10. DC-Coupled Load Connection
If multiple low-impedance loads are DC coupled,
increased power and thermal issues need to be
addressed. In this case, the use of a multilayer board
with a large ground plane is recommended to help
dissipate heat. If a two-layer board is used under these
conditions, an extended ground plane directly under the
device is recommended. This plane should extend at
least 12.7 mm (0.5 inches) beyond the device. PC board
layout issues are discussed in the Layout
Considerations section.
AC-coupled loads should be configured as in shown in
Figure 11.
Figure 11. AC-Coupled Load Connection
Input
Clamp
75
0.1µF
V
ideo source must
be AC coupled
Lowest voltage
set to 125mV
Input
Bias
75
0.1µF
Video source must
be AC coupled
Lowest voltage
set to 625mV
75
Output
Amplifier
75
75
Output
Amplifier
220µF
75