Data Sheet

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FMS6501A • Rev. 1.0.0 2
FMS6501A — 12x9 Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Pin Configuration
Figure 2. Pin Assignments
Pin Definitions
Pin # Name Type Description
1 IN1 Input Input, channel 1
2 IN2 Input Input, channel 1
3 IN3 Input Input, channel 1
4 IN4 Input Input, channel 1
5 IN5 Input Input, channel 1
6 IN6 Input Input, channel 1
7 VCC Power Core power, must be tied to positve power supply
8 GND Power Core ground, must be tied to ground
9 IN7 Input Input, channel 7
10 IN8 Input Input, channel 8
11 IN9 Input Input, channel 9
12 IN10 Input Input, channel 10
13 IN11 Input Input, channel 11
14 IN12 Input Input, Channel 12
15 ADDR Input Selects I
2
C address; 0=0x06 (0000 0110), 1=0x86 (1000 0110)
16 SCL Input Serial clock for I
2
C port
17 SDA Input Serial data for I
2
C port
18 OUT9 Output Output, channel 9
19 OUT8 Output Output, channel 8
20 OUT7 Output Output, Channel 7
21 GNDO Power Output ground, must be tied to ground
22 VCCO Power Output power, must be tied to positve power supply
23 OUT6 Output Output, channel 6
24 OUT5 Output Output, channel 5
25 OUT4 Output Output, channel 4
26 OUT3 Output Output, channel 3
27 OUT2 Output Output, channel 2
28 OUT1 Output Output, channel 1