Data Sheet

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FMS6501A • Rev. 1.0.0 5
FMS6501A — 12x9 Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Applications Information
Digital Interface
The I
2
C-compatible interface is used to program output
enables, input-to-output routing, input clamp / bias, and
output gain. The I
2
C address is 0x06 (0000 0110) with
the ability to offset it to 0x86 (1000 0110) by tying the
ADDR pin HIGH.
Both data and address data, of eight bits each, are
written to the I
2
C address to access control functions.
There are separate internal addresses for each output.
Each output’s address includes bits to select an input
channel, adjust the output gain, and enable or disable
the output amplifier. More than one output can select
the same input channel for one-to-many routing. When
the outputs are disabled, they are placed in a high-
impedance state. This allows multiple FMS6501A
devices to be paralleled to create a larger switch matrix.
Typical output power-up time is less than 500 ns.
The clamp / bias control bits are written to their own
internal addresses, since they should always remain the
same regardless of signal routing. They are set based
on the input signal connected to the FMS6501A.
All undefined addresses may be written without effect.
Table 1. Output Control Register Contents and Defaults
Control Name Width Type Default Bit(s) Description
Enable 1 Bit Write 0 7 Channel Enable: 1=Enable, 0=Power Down
(6)
Gain 2 Bits Write 0 6:5 Channel Gain: 00=6dB, 01=7dB, 10=8dB, 11=9dB
Inx 5 Bits Write 0 4:0
Input Selected to Drive this Output: 00000=OFF
(7)
,
00001=IN1, 00010=IN2... 01100=IN12
Notes:
6. Power down places the output in a high-impedance state so multiple FMS6501 devices may be paralleled.
Power down also de-selects any input routed to the specified output.
7. When all inputs are OFF, the amplifier input is tied to approximately 150 mV and the output goes to
approximately 300 mV with the 6 dB gain setting.
Table 2. Output Control Register MAP
Register
Name
Register
Address
Bit 7 Bit 6 Bit5
Bit4
(8)
Bit3 Bit2 Bit1 Bit0
OUT1 0x01 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0
OUT2 0x02 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0
OUT3 0x03 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0
OUT4 0x04 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0
OUT5 0x05 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0
OUT6 0x06 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0
OUT7 0x07 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0
OUT8 0x08 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0
OUT9 0x09 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0
Notes:
8. IN4 is provided for forward compatibility and should always be written as 0.
Table 3. Clamp Control Register Contents and Defaults
Control Name Width Type Default Bit(s) Description
CLAMP 1 bit Write 0 7:0 Clamp / Bias selection: 1 = Clamp, 0 = Bias