Data Sheet

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FMS6501A • Rev. 1.0.0 6
FMS6501A — 12x9 Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Table 4. Clamp Control Register Map
Register Name
Register
Address
Bit 7 Bit 6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CLAMP1 0x1D Clmp8 Clmp7 Clmp6 Clmp5 Clmp4 Clmp3 Clmp2 Clmp1
CLAMP2 0x1E Resv’d Resv’d Resv’d Resv’d Clmp12 Clmp11 Clmp10 Clmp9
I
2
C BUS Characteristics
T
A
= 25°C and V
CC
= 5 V unless otherwise noted.
Symbol Parameter Conditions Min. Typ. Max. Unit
V
IL
Digital Input Lo
w
(
9
)
SDA, SCL, ADDR 0 1.5 V
V
IH
Digital Input High
(
9
)
SDA, SCL, ADDR 3.0 V
CC
V
f
scl
Clock Frequency SCK 100 kHz
t
R
Input Rise Time 1.5 V to 3 V 1000 ns
t
F
Input Fall Time 1.5 V to 3 V 300 ns
t
LOW
Clock Low Period 4.7 µs
t
HIGH
Clock High Period 4.0 µs
t
SU,DAT
Data Set-up Time 300 ns
t
HD,DAT
Data Hold Time 0 ns
t
SU,STO
Set-up Time from Clock HIGH to Stop 4 µs
t
BUF
Start Set-up Time Following a Stop 4.7 µs
t
HD,STA
Start Hold Time 4 µs
t
SU,STA
Start Set-up Time Following Clock LOW to HIGH 4.7 µs
Notes:
9. 100% tested at T
A
=25°C.
Figure 3. I
2
C Bus Timing
SDA
SCL
SDA
t
BUF
t
LOW
t
f
t
HD,STA
t
r
t
HD,DAT
t
HIGH
t
SU,DAT
t
SU,STO
t
SU,STA