Data Sheet

ManualsBrandsON SEMICONDUCTOR ManualsLinear ICsLinear IC - Video editing Video switcher TSSOP 28

FMS6501A • Rev. 1.0.0 7

FMS6501A — 12x9 Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers

C Interface

Operation

The I

C-compatible interface conforms to the I

specification for Standard Mode. Individual addresses

may be written. There is no read capability. The

interface consists of two lines. These is a serial data line

(SDA) and a serial clock line (SCL), both of which must

be connected to a positive supply through an external

resistor. Data transfer may be initiated only when the

bus is not busy.

Bit Transfer

One data bit is transferred during each clock pulse. The

data on the SDA line must remain stable during the

HIGH period of the clock pulse. Changes in the line

during this time are interpreted as a control signal.

Figure 4. Bit Transfer

Start and Stop Conditions

The data and clock lines remain HIGH when the bus is

not busy. A HIGH-to-LOW transition of the data line,

while the clock is HIGH, is defined as START condition

(S). A LOW-to-HIGH transition of the data line, while the

clock is HIGH, is defined as STOP condition (P).

Figure 5. Definition of START and STOP conditions

Acknowledge

The number of data bytes transferred between the

START and STOP conditions from transmitter to

receiver is unlimited. Each byte of eight bits is followed

by an acknowledge bit. The acknowledge bit is a high-

level signal put on the bus by the transmitter, during

which the master generates an extra acknowledge-

related clock pulse. A slave receiver must generate an

acknowledge (ACK) after the reception of each byte. A

master receiver must generate an acknowledge after

the reception of each byte that has been clocked out of

the slave transmitter.

The device that acknowledges must pull down the SDA

line during the acknowledge clock pulse so the SDA line

is stable LOW during the HIGH period of the

acknowledge-related clock pulse (set-up and hold times

must be taken into consideration). A master receiver

must signal an end of data to the transmitter by not

generating an acknowledge on the last byte clocked out

of the slave. In this event, the transmitter must leave the

data line HIGH to enable the master to generate a

STOP condition.

Data line

stable;

data valid

SCL

SDA

Change

of data

allowed

START condition

STOP condition

SCL

SDA