Datasheet

ManualsBrandsON SEMICONDUCTOR ManualsLinear ICsLinear IC - Op-amp MC 34072 P ONS Multi-purpose PDIP 8

July, 2014 − Rev. 22

1 Publication Order Number:

MC34071/D

MC34071,2,4,A

MC33071,2,4,A,

NCV33072,4,A

Single Supply 3.0 V to 44 V

Operational Amplifiers

Quality bipolar fabrication with innovative design concepts are

employed for the MC33071/72/74, MC34071/72/74, NCV33072/74A

series of monolithic operational amplifiers. This series of operational

amplifiers offer 4.5 MHz of gain bandwidth product, 13 V/ms slew rate

and fast settling time without the use of JFET device technology.

Although this series can be operated from split supplies, it is

particularly suited for single supply operation, since the common

mode input voltage range includes ground potential (V

). With a

Darlington input stage, this series exhibits high input resistance, low

input offset voltage and high gain. The all NPN output stage,

characterized by no deadband crossover distortion and large output

voltage swing, provides high capacitance drive capability, excellent

phase and gain margins, low open loop high frequency output

impedance and symmetrical source/sink AC frequency response.

The MC33071/72/74, MC34071/72/74, NCV33072/74,A series of

devices are available in standard or prime performance (A Suffix)

grades and are specified over the commercial, industrial/vehicular or

military temperature ranges. The complete series of single, dual and

quad operational amplifiers are available in plastic DIP, SOIC, QFN

and TSSOP surface mount packages.

Features

• Wide Bandwidth: 4.5 MHz

• High Slew Rate: 13 V/ms

• Fast Settling Time: 1.1 ms to 0.1%

• Wide Single Supply Operation: 3.0 V to 44 V

• Wide Input Common Mode Voltage Range: Includes Ground (V

EE)

• Low Input Offset Voltage: 3.0 mV Maximum (A Suffix)

• Large Output Voltage Swing: −14.7 V to +14 V (with ±15 V

Supplies)

• Large Capacitance Drive Capability: 0 pF to 10,000 pF

• Low Total Harmonic Distortion: 0.02%

• Excellent Phase Margin: 60°

• Excellent Gain Margin: 12 dB

• Output Short Circuit Protection

• ESD Diodes/Clamps Provide Input Protection for Dual and Quad

• NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

http://onsemi.com

See detailed ordering and shipping information on page 18 o

this data sheet.

ORDERING INFORMATION

PDIP−8

P SUFFIX

CASE 626

SOIC−8

D SUFFIX

CASE 751

PDIP−14

P SUFFIX

CASE 646

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14

DTB SUFFIX

CASE 948G

See general marking information in the device marking

section on page 21 of this data sheet.

DEVICE MARKING INFORMATION

http://onsemi.com

WQFN10

MT SUFFIX

CASE 510AJ

Summary of content (26 pages)

PAGE 1
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A Single Supply 3.0 V to 44 V Operational Amplifiers http://onsemi.com Quality bipolar fabrication with innovative design concepts are employed for the MC33071/72/74, MC34071/72/74, NCV33072/74A series of monolithic operational amplifiers. This series of operational amplifiers offer 4.5 MHz of gain bandwidth product, 13 V/ms slew rate and fast settling time without the use of JFET device technology.
PAGE 2
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A PIN CONNECTIONS CASE 646/CASE 751A/CASE 948G CASE 626/CASE 751 CASE 510AJ VCC Offset Null 1 2 Inputs + 3 VEE 4 8 NC 7 VCC Output 1 Inputs 1 6 Output 5 Offset Null 1 2 3 VCC (Single, Top View) 1 2 Inputs 1 VEE 3 8 5 7 + + 4 6 VCC Output 2 1 + 4 + 4 Inputs 2 Output 1 14 2 3 10 13 Inputs 4 Output 1 1 9 Output 2 NC 2 8 NC In 1 3 7 In 2 6 In + 2 12 11 + - Output 4 VEE + 10 9 Inputs 3 In + 1 4 5 Output
PAGE 3
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A MAXIMUM RATINGS Rating Symbol Value Unit VS +44 V Input Differential Voltage Range VIDR (Note 1) V Input Voltage Range VIR (Note 1) V Output Short Circuit Duration (Note 2) tSC Indefinite Sec Supply Voltage (from VEE to VCC) Operating Junction Temperature TJ +150 °C Storage Temperature Range Tstg −60 to +150 °C ESDHBM ESDMM 2000 200 ESD Capability, Dual and Quad (Note 3) Human Body Model Machine Model V Stresses exceeding those listed
PAGE 4
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL = connected to ground, unless otherwise noted. See Note 4 for TA = Tlow to Thigh) A Suffix Characteristics Symbol Input Offset Voltage (RS = 100 W, VCM = 0 V, VO = 0 V) VCC = +15 V, VEE = −15 V, TA = +25°C VCC = +5.
PAGE 5
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL = connected to ground. TA = +25°C, unless otherwise noted.) A Suffix Characteristics Symbol Non−Suffix Min Typ Max Min Typ Max 8.0 − 10 13 − − 8.0 − 10 13 − − − − 1.1 2.2 − − − − 1.1 2.2 − − GBW 3.5 4.5 − 3.5 4.5 − MHz BW − 160 − − 160 − kHz − − 60 40 − − − − 60 40 − − − − 12 4.0 − − − − 12 4.0 − − SR Slew Rate (Vin = −10 V to +10 V, RL = 2.
PAGE 6
V IO INPUT OFFSET VOLTAGE (mV) V , 2400 2000 1600 8 & 14 Pin Plastic Pkg SOIC-14 Pkg 1200 800 400 2.0 0 -4.0 0 -55 -40 -20 0 20 40 60 80 100 120 140 160 -55 25 50 75 100 Figure 4. Maximum Power Dissipation versus Temperature for Package Types Figure 5. Input Offset Voltage versus Temperature for Representative Units VCC VCC/VEE = +1.5 V/ -1.5 V to +22 V/ -22 V VCC -1.6 VCC -2.4 VEE +0.01 VEE -55 -25 0 25 50 75 100 125 125 1.3 VCC = +15 V VEE = -15 V VCM = 0 1.2 1.1 1.0 0.9 0.
PAGE 7
VCC/VEE = +4.5 V/ -4.5 V to +22 V/ -22 V Source VCC -1.0 25 125 25 VEE +1.0 85 125 0 5.0 10 15 0.2 0.1 GND 0 100 20 1.0 k 10 k RL, LOAD RESISTANCE TO GROUND (W) Figure 10. Split Supply Output Saturation versus Load Current Figure 11. Single Supply Output Saturation versus Load Resistance to Ground 60 VCC -0.4 -0.8 2.0 VCC = +15 V RL to VCC TA = 25°C 1.0 GND 50 Sink 40 Source 30 20 VCC = +15 V VEE = -15 V RL ≤ 0.1 W DVin = 1.0 V 10 0 100 1.
PAGE 8
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A THD, TOTAL HARMONIC DISTORTION (%) AV = 1000 0.3 VCC = +15 V VEE = -15 V VO = 2.0 Vpp RL = 2.0 k TA = 25°C 0.2 AV = 100 0.1 AV = 10 AV = 1.0 0 100 1.0 k 10 k 108 2.0 AV = 100 1.0 AV = 10 AV = 1.0 0 4.0 20 Figure 17. Total Harmonic Distortion versus Output Voltage Swing 100 VCC = +15 V VEE = -15 V VO= -10 V to +10 V RL = 10 k f ≤ 10Hz 0 80 Gain 60 Phase Margin = 60° 40 0 25 50 75 100 20 1.
PAGE 9
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A 70 VCC = +15 V VEE = -15 V RL = 2.0 k VO = -10 V to +10 V TA = 25°C 80 60 φ m , PHASE MARGIN (DEGREES) 40 20 0 10 100 1.0 k VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k to R VO = -10 V to +10 V TA = 25°C 60 50 40 30 20 10 0 10 k 10 100 Figure 22. Percent Overshoot versus Load Capacitance Figure 23. Phase Margin versus Load Capacitance 14 80 10 8.0 φ m , PHASE MARGIN (DEGREES) VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.
PAGE 10
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A Δ V , O OUTPUT VOLTAGE SWING FROM 0 V (V) 1.1 1.05 1.0 0.95 10 0.9 0 -25 0 25 50 75 100 125 1.0 mV 5.0 Compensated Uncompensated 0 1.0 mV 10 mV 1.0 mV -10 0 0.5 1.0 1.5 3.0 Figure 28. Normalized Slew Rate versus Temperature Figure 29. Output Settling Time VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k CL = 300 pF TA = 25°C 100 VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k CL = 300 pF TA = 25°C 0 Figure 31.
PAGE 11
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A 105 PSR, POWER SUPPLY REJECTION (dB) TA = -55°C 8.0 7.0 TA = 25°C 6.0 TA = 125°C 5.0 Quad device 4.0 VCC = +15 V VEE = -15 V 95 +PSR (DVCC = +1.5 V) 85 +PSR = 20 Log 75 DVCC DVO/ADM ADM DVCC DVO + -PSR = 20 Log DVO/ADM DVEE DVEE 65 0 5.0 10 15 20 25 0 25 50 75 100 Figure 34. Supply Current versus Supply Voltage Figure 35.
PAGE 12
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A Because the PNP output emitter−follower transistor has been eliminated, the MC34071 series offers a 20 mA minimum current sink capability, typically to an output voltage of (VEE +1.8 V). In single supply applications the output can directly source or sink base current from a common emitter NPN transistor for fast high current switching applications.
PAGE 13
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A (Typical Single Supply Applications VCC = 5.0 V) VCC 5.1 M VO 0 3.7 Vpp 0 VCC 20 k 100 k 1.0 M Cin CO + VO 68 k MC34071 36.6 mVpp Cin 100 k Vin 10 k RL - VO CO 10 k RL 100 k AV = 10 BW (-3.0 dB) = 450 kHz BW (-3.0 dB) = 45 kHz Figure 38. AC Coupled Noninverting Amplifier Figure 39. AC Coupled Inverting Amplifier VCC 4.75 Vpp 2.63 V + MC34071 10 k Vin 370 mVpp AV = 101 1.0 k VO 3.7 Vpp 91 k 5.1 k RL 5.1 k 2.
PAGE 14
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A Vin CF 2.0 V RF 5.0 k 5.0 k 5.0 k Vin - VO 10 k + 10 k t 2.0 k RL MC34071 10 k VO + MC34071 VCC 1.0 V VO 0.2 ms Delay 4.0 V Bit Switches 13 V/ms (R-2R) Ladder Network 25 V/ms 0.1 t Delay 1.0 ms Settling Time 1.0 ms (8-Bits, 1/2 LSB) Figure 44. Low Voltage Fast D/A Converter Figure 45.
PAGE 15
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A VO Hysteresis R2 Vref VOH R1 Iout + MC34071 VOL - Vin Vin Vin VinL VinL = R1 (VOL-Vref)+Vref R1+R2 VinH = R1 (VOH-Vref)+Vref R1+R2 VH = R1 (VOH -VOL) R1+R MC34071 - Vref Iout = Figure 50. Low Input Voltage Comparator with Hysteresis R1 + VinH R Figure 51.
PAGE 16
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A GENERAL ADDITIONAL APPLICATIONS INFORMATION VS = ±15.0 V C2 0.02 R1 560 C2 0.05 - R2 5.6 k R3 510 MC34071 C1 1.0 - R2 1.1 k MC34071 C1 0.44 R1 46.1 k C1 1.0 fo = 1.0 kHz Ho = 10 + fo = 100 Hz Ho = 20 + Then: R1 = Choose: fo, Ho, C1 Choose: fo, Ho, C2 Then: C1 = 2C2 (Ho+1) R2 = Ǹ2 R2 R1 = Ho R2 R3 = Ho+1 4pfoC2 R2 = C2 = Figure 56. Second Order Low−Pass Active Filter Ho+0.5 pfoC1 Ǹ2 Ǹ2 2pfoC1 (1/Ho+2) C Ho Figure 57.
PAGE 17
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A + R R MC34074 R VO MC34074 RE + R - R Example: Let: R = RE = 12 k Then: AV = 3.0 BW = 1.5 MHz MC34074 + R AV = 1 + 2 R RE Figure 62. High Impedance Differential Amplifier +VO + + MC34074 100 k - 10 + RL 10 +10 MC34074 + 220 pF 100 k -10 + + RL +VO -VO ∞ 18.93 -18.78 10 k 5.0 k 18 15.4 -18 -15.4 + MC34074 100 k - 10 RL 10 -VO Figure 63. Dual Voltage Doubler http://onsemi.
PAGE 18
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A ORDERING INFORMATION Op Amp Function Device Operating Temperature Range MC34071PG Shipping† 50 Units / Rail MC34071APG PDIP−8 (Pb−Free) 50 Units / Rail MC34071DG SOIC−8 (Pb−Free) 98 Units / Rail SOIC−8 (Pb−Free) 2500 / Tape & Reel MC34071ADG SOIC−8 (Pb−Free) 98 Units / Rail MC34071ADR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC33071PG PDIP−8 (Pb−Free) 50 Units / Rail MC33071APG PDIP−8 (Pb−Free) 50 Units / Rail MC33071DG SOIC−8 (Pb−Free) 98 Un
PAGE 19
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A ORDERING INFORMATION (continued) Op Amp Function Device Operating Temperature Range MC34072PG Package PDIP−8 (Pb−Free) MC34072APG PDIP−8 (Pb−Free) MC34072DG SOIC−8 (Pb−Free) MC34072ADG TA = 0° to +70°C SOIC−8 (Pb−Free) MC34072DR2G SOIC−8 (Pb−Free) MC34072ADR2G SOIC−8 (Pb−Free) MC34072AMTTBG WQFN10 (Pb−Free) MC33072PG PDIP−8 (Pb−Free) MC33072APG PDIP−8 (Pb−Free) MC33072DG SOIC−8 (Pb−Free) Dual MC33072ADG TA = −40° to +85°C SOIC−8 (Pb−Free)
PAGE 20
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A ORDERING INFORMATION (continued) Op Amp Function Device Package MC34074PG PDIP−14 (Pb−Free) MC34074APG PDIP−14 (Pb−Free) MC34074DG SOIC−14 (Pb−Free) MC34074ADG Quad Operating Temperature Range TA = 0° to +70°C SOIC−14 (Pb−Free) MC34074ADR2G SOIC−14 (Pb−Free) MC34074DR2G SOIC−14 (Pb−Free) MC33074PG PDIP−14 (Pb−Free) MC33074APG PDIP−14 (Pb−Free) MC33074DG SOIC−14 (Pb−Free) MC33074ADG SOIC−14 (Pb−Free) MC33074DR2G SOIC−14 (Pb−Free) NCV33074D
PAGE 21
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A MARKING DIAGRAMS PDIP−8 P SUFFIX CASE 626 8 8 MC3x071P AWL YYWWG 8 8 MC3x071AP AWL YYWWG 1 1 MC3x072P AWL YYWWG 1 8 MC3x072AP AWL YYWWG 1 MC34072VP AWL YYWWG 1 SOIC−8 D SUFFIX CASE 751 8 8 3x071 ALYWA 3x071 ALYW 8 3x072 ALYW 1 1 8 8 1 34072 ALYWV 3x072 ALYWA 1 1 *applies to NCV33072DR2G PDIP−14 P SUFFIX CASE 646 14 14 14 MC3x074AP AWLYYWWG MC3x074P AWLYYWWG 1 1 MC34074VP AWLYYWWG 1 SOIC−14 D SUFFIX CASE 751A 14 14 MC3x074DG
PAGE 22
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A PACKAGE DIMENSIONS 8 LEAD PDIP CASE 626−05 ISSUE N D A E H 8 5 E1 1 4 NOTE 8 c b2 B END VIEW TOP VIEW WITH LEADS CONSTRAINED NOTE 5 A2 A e/2 DIM A A1 A2 b b2 C D D1 E E1 e eB L M NOTE 3 L SEATING PLANE A1 C M D1 e 8X SIDE VIEW b 0.010 eB END VIEW C A M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3.
PAGE 23
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A PACKAGE DIMENSIONS TSSOP−14 CASE 948G ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U T U M V S S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A −V− ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 J J1 SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3.
PAGE 24
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE.
PAGE 25
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE K D A B 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 8 A3 E H L 1 0.
PAGE 26
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A PACKAGE DIMENSIONS WQFN10 CASE 510AJ ISSUE A D ÍÍÍ ÍÍÍ ÍÍÍ L1 PIN ONE REFERENCE DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS 0.15 C 0.15 C 0.10 C A3 DETAIL B 0.08 C DIM A A1 A3 b D E e L L1 L2 MOLD CMPD DETAIL B ALTERNATE CONSTRUCTIONS MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.20 0.30 2.60 BSC 2.60 BSC 0.50 BSC 0.45 0.55 0.00 0.15 0.55 0.65 A1 NOTE 4 SOLDERING FOOTPRINT* SEATING PLANE C SIDE VIEW 2.90 DETAIL A 5 L L2 NOTES: 1.