Datasheet

NCL30051
http://onsemi.com
11
High Voltage Startup Circuit
The NCL30051 internal startup regulator eliminates the
need for external startup components. In addition, this
regulator increases the efficiency of the supply as it uses no
power when in the normal mode of operation, but instead
uses power supplied by an auxiliary winding. The startup
regulator consists of a constant current source that supplies
current from the high voltage line (V
in
) to the supply
capacitor on the V
CC
pin (C
CC
). The startup current (I
start
)
is typically 7.5 mA. The startup circuit is rated at a
maximum voltage of 600 V.
Once C
CC
is charged to 15.3 V (V
CC(on)
), the startup
regulator is disabled and the PFC controller is enabled if the
PFB voltage exceeds V
PUVP(high)
. The startup regulator
remains disabled until the lower supply threshold, V
CC(off)
,
(typically 9.3 V) is reached. Once reached, the drive
outputs are disabled and the startup current source is
enabled. Once the outputs are disabled, the bias current of
the NCL30051 is reduced, allowing V
CC
to charge back up.
The supply capacitor provides power to the controller
while operating in the power up or self−bias mode. During
the converter power up, C
CC
must be sized such that a V
CC
voltage greater than V
CC(off)
is maintained while the
auxiliary supply voltage is building up. Otherwise, V
CC
will collapse and the controller will turn off. The IC bias
current and gate charge load at the drive outputs must be
considered to correctly size C
CC
. The increase in current
consumption due to external gate charge is calculated using
Equation 1.
I
CC(gate charge)
+ f @ Q
G
(eq. 1)
where, f is the operating frequency and Q
G
is the gate
charge of the external MOSFETs.
Main Oscillator
The oscillator frequency is set by the oscillator capacitor,
C
OSC
, on the OSC pin. The oscillator operates at a fixed
80% duty ratio. A current source charges C
OSC
to its peak
voltage, typically 5 V. Once the peak voltage is reached, the
charge current is disabled and C
OSC
is discharged down to
3 V by another current source. The charge and discharge
currents are typically 173 and 692 mA, respectively. The
oscillator frequency vs oscillator capacitance graph is
shown in Figure 3.
Figure 3. Oscillator Frequency vs.
Oscillator Capacitor
C
OSC
, OSCILLATOR CAPACITOR (pF)
2400200016001200400
0
10
30
40
60
70
90
100
f
OSC
, OSCILLATOR FREQUENCY (kHz)
20
50
80
800
An internal clock signal is generated by dividing the
oscillator frequency by two. This clock signal is used to
control the half−bridge driver. The half−bridge duty ratio
is limited to 50%. The PFC is not synchronized to the
oscillator as it operates in variable frequency mode.
Half−Bridge Disable
The half−bridge oscillator and the half−bridge low and
high side drivers are disabled once the voltage on the OSC
pin is brought below the half−bridge disable threshold,
V
HB(DIS)
(typically 1.955 V). This can be accomplished by
pulling down on the oscillator pin using a transistor or open
collector/drain device. Once the oscillator pin is released
the oscillator capacitor returns to its normal operating
range and the half bridge is re−enabled. The low side
half−bridge driver generates the first drive pulse during
initial power up or re−starting of the half−bridge. This
ensures boost voltage is generated to supply the high side
driver.
Voltage Reference
The internal voltage reference, V
REF
, is brought out of
the controller to ease compensation requirements. The
reference voltage is typically 7.0 V. A 0.1 mF bypass
capacitor is required for stability. The reference should not
be loaded with external circuitry.