Datasheet

NCL30051
http://onsemi.com
12
PFC Regulator
The PFC inductor current, I
L(t)
, reaches zero at the end
of the switch cycle as shown in Figure 4 and the average
input current, I
in(t)
, is in phase with the ac line voltage,
V
in(t)
.
Figure 4. Inductor Current in CrM
PFC MOSFET
Drive Signal
I
in
(t)
I
L
(t)
V
in
(t)
t
t
High power factor is achieved in CrM by maintaining a
constant on time (t
on
) for a given RMS input voltage
(V
ac(RMS)
) and load conditions. Equation 2 shows the
relationship between on time and system operating
conditions.
t
on
+
2 @ P
out
@ L
h @ V
ac(RMS)
2
(eq. 2)
where, P
out
is the output power, L is the PFC inductor
inductance and h is the system efficiency.
On Time Control
The NCL30051 controls the on time by charging an
external timing capacitor on the PCT pin, C
T
, with a
constant current source, I
PCT(C)
. The C
T
ramp is then
compared to the control voltage, V
PControl
. The control
voltage is constant for a given RMS line voltage and output
load, satisfying Equation 2. The block diagram of the
constant on time section is shown in Figure 5.
Figure 5. Constant On Time Control Block Diagram
Error
Amplifier
+
+
PFB
Level
Shifter
+
+
+
PFC OVP
Comparator
On time
Comparator
+
+
ZCD
Comparator
PFCoff
PZCD
PCS
LEB
+
Clamp
> 5.65 V
Clamp
PCS
Comparator
+
+
PFC UVP
Comparator
+
V
DD
< 2.25 V
V
DD
−
V
PREF
−
I
PCT(C)
−
−
V
POVP
−
−
−
V
PUVP
−
−
S
R
Q
Dominant
Reset
Latch
Q
−
V
ZCD
V
CC
Good
PCT
PFC
V
PCS(ILIM)
I
PFB
PControl
10V
The PControl voltage is internally clamped between
2.25 V and 5.65 V. A voltage offset, V
PCT(offset)
, is added
to the C
T
ramp to account for the control voltage range.
This allows the PFC stage to stop the drive pulses (0% duty
ratio) and regulate at light loads. The delta between the
PControl voltage needed to generate a PDRV pulse and the
minimum PControl Clamp voltage is V
PCT(offset)
.
The timing capacitor is discharged and held low once the
C
T
ramp voltage plus offset reaches V
PControl
. The PFC
drive pulse terminates once the C
T
voltage reaches its peak
voltage threshold, V
PCT(peak)
. A new cycle starts once the
inductor current reaches zero detected by a transition on the
ZCD pin or the maximum off time has been reached.
The timing capacitor is sized such that the C
T
ramp peak
voltage is reached at low line and full load. In this operating
mode V
PControl
is at its maximum. Equation 3 is used to
calculate the on time for a given C
T
.
t
on(MAX)
+
C
T
@ V
PCT(peak)
I
PCT(C)
(eq. 3)
Substituting t
on
in Equation 2 with Equation 3 and
rearranging Equation 4 provides a maximum value for C
T
.
C
T
w
2 @ P
out
@ L @ I
PCT(C)
h @ V
ac(RMS)
2
@ V
PCT(peak)
(eq. 4)
where, V
PCT(peak)
, is the maximum PCT voltage, typically
3.0 V.