Datasheet

NCL30051
http://onsemi.com
2
Figure 1. Functional Block Diagram
HVS
HDRVhi
HBoost
Error
Amplifier
+
+
PFB
PControl
Level
Shifter
+
+
+
PFC OVP
Comparator
On time
Comparator
+
+
ZCD
Comparator
PZCD
PDRV
PCS LEB
+
HDRVlo
GND
OSC
+
+
Clock
Delay
Pulse
Level
S
R
Q
Undervoltage
Detector
Q
Enable
+
+
VCC
Management
VREF
Voltage
Reference
UVLO
Q
CLK
Q
Clamp
> 5.65 V
Clamp
HV
PCS
Comparator
+
+
PFC UVP
Comparator
PDRV
+
VCC
< 2.25 V
−
−
−
−
−
−
−
−
−
S
R
Q
Dominant
Reset
Latch
Delay
Trigger
Shifter
Dominant
Reset
Latch
VCC
−
−
5 V /
3 V
VCC
−
−
−
Good
PCT
PFC
S
R
UVLO
CLK
+
+
−
−
Disable
UVLO
PFC UVP
Disable
PDRV
Reset
UVLO
Edge
Detector
V
PCS(ILIM)
V
PUVP
V
CC
Good
V
POVP
V
DD
I
PCT(C)
I
PFB
V
PREF
PFCUVP
V
ZCD
V
DD
V
CC
I
start
C
boost
D
boost
t
PFC(off)
Timer
Q
Q
Q
V
DD
4*I
OSC(C)
V
DD
V
HB(DIS)
I
OSC(C)
V
CC(on)
/
V
CC(off)
/
UVLO
C
CC
10V