Datasheet

NCL30100
http://onsemi.com
9
and I3 represent different delays depending on the
magnitude of IVC.
Gate Driver
The Gate Driver consists of a CMOS buffer designed to
directly drive a power MOSFET. It features unbalanced
source and sink capabilities to optimize switch on and off
performance without additional external components. The
power MOSFET is switched off at high drain current, to
minimize its switch off losses the sink capability of the gate
driver is increased for a faster switch off. On the other hand,
the source capability of the driver is reduced to slow−down
the power MOSFET at switch on in order to reduce EMI
generation. Whenever the IC supply voltage is lower than
the under voltage threshold, the Gate Driver is low, pulling
down the gate to ground thus eliminating the need for an
external resistor.
Input Voltage Compensation:
The Input Voltage Compensation block gives the user
optional flexibility to sense the input voltage and modify the
current sense threshold and off time. This function provides
a feed forward mechanism that can be used when the input
voltage of the controller is loosely regulated to improve
output current regulation. If the input voltage is well
regulated, the IVC input can also be used to adjust the offset
of the off time comparator and the current sense control to
achieve the best current regulation accuracy.
An external resistor connected between IVC and the input
supply results in a current being injected into this pin which
has an internal 17 kW resistor connected to a current mirror.
This current information is used to modify V
offset
and I
CS
.
By changing V
offset
the off time comparator threshold is
modified and the off time is increased. A small capacitor
should be connected between the IVC pin and ground to
filter out noise generated during switching period. Figure 19
shows the simplified internal schematic:
Figure 19. Input Voltage Compensation, OFF Time
Control
Current
Mirror
1:1
Current
Mirror
1:1
25 kW
VOffset
To OFF
Time
Comparator
V
CC
17 kW
IVC
Figure 20. IVC Loop Transfer Characteristic
V
IVC Pin Sink Current
Voffset
VDD
mA
0
OFF Time Comparator Input
Voltage
The transfer characteristic (output voltage to input
current) of the input voltage compensation loop control
block can be seen in Figure 20. V
DD
refers to the internal
stabilized supply. If no IVC current is injected, the off time
comparator is set to V
offset
.
The value of the current injected into IVC also change Ics.
This is accomplished by changing the voltage drop on R
shift
.
The corresponding block diagram of the IVC pin can be seen
in Figure 21.
Figure 21. Input Voltage Compensation Loop – Current Sense Control
Current
Mirror
4:3
To Current Sense Comparator
17 kW
IVC
CS
37.5 mA
12.5 mA