Datasheet

NCP1351
http://onsemi.com
17
Depending on the design conditions (DCM or CCM), the
error flag assertion will correspond to either 50% of the
maximum power (full load DCM design) or a value above
this number if the converter operates in CCM at full load and
remains in CCM at half the switching frequency.
The figures below details circuits operation for the various
controller options.
Vcc
ON
Vcc
stop
V
cc
I
FB
V
timer
40 μA
fault
V
timer
DRV
V
zener
FB reacts
ok
startup
User
reset
ICC < 20 μA
ok
ICC1
ICC1
Pulldown
SCR action
Latched
state
fault
FB reacts
ok
startup
A version, latched
User
reset
ICC < 20 μA
ok
ICC1
ICC1
Pulldown
SCR action
Latched
state
Figure 20. The A Version Latches-off in Presence of a Fault
Vcc
ON
Vcc
stop
V
cc
I
FB
V
timer
40 μA
fault
V
timer
DRV
V
zener
FB reacts
ok
startup
Auto-recovery
Pulses
stopped
Fault
still present
ICC4 ICC1
ICC1
Vcc
ON
Vcc
stop
V
cc
I
FB
V
timer
40 μA
fault
V
timer
DRV
V
zener
FB reacts
ok
startup
B version, auto-recovery
Auto-recovery
Pulses
stopped
Fault
still present
ICC4 ICC1
ICC1
Figure 21. The B Version Enters an Auto-Recovery Burst Mode in Presence of a Fault