Datasheet

NCP1351
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20
Let us round it to 0.25 or 1/N = 4
Figure 26. Primary Inductance Current Evolution
in CCM
DT
SW
I
L
T
SW
I
peak
I
valley
I
valley
I
avg
I
1
t
2. Calculate the maximum operating duty-cycle for
this flyback converter operated in CCM:
d
max
+
V
out
ńN
V
out
ńN ) V
in_min
+
19 4
19 4 ) 100
+ 0.43
(eq. 21)
In this equation, the CCM duty-cycle does not exceed
50%. The design should thus be free of subharmonic
oscillations in steady-state conditions. If necessary,
negative ramp compensation is however feasible by the
auxiliary winding.
3. To obtain the primary inductance, we can use the
following equation which expresses the inductance
in relationship to a coefficient k. This coefficient
actually dictates the depth of the CCM operation.
If it goes to 2, then we are in DCM.
L +
(
V
in_min
d
max
)
2
F
SW
KP
in
(eq. 22)
where K = I
L
/I
I
and defines the amount of ripple we want
in CCM (see Figure 26).
• Small K: deep CCM, implying a large primary
inductance, a low bandwidth and a large leakage
inductance.
• Large K: approaching BCM where the RMS losses are
the worse, but smaller inductance, leading to a better
leakage inductance.
From Equation 17, a K factor of 0.8 (40% ripple) ensures a
good operation over universal mains. It leads to an
inductance of:
L +
(
100 43
)
2
65k 0.8 72
+ 493H
(eq. 23)
+ 1.34Apeak-to-peak
(eq. 24)
I
L
+
V
in_min
d
max
LF
SW
+
100 0.43
493u 65k
The peak current can be evaluated to be:
I
in_avg
+
P
out

V
in_min
+
19 3
0.8 100
+ 712mA
(eq. 25)
I
peak
+
I
avg
d
)
I
L
2
+
0.712
0.43
)
1.34
2
+ 2.33A
(eq. 26)
On Figure 26, I
1
can also be calculated:
I
I
+ I
peak
*
I
L
2
+ 2.33 *
1.34
2
+ 1.65A
(eq. 27)
The valley current is also found to be:
I
valley
+ I
peak
* I
L
+ 2.33 * 1.34 + 1.0A
(eq. 28)
4. Based on the above numbers, we can now evaluate
the RMS current circulating in the MOSFET and
the sense resistor:
I
d_rms
+ I
I
d
Ǹ
1 )
1
3
ǒ
I
L
2I
1
Ǔ
2
Ǹ
(eq. 29)
+ 1.65 0.65
1 )
1
3
ǒ
1.34
2 1.65
Ǔ
2
Ǹ
+ 1.1A
5. The current peaks to 2.33 A. Selecting a 1 V drop
across the sense resistor, we can compute its value:
R
sense
+
1
I
peak
+
1
2.5
+ 0.4
(eq. 30)
To generate 1 V, the offset resistor will be 3.7 k, as already
explained. Using Equation 29, the power dissipated in the
sense element reaches:
P
sense
+ R
sense
I
d_rms
2
+ 0.4 1.1
2
+ 484mW
(eq. 31)
6. To switch at 65 kHz, the C
t
capacitor connected to
pin 2 will be selected to 180 pF.
7. As the load changes, the operating frequency will
automatically adjust to satisfy either equation 5
(high power, CCM) or equation 6 in lighter load
conditions (DCM).
Figure 27 portrays a possible application schematic
implementing what we discussed in the above lines.