Datasheet

NCV8873
http://onsemi.com
2
Gm
8
3
2
4
6
GND
ISNS
GDRV
VIN
VFB
5
VDRV
CSA
OSC
Q
D1
L
SC
TEMP
VDRV
DRIVE
LOGIC
CL
SS
FAULT
LOGIC
CLK
1
EN/SYNC
EN/
SYNC
7
VC
PWM
+
R
C
C
C
R
SNS
R
F1
V
ref
C
DRV
V
g
V
o
C
g
C
o
Figure 1. Simplified Block Diagram and Application Schematic
D2
Dn
PACKAGE PIN DESCRIPTIONS
Pin No.
Pin
Symbol
Function
1 EN/SYNC Enable and synchronization input. The falling edge synchronizes the internal oscillator. The part is disabled
into sleep mode when this pin is brought low for longer than the enable time−out period.
2 ISNS Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense
resistor to ground to sense the switching current for regulation and current limiting.
3 GND Ground reference.
4 GDRV Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from
GDRV to the gate to tailor EMC performance.
5 VDRV Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VIN. Bypass
with a 1.0 mF ceramic capacitor to ground.
6 VIN Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addi-
tion to a diode from the output voltage to VDRV and/or VIN.
7 VC Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize
the converter.
8 VFB Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND
creates a voltage divider for regulation and programming of the output voltage.