Data Sheet

NDP6020P / NDB6020P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
________________________________________________________________________________
Absolute Maximum Ratings T
C
= 25°C unless otherwise noted
Symbol Parameter NDP6020P NDB6020P Units
V
DSS
Drain-Source Voltage -20 V
V
GSS
Gate-Source Voltage - Continuous ±8 V
I
D
Drain Current - Continuous -24 A
- Pulsed -70
P
D
Total Power Dissipation @ T
C
= 25°C
60 W
Derate above 25°C 0.4 W/°C
T
J
,T
STG
Operating and Storage Temperature Range -65 to 175 °C
Publication Order Number:
NDP6020P/D
-24 A, -20 V. R
DS(ON)
= 0.05 @ V
GS
= -4.5 V.
R
DS(ON)
= 0.07 @ V
GS
= -2.7 V.
R
DS(ON)
= 0.075 @ V
GS
= -2.5 V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R
DS(ON)
.
TO-220 and TO-263 (D
2
PAK) package for both through
hole and surface mount applications.
General Description Features
These logic level P-Channel enhancement mode power field
effect transistors are produced using ON Semiconductor's
proprietary, high cell density, DMOS technology. This very
high density process has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulses in
the avalanche and commutation modes. These devices
are particularly suited for low voltage applications such
as automotive, DC/DC converters, PWM motor controls,
and other battery powered circuits where fast switching,
low in-line power loss, and resistance to transients are
needed.
D
S
G
© 1997 Semiconductor Components Industries, LLC.
September-2017, Rev. 3

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