Data Sheet

©2002 Fairchild Semiconductor Corporation
RFP50N06 Rev. C0
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. SWITCHING WAVEFORMS
RFP50N06
Typical Performance Curves Unless Otherwise Specified (Continued)
C
ISS
C
OSS
C
RSS
4000
3000
2000
1000
0
0 5 10 15 20 25
C, CAPACITANCE (pF)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
= C
DS
+ C
GD
60
45
30
15
0
10
7.5
5.0
2.5
0
20
I
g(REF)
I
g(ACT)
80
I
g(REF)
I
g(ACT)
t, TIME (µs)
V
DD
= BV
DSS
V
DD
= BV
DSS
0.75 BV
DSS
0.50 BV
DSS
0.25 BV
DSS
0.75 BV
DSS
0.50 BV
DSS
0.25 BV
DSS
V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
V
GS
,
GATE TO SOURCE VOLTAGE (V)
R
L
= 1.2Ω
I
g(REF)
= 1.45mA
V
GS
= 10V
t
P
V
GS
0.01Ω
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0