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ManualsBrandsonsemi ManualsOtheronsemi NCP51820 GaN Driver, PCB Design and Layout

APPLICATION NOTE

www.onsemi.com

 Semiconductor Components Industries, LLC, 2019

August, 2021 − Rev. 3

1 Publication Order Number:

AND9932/D

NCP51820 GaN Driver,

PCB Design and Layout

AND9932/D

ABSTRACT

The NCP51820 is a 650−V, high speed, half−bridge driver

capable of driving GaN power switches at dV/dt rates up to

200 V/ns. The full performance benefit of switching high

voltage at high frequency with fast dV/dt edge rates can only

be achieved with a properly designed printed circuit board

(PCB) capable of supporting such aggressive power

switching transitions. This whitepaper will highlight the

most important PCB design considerations that must be

taken into account for successfully designing a GaN based,

half−bridge, gate drive circuit utilizing the NCP51820.

INTRODUCTION

The NCP51820 is a full−featured, dedicated driver

intended to maximize high electron mobility transistor

(HEMT) GaNFET switching performance. For similar rated

breakdown voltage, GaNFETs are fabricated using a smaller

die size compared to silicon. As a result, GaNFETs have

significantly reduced gate charge, output capacitance and

dynamic on−resistance compared to even the best in class

silicon MOSFETs. In addition, GaNFETs do not include p-n

junctions so there is no intrinsic, parasitic body−diode across

the drain−source and therefore no reverse recovery charge

associated with third quadrant operation.

GaNFETs can be especially beneficial in off−line,

half−bridge power topologies, bridgeless PFC and

single−ended, active clamp topologies. These power stages

often employ zero voltage switching (ZVS) but can also

operate under hard−switching conditions, from voltages in

the range of 400 V. These combined improvements, enable

GaNFETs to switch at or near frequencies in the MHz range

with drain−source edge rates as high as 100 V/ns. Achieving

optimal performance from GaN based power stages is

highly dependent upon the designer’s understanding of

parasitic circuit elements such as package inductance, PCB

trace inductance, transformer capacitance and component

selection and placement. While these various parasitic

elements also exist in silicon MOSFET power systems, they

become much more responsive and therefore, problematic

when stimulated by the high dV/dt and di/dt that can exist in

a GaN power solution.

The NCP51820, MLP leadless power package (Figure 3)

combined with the various leadless GaNFET power

packages (Figure 1 and Figure 2) available in the industry

attest to the amount of design effort placed upon minimizing

parasitic inductance. Similarly, specific care must be given

to the PCB design and component placement. This

whitepaper will focus on some of the most important PCB

design considerations necessary to take full advantage of the

benefits offered from using the NCP51820 for driving GaN

power switches used in high−speed, half−bridge power

topologies.

HEMT GaN AND NCP51820 PACKAGE

DESCRIPTIONS

Most GaNFET packages include a dedicated source

Kelvin return, shown as “SK” in Figure 1, which is intended

only to carry gate drive return current back to the

NCP51820. The higher current drain−source pins are

bonded to multiple pads using multiple bond wires, although

the simplified diagram in Figure 1 shows only single bond

wire connections for simplicity. The interface between the

NCP51820 outputs and the GaNFET gate−source Kelvin

needs to be a direct single point connection and is especially

critical as described in section

GaNFET with Source Kelvin

Pin.

However, not all GaNFETs include a dedicated source

Kelvin return, such as the example shown in Figure 2. For

GaNFETs that do not include a source Kelvin return, special

care must be taken when routing the gate drive portion of the

PCB design. For the switch−node connection in

ahalf−bridge power stage, the source of the high−side

GaNFET connects directly to the drain of the low−side

GaNFET creating a high dV/dt node carrying high di/dt load

current. Referencing the gate drive return directly from this

high−voltage switch−node is not recommended as described

in section

GaNFET without Source Kelvin Pin

Summary of content (13 pages)

PAGE 1
APPLICATION NOTE www.onsemi.com NCP51820 GaN Driver, PCB Design and Layout AND9932/D ABSTRACT The NCP51820 is a 650−V, high speed, half−bridge driver capable of driving GaN power switches at dV/dt rates up to 200 V/ns. The full performance benefit of switching high voltage at high frequency with fast dV/dt edge rates can only be achieved with a properly designed printed circuit board (PCB) capable of supporting such aggressive power switching transitions.
PAGE 2
AND9932/D G G SK S D D S S S S Figure 2. Typical GaN without Source Kelvin Return The NCP51820 is packaged in a 4x4 mm, leadless package with all logic level inputs and programming functions grouped together on the right side of the IC, separate from the power functions which are strategically grouped on the remaining three sides of the IC. The pins are strategically placed to provide high−voltage isolation where necessary.
PAGE 3
AND9932/D PCB DESIGN STRATEGY SUMMARY closely matched as possible. To avoid high current and high dV/dt through vias, it is preferred that both GaNFETs be located on the same side of the PCB as the NCP51820. 7. The HO and LO gate drives should be considered as two independent gate drive circuits that are electrically isolated from each other. HO and LO will therefore each require dedicated copper land return planes on layer 2 directly beneath layer 1 gate drive routing.
PAGE 4
AND9932/D GaNFET with Source Kelvin Pin Many GaNFET packages include a dedicated source Kelvin pin, reserved for isolating the gate drive return current from the higher current and voltage levels seen at the power switch−node (high−side) or power ground (low−side). For GaNFETs with dedicated source Kelvin pins, the gate−drive routing is fairly straight forward.
PAGE 5
AND9932/D VDD Capacitors frequency bypass capacitor (typically 0.1 mF) should be placed closest to the VDD pin along with a second parallel capacitor (1 mF) as shown in Figure 7. The VDD pin should have two ceramic capacitors placed as close to the VDD pin as possible. A lower value high VDD CAPACITORS HS GaNFET VDD SGND LS GaNFET SGND PLANE Figure 7.
PAGE 6
AND9932/D VBST Capacitor and Diode, VDDH and VDDL Bypass Capacitors switch−node. The only connection from “switch−node” is through the HS GaNFET source Kelvin pin. The HS gate return plane should be designed such that there is no overlap or interaction with the power stage switch−node. Similarly, the LS gate return plane should be designed such that there is no overlap or interaction with the LS GaNFET power ground.
PAGE 7
AND9932/D Gate Drive Routing driver source impedance, the gate−source resistor, and into the GaNFET gate. The current then returns from the GaNFET source Kelvin pin and back to the VDDH bypass capacitor. When the NCP51820 is sourcing current to the HS GaNFET gate, the gate current is derived from the charge stored in the VDDH regulator bypass capacitor.
PAGE 8
AND9932/D When the NCP51820 is sourcing current to the LS GaNFET gate, the gate current is derived from the charge stored in the VDDL regulator bypass capacitor. As shown in Figure 11, source current flows through the LO driver source POWER SWITCH NODE LO SRC PGND KELVIN SEPARATION OF GATE DRIVE AND MAIN SWITCH CURRENT impedance, the gate−source resistor, and into the GaNFET gate. The current then returns from the GaNFET source Kelvin pin and back to the VDDL bypass capacitor.
PAGE 9
AND9932/D connection between the NCP51820 PGND and the power PGND, as illustrated in Figure 11 and Figure 12. Both HS and LS gate traces should be as equal in length as the design allows. This will help assure both GaNFETs have similar gate drive impedance. Staggering the alignment of the high−side and low−side GaNFETs serves the dual purpose of allowing nearly symmetrical, equidistant gate drive routing and permitting a larger, higher current, power switch−node copper land.
PAGE 10
AND9932/D Signal Ground (SGND) and Power Ground (PGND) PGND should be connected together on the PCB. In such applications, it is recommended to connect the SGND and PGND pins together with a short, low−impedance trace on the PCB as close to the NCP51820 as possible. Directly beneath the NCP51820 is an ideal way to make the SGND to PGND connection as illustrated in Figure 13. SGND is the GND for all internal control logic and digital inputs. Internally, the SGND and PGND pins are isolated from each other.
PAGE 11
AND9932/D PGND SGND PLANE VIAS CS HO LO HIN LIN SGND GND VDD CONTROLLER SGND PLANE VRCS CURRENT SENSE RESISTOR RCS POWER STAGE PGND VRCS RETURN LS GATE RETURN PLANE (ISOLATED FROM SGND and POWER STAGE PGND) Figure 14. LS Gate Return Isolation and VRCS Connection www.onsemi.
PAGE 12
AND9932/D SWITCHING PERFORMANCE VERIFICATION The PCB design techniques illustrated in this document were used to layout a half−bridge power stage utilizing the NCP51820 driving GaNFETs. Figure 15. 650 V, 18 A, HEMT, GaNFETs, 350 V, 10 APK probe to measure a low−voltage floating signal, measured from gate to power, switch−node. A “truer” measurement of the gate−source voltage is shown by channel 2 (red) where the low−side GaNFET gate−source voltage is measured referenced from gate to PGND.
PAGE 13
AND9932/D The waveform shown in Figure 16 is a result of driving two HEMT, GIT, 600 V, 26 A, 56 mW GaNFETs which have higher current capability compared to the devices used in Figure 15. To achieve high dV/dt, a significant amount of drain current, ID is required. For example, the measurement shown is taken at ID = 20 APK resulting in a measured VDS, dV/dt = 75 V/ns. The triangular, peak inductor current appears as DC only because of the time base (2 ns/div) necessary to make this measurement.