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SPARC/CPU−56T

Reference Guide

P/N 224548 Revision AA

November 2004

Summary of content (145 pages)

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SPARC/CPU−56T Reference Guide P/N 224548 Revision AA November 2004
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Copyright The information in this publication is subject to change without notice. Force Computers, GmbH reserves the right to make changes without notice to this, or any of its products, to improve reliability, performance, or design.a Force Computers, GmbH shall not be liable for technical or editorial errors or omissions contained herein, nor for indirect, special, incidental, or consequential damages resulting from the furnishing, performance, or use of this material.
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World Wide Web: www.fci.com 24−hour access to on−line manuals, driver updates, and application notes is provided via SMART, our SolutionsPLUS customer support program that provides current technical and services information. Headquarters The Americas Europe Asia Force Computers Inc. 4211 Starboard Drive Fremont CA 94538 Force Computers GmbH Lilienthalstr. 15 D−85579 Neubiberg/München Tel.: +1 (510) 624−5300 Fax: +1 (510) 624−5301 Email: support@fci.com Tel.
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SPARC/CPU−56T
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Contents Using this Guide Other Sources of Information Safety Notes Sicherheitshinweise 1 Introduction Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Standard Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RS−422 Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PS/2 Splitter Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Board Installation . . . . . . . . . . . . . .
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4 Devices’ Features and Data Paths Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 UltraSPARC IIi+ Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 PCI Bus A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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CORE Workflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 CORE Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 POST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 OpenBoot . . . . . . . .
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UltraSPARC−IIi+ Internal CSR Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 PCI Bus Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 PCIO−2 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 System Configuration Registers . . . . . . .
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Product Error Report 10 SPARC/CPU−56T
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Tables Introduction Tablei1aaaaaaaStandard Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tablei2aaaaaaaProduct Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tablei3aaaaaaaBoard Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Tablei29aaaaaaLED Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tablei30aaaaaaLED Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tablei31aaaaaaExternal Failure Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tablei32aaaaaaWatchdog Timer Control Register . . .
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Figures Introduction Figurei1aaaaaaaFunction Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Installation Figurei2aaaaaaaLocation of PMC Voltage Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figurei3aaaaaaaLocation of Switches on Board’s Top Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Using this Guide This Reference Guide is intended for users qualified in electronics or electrical engineering. Users must have a working understanding of Peripheral Component Interconnect (PCI), VMEbus, and telecommunications. Conventions Notation Description 57 All numbers are decimal numbers except when used with the notations described below. 00000000 16 or 0x00000000 Typical notation for hexadecimal numbers (digits 0 through F), e.g.
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Notation Description Possibly dangerous situation: slight injuries to people or damage to objects possible Dangerous situation: injuries to people or severe damage to objects possible Start of a p procedure End of a p procedure Abbreviations Abbreviation Description B B BGA BIB BMC Ball Grid Array Board Information Block Base Board Management Controller C C CAS CSR Column Address Select Control Status Register D D DMA DRAM Direct Memory Access Dynamic Random Access Memory E E ECC EEPROM
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Abbreviation Description F F FAE FIFO Field Application Engineers First In First Out FPGA Field−Programmable Gate Array I I IBMU ICMB Intelligent Board Management Unit Intelligent Chassis Management Bus ICT In−Circuit Test IDE Integrated Drive Electronics IEC International Electric Code IOBP Input Output Back Panel IOM I/O Memory Management Unit IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface ISO International Organization for Standardiz
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Abbreviation PCIO PHY PIE PLCC PLL PMC POST PROM Description Peripheral Component Interconnect Input/Output Physical Layer PCI Interrupt Engine Plastic Leadless Chip Carrier Phase−Locked Loop PCI Mezzanine Card Power−On Self−Test Programmable Read Only Memory R R RIC ROM RTB RTC RTOS Reset/Interrupt/Clock Controller Read Only Memory Rear Transition Board Real−Time Clock Real Time Operating System S S SDRAM SELV SPD SRAM STP Synchronous DRAM Safety Extra Low Voltages Serial Presence Detect Static Ra
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Order No. Rev. Date Description 223146 AA April 2004 Corrected number of SUN patch for audio support. Now it reads 109896−17; added note to abort/reset key description; corrected feature list of FRctrl Solaris driver 224548 AA November 2004 Corrected typical and maximum power consumption values for 5V.
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Other Sources of Information For further information refer to: Company www. Document ALI Corporation ali.com.tw ALI M1535D+ Southbridge documentation Force Computers forcecomputers.com SPARC/IOBP−CPU−56 Installation Guide aa SPARC/IOBP−IO−56 Installation Guide SPARC/MEM−550 Installation Guidea ACC/CABLE/SCSI−U160 Installation Guide ACC/CABLE/RS422 Installation Guide IEEE Standards Department ieee.com IEEE P1386 Standard Mechanics for a Common Mezzanine Card Family: CMC Intel intel.
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Safety Notes The text in this chapter is a translation of the Sicherheitshinweise" chapter This section provides safety precautions to follow when installing, operating, and maintaining the board. We intend to provide all necessary information to install and handle the board in this Installation Guide. However, as the product is complex and its usage manifold, we do not guarantee that the given information is complete. If you need additional information, ask your Force Computers representative.
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Setting/resetting the switches during operation causes board damage. Therefore, check and change switch settings before you install the board. Installation Electrostatic discharge and incorrect board installation and removal can damage circuits or shorten their life. Therefore: S Touching the board or electronic components in a non−ESD protected environment causes component and board damage. Before touching boards or electronic components, make sure that you are working in an ESD−safe environment.
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Check the total power consumption of all components installed (see the technical specification of the respective components). Ensure that any individual output current of any source stays within its acceptable limits (see the technical specification of the respective source). RJ−45 Connector The RJ−45 connector on the front panel must only be used for twisted−pair Ethernet (TPE) connections. Connecting a telephone to such a connector may destroy your telephone as well as your board.
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Sicherheitshinweise Dieser Abschnitt enthält Sicherheitshinweise, die bei Einbau, Betrieb und Wartung des Boards zu beachten sind. Wir sind darauf bedacht, alle notwendigen Informationen, die für die Installation und den Betrieb erforderlich sind, in diesem Handbuch bereit zu stellen. Da es sich jedoch bei dem Board um ein komplexes Produkt mit vielfältigen Einsatzmöglichkeiten handelt, können wir die Vollständigkeit der im Handbuch enthaltenen Informationen nicht garantieren.
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gekennzeichneten Schalter nicht, da diese Schalter mit produktionsrelevanten Funktionen belegt sein können, die im normalen Betrieb Störungen auslösen könnten. Das Ändern der Schaltereinstellungen während des laufendes Betriebs kann das Board beschädigen. Prüfen und ändern Sie die Schaltereinstellungen, bevor Sie das Board installieren. Installation Elektrostatische Entladung und unsachgemäßer Ein− und Ausbau des Boards kann Schaltkreise beschädigen oder ihre Lebensdauer verkürzen.
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entstehen können. Stellen Sie vor dem Einschalten des Stroms sicher, dass sich auf dem Board kein Kondensat befindet und betreiben Sie das Board nicht unter 0°C. Wenn Sie das Board in Gebieten mit starker elektromagnetischer Strahlung betreiben, stellen Sie sicher, dass das Board mit dem System verschraubt ist und das System durch ein Gehäuse abgeschirmt wird. Stellen Sie sicher, dass Anschlüsse und Kabel des Boards während des Betriebs nicht versehentlich berührt werden können.
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S Verwenden Sie die Batterien länger als sieben Jahre, kann dies zu Datenverlusten führen. Tauschen Sie deshalb die Batterie aus, bevor sieben Jahre reiner Betrieb vorüber sind. S Der Austausch der Batterie bringt immer einen Datenverlust bei den Komponenten mit sich, die sich durch die Batterie die Stromversorgung sichern. Sichern Sie deshalb vor dem Batterieaustausch Ihre Daten.
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1 Introduction Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Standard Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Product Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Introduction Features Features The SPARC/CPU56 is a high−performance VME single−board computer based on the 650 Mhz UltraSPARC IIi+ processor. It provides 512 MByte on−board SDRAM memory.
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Features Introduction Figure 1: Function Blocks SPARC/CPU−56T 29
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Introduction Standard Compliances Standard Compliances The CPU board was designed to comply with the standards listed below. Table 1: Standard Compliances 30 Standarda Description IEC 68−2−1/2/3/13/14 Climatic environmental requirements. IEC 68−2−6/27/32 Mechanical environmental requirements EN 609 50/UL 1950 (predefined Force system); UL 94V−0/1 Legal safety requirements EN 55022,a EN 55024, FCC Part 15 Class A EMC requirements on system level ANSI/IPC_A−610 Rev.
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Ordering Information Introduction Ordering Information When ordering board variants, hard− and software upgrades use the order numbers given below. Product Nomenclature In the following table you find the key for the product name extensions used for board variants.
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Introduction 32 Ordering Information Order No.
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2 Installation Action Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .
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FRCflash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 FRCctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 FRCplatmod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Action Plan Installation Action Plan In order to install the board, the following steps are necessary and will be described in further detail in the sections of this chapter.
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Installation Requirements Requirements In order to meet the environmental requirements, the CPU board has to be tested in the system in which it is to be installed.a Before you power up the board, calculate the power needed according to your combination of board upgrades and accessories. Environmental Requirements The environmental conditions must be tested and proven in the used system configuration. The conditions refer to the surrounding of the board within the user environment.
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Requirements Installation Feature Operating Non−Operating Shock 5g/11 ms halfsine 15g/11 ms halfsine Free fall 100 mm / 3 axes 1,200 mm / all edges and corners (packed state) Power Requirements The board power requirements depend on the installed hardware accessories. In the following table you will find typical examples of power requirements without any accessories installed.
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Installation Hardware Accessories Hardware Accessories The following upgrades and accessories are available: S IOBPs for CPU and I/O Board S PMC modules S Memory modules S Hard Disk S SCSI−U160 cable S RS−422 serial cable S PS2 splitter cable IOBPs for CPU and I/O Board As separate price list items two IOBPs are available for the SPARC/CPU−56T. One is called SPARC/IOBP−IO−56 and is connected to the I/O board.
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Hardware Accessories Installation Note:aOn the IOBP−CPU−56−3 the RS−232 signals are limited to RXD, TXD, RTS and CTS.a On the IOBP−CPU−56−5 the additional signals DTR, DSR, DCD and RI are available.a In addition to these interfaces, the five−row variant IOBP−CPU−56−5 provides: S Keyboard/mouse interface (SUN or PS/2 style) S Third USB interface S Floppy interface S 10/100/1000 Base−TX Ethernet For details about this IOBP and its installation refer to theaSPARC/IOBP−CPU−56 Installation Guide.
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Installation Hardware Accessories PMC#4 PMC#3 PMC#2 PMC slot 2 supports a 64−bit data bus width with a maximum frequency of 33 MHz and is attached to PCI bus B. PMC slots 3 and 4 support a 64−bit data bus width with a maximum frequency of 66 MHz and are attached to PCI bus C.a If a 32−bit PMC module is mounted into PMC slots 3 and 4, the Sentinel64 PCI−to−PCI bridge dynamically detects the 32−bit bus and changes its transfer size to 32−bit for this PMC module.
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Hardware Accessories Installation Installation Procedure Note:a S To ensure proper EMC shielding, either operate each PMC slot with a blind panel or with a PMC module installed. S If the SPARC/CPU−56T is upgraded with PMC modules, ensure that the blind panels are stored in a safe place in order to be used again when removing the respective PMC module.a S Processor PMC modules are only supported in non−monarch mode.a Removing I/O Board Start 1.
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Installation Hardware Accessories 2. Carefully remove I/O board from CPU board by unplugging it from PMC connectors Finish Changing Signaling Level Start 1. Remove screw which fixes the voltage key to IO board Voltage Key Screw 2. Remove voltage key 3. Place voltage key into hole which corresponds to desired signalling level 5V 3.3V Note:aThe signaling levels of PMC slots 3 and 4 must be equal. Otherwise they are automatically set to 3.3V.
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Hardware Accessories Installation 4. Fix voltage key to I/O board by fastening screw Voltage Key Screw Finish Installing the PMC Module Start 1. Plug PMC module into desired PMC connectors of I/O board PMC#4 PMC#3 PMC#2 PMC Module Damage If the power consumption of the PMC module exceeds 7.5W, the board and the PMC module are damaged. Make sure that the total power consumption at +/−12V, 5V and 3.3V level does not exceed 7.5W. 2.
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Installation Hardware Accessories 4. Fasten screws Finish Reinstalling I/O Board Start 1. Plug I/O board onto PMC connectors of CPU board 2. Fix it by fastening the 14 screws which you previously have removed Finish Memory Modules The main memory capacity is adjustable via installation of a Force Computers memory module. Currently the SPARC/MEM−550 is available for the CPU−56T. It provides 1 GByte memory .
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Hardware Accessories Installation The actual memory module installation procedure is described in theaSPARC/MEM−550 Installation Guidea which is delivered together with the memory module.a Hard Disk A hard disk is available for the CPU board on request. It can be connected to the IDE1 interface which is accessible via an on−board connector.a Before installing the hard disk you have to remove the I/O board and afterwards you have to reinstall it.
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Installation Switch Settings Switch Settings Board Damage Setting/resetting the switches during operation causes board damage. Therefore, check and change switch settings before you install the board. 8G The CPU board provides four configuration switches: SW1, SW2, SW3 and SW4. 4 3 2 1 O N 8G SW4 O N 8G 4 3 2 1 O N 8G 4 3 2 1 4 3 2 1 O N Figure 3: Location of Switches on Board’s Top Side Table 7: Switch Settings 46 Switch No.
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Switch Settings Switch SW4 SPARC/CPU−56T Installation No. Description 2 Enable termination for SCSI 2 OFF (default): Termination enabled ON: Termination disabled 3 Enable termination for SCSI 3 (on I/O−board, if applicable) OFF (default): Termination enabled ON: Termination disabled 4 Reserved 1..
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Installation Board Installation Board Installation Board Damage Installing the board into a powered system may damage this and other boards in the system.a Only install the board into a non−powered system.a Backplane Configuration If the CPU board is plugged into slot 1 and configured accordingly with switch SW4 (refer to Switch Settings" table), the board acts as IACK daisy−chain driver. Plugged in any other slot, the board closes the IACKIN−IACKOUT path.
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Board Installation Installation Installing the CPU Board Procedure Start 1. Check system documentation for all important steps to be taken before switching off power 2. Take those steps 3. Switch off power 4. Plug board into system slot on left−hand sidea Note:aMake sure all other boards which are plugged into the system are to the right of the system board. 5. Fasten board with screws 6. Plug interface cables into front panel connectors, if applicable 7.
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Installation Board Installation 4. Remove interface cables, if applicable 5. Unfasten screwsa 6. Remove board Finish Powering Up We recommend to use a terminal when powering up the CPU board. The advantage of using a terminal is that you do not need any frame buffer, monitor, or keyboard for initial power up. Note:a S Before powering up, check the "Requirements" section for installation prerequisites and requirements.
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Board Installation Installation Installing Solaris The CPU board is designed to run with Solaris 8 2/02 or higher with the 64−bit kernel and with Solaris 9. Pay attention to the guidelines in this section before and during Solaris installation.a Note:aSolaris versions prior to version 8 2/2 are not supported. The CPU board runs with 64−bit kernel only.
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Installation Board Installation For audio I/O and IDE ATA 100 support, you have to install Solaris patches. The following table provides details.a Table 8: Solaris Patches Supported Device Solaris Version Patch Audio I/O (if applicable) 8 109896−17 or newer 9 Currently not supported. A patch will be available in the near future.
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Board Installation Installation Further information on these drivers is given in the following sections.a FRCgei The assignment of the driver’s instance number to an Intel 8254xEM GBit Ethernet device can be viewed by booting with the OpenBoot command boot −v. Each device is shown with the driver name and instance number during the Solaris boot up. The other way to obtain the instance number of the Ethernet devices is to look into the file /etc/path_to_inst.
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Installation Board Installation S Slave windows S Interrupts S DMA controller S VME arbiter S Mailboxes Additionally, the FRCvme package provides a common programming interface for application and driver development. For more detailed information and board−specific notes, refer to theaSolaris Driver Package Installation and Reference Guidea and theaSolaris VMEbus Driver Programmer’s Guide.a FRCflash The Solaris 2.x flash memory driver provides access to the flash memory device.
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Board Installation S Enables and triggers watchdog functions To enable the watchdog, set switch SW1−3 to ON S Increases the volume of a headphone (if applicable) Installation FRCplatmod This driver ensures proper error handling for IDE devices. It should be installed immediately after the Solaris installation has been completed.a If this driver is not installed, the system may send error messages or can panic in case of IDE error handling.
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3 Controls, Indicators, and Connectors Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Front Panel Controls, Indicators, and Connectors Front Panel The following figure shows the connectors, keys and LEDs available on the front panel of the CPU board.
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Controls, Indicators, and Connectors Front Panel LEDs All four LEDs available at the front panel are multi−purpose LEDs. Depending on the values contained in the LED control registers 1 to 4, they indicate either the board status or different network activities. Furthermore, all LEDs can be operated in user LED mode.aa For details about the LED control registers, refer to chapter Maps and Registers".
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Front Panel Controls, Indicators, and Connectors LED Description 3 VME Bus Activity (default) Red: Universe II asserted VME SYSFAIL signal to the VMEbus Green: Universe II accesses the VMEbus as master OFF: No SYSFAIL signal asserted and no Universe PCI−to−VME bridge activity Ethernet Activity Depending on LED control register 3 settings, the LED indicates activity of Ethernet interfaces 1 to 4 or a combination of these User−LED Mode Via LED control register 3, the LED can be programmed to be OFF, gree
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Controls, Indicators, and Connectors S Keyboard/Mouse S Ethernet S SCSI Front Panel Serial I/O Two serial RS−232 interfaces A and B are available via two Mini D−Sub 9 connectors. Their pinouts are given below.
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Front Panel 1 3 5 Controls, Indicators, and Connectors Mouse Data GND Mouse Clock 3 5 1 2 4 6 n.c. Vcc n.c. 2 4 6 Figure 9: PS/2 Mouse Connector Pinout Ethernet Ethernet 1 and 2 are available via two RJ−45 connectors. Ethernet 1 is of type 10/100BaseT and Ethernet 2 of type 10/100/1000BaseT. The respective pinouts are given below.
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Controls, Indicators, and Connectors 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 SCSIx_D12+ SCSIx_D13+ SCSIx_D14+ SCSIx_D15+ SCSIx_DP1+ SCSIx_D0+ SCSIx_D1+ SCSIx_D2+ SCSIx_D3+ SCSIx_D4+ SCSIx_D5+ SCSIx_D6+ SCSIx_D7+ SCSIx_DP0+ GND DIFFSENSE TERMPWR TERMPWR n.c.
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On−Board Connectors Controls, Indicators, and Connectors On−Board Connectors The following connectors are on−board: S PMC S Memory module S IDE S VME PMC The I/O board provides the following PMC connectors: PMC Connectors Corresponding PMC Slot Pn31 − Pn33 PMC #4 Pn21 − Pn24 PMC #3 Pn11 − Pn13 PMC #2 PMC#4 PMC#3 PMC#2 Figure 13: Location of PMC Connectors The connectors corresponding to PMC slots 2 and 4 are standard and are therefore not described in this guide.
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Controls, Indicators, and Connectors On−Board Connectors Pn24 2 64 1 63 PMC#3 It carries user I/O signals that are routed to the I/O board′ s IOBP. There they are available via an on−board PMC connector. For details, refer to theaSPARC/IOBP−IO−56 Installation Guide.a The pinout of Pn24 is given below.
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On−Board Connectors Controls, Indicators, and Connectors P8 P9 Figure 15: Location of Memory Module Connectors IDE The CPU board provides one IDE connector which provides access to IDE1.a IDE Connector 1 Its pinout is given below.
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Controls, Indicators, and Connectors 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 39 40 41 43 On−Board Connectors GND IDE1_D8 IDE1_D9 IDE1_D10 IDE1_D11 IDE1_D12 IDE1_D13 IDE1_D14 IDE1_D15 KEY GND GND GND IDE1_CSEL GND n.c. IDE1_CBLID# IDE1_A2 IDE1_CS1# GND 5V n.c.
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On−Board Connectors Controls, Indicators, and Connectors P2 carries the following Force Computers specific signals:a S 10/100Mbit Ethernet 3 (ETH3) S IDE (IDE2) S Parallel (PAR) S Serial (SERC, SERD) S USB 1 and 2 (USB1, USB2) S 10/100/1000 Mbit Ethernet 4 (ETH4) S Floppy (FDC) S USB 3 and 4 (USB3, USB4) S SUN or PS/2 keyboard/ mouse interface (KBD) S I2C (SMB) Figure 18: CPU Board P2 VMEbus Connector Pinout Rows Z − B SPARC/CPU−56T 67
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Controls, Indicators, and Connectors On−Board Connectors Figure 19: CPU Board P2 VMEbus Connector Pinout Rows C + D I/O Board P1 carries standard VME signals and is therefore not further described in this guide.
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On−Board Connectors Controls, Indicators, and Connectors Figure 20: I/O Board P2 VMEbus Connector Pinout Rows Z – B SPARC/CPU−56T 69
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Controls, Indicators, and Connectors On−Board Connectors Figure 21: I/O Board P2 VMEbus Connector Pinout Rows C + D 70 SPARC/CPU−56T
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4 Devices’ Features and Data Paths Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 UltraSPARC IIi+ Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 PCI Bus A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Real−Time Clock and NVRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Serial Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 PCI Bus C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Block Diagram Devices’ Features and Data Paths Block Diagram Figure 22: CPU Board Block Diagram SPARC/CPU−56T 73
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Devices’ Features and Data Paths Block Diagram Figure 23: I/O Board Block Diagram 74 SPARC/CPU−56T
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UltraSPARC IIi+ Processor Devices’ Features and Data Paths UltraSPARC IIi+ Processor The UltraSPARC IIi+ processor is based on the SPARC V9 architecture with VIS instruction set and supports up to 4 GByte of memory.
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Devices’ Features and Data Paths Interrupt Controller Interrupt Controller The UltraSPARC−IIi+ provides a 6−bit wide interrupt vector for 63 interrupt sources.a The UPA interrupt concentrator (UIC) provides the inputs for all necessary interrupts. It monitors all interrupts using a round−robin scheme with 33 MHz, converts them to a device−own vector and transmits this vector to the processor. The PCI interrupts engine (PIE) reflects every vector in one state bit.
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PCI Bus A Devices’ Features and Data Paths PCI Bus A PCI bus A is the primary PCI bus. It runs at 33 MHz and is 32 bit wide. The following devices are connected to it: S Ethernet controller S SCSI controller S SENTINEL64 PCI−to−PCI bridge S Universe Ethernet Controller The used Ethernet controller is an Intel 82540. It corresponds to Ethernet interface 2 available via the front panel and supports 10/100/1000BaseT Ethernet.
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Devices’ Features and Data Paths S Integral FIFOs for write posting to maximize bandwidth utilization S Programmable DMA controller with linked−list mode S CPU or peripheral boards functioning as both master and slave in the S Sustained transfer rates up to 60−70 Mbytes/s PCI Bus A Note:aWhen operating the board in system slot 1, the system clock is disabled while the board is in reset. This is a limitation of the Universe II device.
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PCI Bus B Devices’ Features and Data Paths PCI Bus B PCI bus B runs at 33 MHz and is 64 bit wide. It is the secondary PCI bus of the CPU board and has the following devices attached to it: S Ethernet controllera S Southbridge S PCIO−2 controller S PMC module Ethernet Controller The Ethernet controller used at PCI bus B is the same as is used at PCI bus A.a Southbridge The used Southbridge is an ALI M1535D+.
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Devices’ Features and Data Paths PCI Bus B Media Independent Interface Two on−board Intel LXT971 PHY devices are connected to the MII. They transform the MII into a 10/100BaseT Ethernet interface which is available either via front panel or via IOBP.
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EBus Devices’ Features and Data Paths EBus The EBus is a generic slave 8−bit wide Direct Memory Access (DMA) bus (pseudo ISA bus) to which the following devices are connected: S Field−Programmable Gate Array (FPGA) S PLCC PROM and flash memory device S Real time clock and NVRAM S Quad serial controller FPGA The used FPGA is a Spartan XCS20XL device made by XILINX.
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Devices’ Features and Data Paths EBus interrupt is generated is set to 1.25s. Once the watchdog timer is running, it is only possible to reduce the watchdog run out time.a Timer The FPGA contains two timers which can be used as two independent 16−bit count−down timers with a timer interval of 10 µs and a maximum run−out time of 655.35 ms. Two independent interrupts are possible which can be enabled or disabled with the Interrupt Enable Control register.
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EBus Devices’ Features and Data Paths Ethernet Interface 1/3 Switching As mentioned earlier in this guide, Ethernet interface 1 is available via front panel and Ethernet interface 3 via the CPU board′s IOBP. Only one of both interfaces can be active at the same time.a The selection which interface is active is made at board reset by the FPGA′s internal logic. It depends on the Miscellaneous Control Register bits 5 to 7 and on which Ethernet interface provides a link.
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Devices’ Features and Data Paths EBus Reset Source Description Power−up reset If one or more on−board voltages are not within their thresholds, a reset is issued PMC reset A PMC module in non−monarch mode can reset the CPU board PLCC PROM and Flash Memory Device The following memory devices are connected to the EBus: S One PLCC PROM with 1 MByte address spacea S One flash memory device with 16 MByte address space The PLCC PROM is the device from which the CPU board boots by default.
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EBus Devices’ Features and Data Paths The device offers the following features: S Four independent full−duplex serial channels S Four independent baud rate generators S Hardware handshake support (RTS/CTS/DTR/DTS/RI/DCD) S Interrupt controlled Interface 1 and 2 are available on the front panel via two micro DSub connectors. The interfaces 3 and 4 are routed to the SPARC/IOBP−CPU−56 via the P2 connector.
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Devices’ Features and Data Paths PCI Bus C PCI Bus C PCI Bus C has the following devices attached to it: S SENTINEL64 PCI−To−PCI bridge S PMC#2 (PMC slot 3) providing 64 bit/66 MHz S PMC#3 (PMC slot 4) providing 64 bit/66 MHz S SCSI device Ultra 160−LVD supporting 64 bit/66 MHz The data width provided by PCI bus C is 64 bit. The bus speed depends on the PMC modules installed into slot 3 and 4. If no PMC modules are installed or only PMC modules which support 66 MHz, the bus speed is 66 MHz.
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5 OpenBoot Firmware Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 CORE Workflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 CORE Commands . . . .
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OpenBoot Firmware Introduction Introduction The OpenBoot firmware consists of the Common Operations and Reset Environment (CORE), the power−on selftest (POST), the OpenBoot Diagnostics (OBDIAG), and the OpenBoot itself as well as support for the VxWorks real−time operating system (RTOS). The OpenBoot firmware is subject to changes. For the newest version and how to upgrade, refer to the SMART service accessible via the Force Computers World Wide Web site (www.forcecomputers.com).
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Introduction OpenBoot Firmware Additionally, CORE is designed to reach the following goals: S Ability to use I/O devices including serial port, flash, floppy, and net early on the cold boot sequence of a firmware client.a S Basic system tests that can replace existing POST in min. mode. S System testing may be done using the POST drop−in in max. mode.
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OpenBoot Firmware Introduction CORE Commands In order to change or interrupt the boot process in CORE, the following commands can be executed: S Skip POST: +
S Enter user interface: +a S User default NVRAM variables for this run: +a S Turn−on messages (if is set to true): +a POST At hardware power−on or button power−on, the CORE firmware executes POST if the NVRAM configuration parameter was set to true beforehand.
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Introduction OpenBoot Firmware boot <−bootoption> Optional Boot Parameters Table 13: Boot Parameters Parameter Description Name (full path or alias) of the boot device. Typical values are cdrom, disk, floppy, net or tape. Name of program to be booted The filename parameter is relative to the root of the selected device. If no filename is specified, the boot command uses the value of the boot file NVRAM parameter.
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OpenBoot Firmware 92 Introduction Alias SCSI Devicea SCSI Interface diskc Disk SCSI−target−ID c 1 diskb Disk SCSI−target−ID b 1 diska Disk SCSI−target−ID a 1 disk9 Disk SCSI−target−ID 9 1 disk8 Disk SCSI−target−ID 8 1 disk7 Disk SCSI−target−ID 7 1 disk6 Disk SCSI−target−ID 6 1 disk5 Disk SCSI−target−ID 5 1 disk4 Disk SCSI−target−ID 4 1 disk3 Disk SCSI−target−ID 3 1 disk2 Disk SCSI−target−ID 2 1 disk1 Disk SCSI−target−ID 1 1 disk0 Disk SCSI−target−ID 0 1 tape (or
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Introduction OpenBoot Firmware Alias SCSI Devicea SCSI Interface disk24 Disk SCSI−target−ID 4 2 disk23 Disk SCSI−target−ID 3 2 disk22 Disk SCSI−target−ID 2 2 disk21 Disk SCSI−target−ID 1 2 disk20 Disk SCSI−target−ID 0 2 tape−2 (or tape20)a First tape drive SCSI−target−ID 4 2 tape21 Second tape drive SCSI−target−ID 5 2 cdrom−2 CD−ROM partition f, SCSI−target−ID 6 2 The following table lists device aliases available for other devices.
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OpenBoot Firmware Introduction Alias Device ttyb Serial interface B tyyc Serial interface C tyyd Serial interface D vme VME OBDIAG OBDIAG stands for OpenBoot Diagnostics and is an additional diagnostics drop−in driver program which serves as an NVRAM configuration feature.a It allows to test the hardware by calling OBDIAG when the OpenBoot firmware is present and the prompt has appeared.
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Introduction OpenBoot Firmware When OBDIAG is called, the test prompt appears and you can now choose the required test. You can run single tests, a number of tests, all tests, or all tests with exceptions. If the test has passed successfully, a short test comment will appear on screen. In order to return to the main menu, hit the enter key. Terminating OBDIAG In order to terminate OBDIAG and return to OpenBoot, entera exit The OpenBoot prompt will then reappear.
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OpenBoot Firmware Introduction obdiag>asetenv diag−verbosity 2aa diag−verbosity =aaaaaa2 aa Hit any key to return to the main menua aa obdiag>asetenv diag−continue? 0 diag−continue? =aaaaaa0 aa Hit any key to return to the main menuaa aa obdiag>atest 2 Hit the spacebar to interrupt testing Testing /pci@1f,0/ebus@1a SUBTEST: vendor−id−test SUBTEST: device−id−test SUBTEST: mixmode−read SUBTEST: e2−class−test SUBTEST: status−reg−walk1 SUBTEST: line−size−walk1 SUBTEST: latency−walk1 SUBTEST: line−walk
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NVRAM Boot Parameters OpenBoot Firmware NVRAM Boot Parameters The OpenBoot firmware holds its configuration parameters in NVRAM. To see a list of all available configuration parameters, enter at the Forth Monitor prompt:aprintenv As you can see in the list, the default setting is for the CPU board to boot the operating system automatically. If this is not the case, ensure that the parameter is set to true.
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OpenBoot Firmware Diagnostics Diagnostics The Forth Monitor includes several diagnostic routines. These on−board tests let you check devices such as network controller, SCSI devices, floppy disk system, memory, clock, keyboard and audio. User−installed devices can be tested if their firmware includes a self−test routine. The table below lists several diagnostic routines.
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Diagnostics OpenBoot Firmware probe−scsi−all The actual response depends on the devices on the SCSI buses. Note:aA terminal message as answer to the command probe−scsi−all can take up to two minutes. okaprobe−scsi−all /pci@1f,0/scsi@2 aa Target 6 Unit 0 Disk Removable Read Only Device SONY CD−ROM CDU−8012 3.1a aa /pci@1f/pci@4,1/scsi@2 aa Target 3 Unit 0 Disk FUJITSU M2952ESP SUN2.
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OpenBoot Firmware Diagnostics The system responds by incrementing a number every second. Press any key to stop the test. Network To monitor the network connection enter: okawatch−net Internal loopback test −− succeeded. Transceiver check −− Using Onboard transceiver −− Link Up. passed Using Onboard transceiver −− Link Up. Looking for Ethernet packets. ‘.’ is a good packet. ‘X’ is a bad packet. Type any key to stop. ...........X...........................X..............
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Displaying System Information OpenBoot Firmware Displaying System Information The Forth Monitor provides several commands to display system information such as the system banner, the Ethernet address for the Ethernet controller, the contents of the ID PROM, and the version number of the OpenBoot firmware.
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OpenBoot Firmware Displaying System Information Table 19: Commands to Display System Information 102 Command Description banner Displays system banner .enet−addr Displays the Ethernet address. .idprom Displays ID PROM contents, formatted .traps Displays a list of SPARC trap types .
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Resetting the System OpenBoot Firmware Resetting the System If your system needs to be reset, there are two possibilities: S Software reset For this type of reset, use the command reset at the Forth command line. S Button power−on reset In both cases the system begins with the initialization procedures. If the system is reset via a button power−on reset, the power−on self test is executed before the initialization if the NVRAM configuration variable is set true.
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OpenBoot Firmware Activating OpenBoot Help Activating OpenBoot Help The Forth Monitor contains an online help which can be activated by entering the command help. Entering help creates the following screen output.
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Activating OpenBoot Help l@ w@ c@ x! l! w! c! ok ( ( ( ( ( ( ( addr −− n addr −− n addr −− n n addr −− n addr −− n addr −− n addr −− SPARC/CPU−56T OpenBoot Firmware ) ) ) ) ) ) ) place place place store store store store on the stack the 32−bit data at location addra on the stack the 16−bit data at location addra on the stack the 8−bit data at location addra the 64−bit value n at location addra the 32−bit value n at location addra the 16−bit value n at location addra the 8−bit value n at location ad
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6 Maps and Registers Interrupt Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Physical Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 UltraSPARC−IIi+ Physical Address Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Interrupt Enable Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Interrupt Pending Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Board Status Registers . . . . . . . . . . . . .
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Maps and Registers Interrupt Map Interrupt Map The following table lists all interrupt sources, their vectors from the UIC to the PIE, their vectors from the PIE to the processor’s execution unit and the respective priority.
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Interrupt Map Maps and Registers Interrupt Source RIC Vector CPU Internal Vector Offset Priority PMC4 D 0916 7D716 1716 1 PS/2 keyboard 2B16 7E916 2916 4 PS/2 mouse 2C16 7EA16 2A16 4 SCSI interface 1 2016 7E016 2016 3 SCSI interface 2 1416 7D916 1916 4 SCSI interface 3 0D16 7C516 0516 5 Serial interface 1 2D16 7EB16 2B16 7 Serial interface 2 0416 7D116 1116 4 Serial interface 3 0A16 7C716 0716 2 Serial interface 4 0116 7D316 1316 1 SUN keyboard 1016
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Maps and Registers Physical Memory Map Physical Memory Map The UltraSPARC−IIi+ has a 41−bit wide physical address range. This address range is divided into some specified areas for e.g. the main memory or the PCI bus.a Each area is subdivided into other areas, e.g. the main memory area is subdivided into the different memory module areas with the memory banks. Some areas are subdivided further down to one register with one byte, i.e. the System Control registers in the EBus area are byte−oriented.
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Physical Memory Map Maps and Registers Physical Address Range PA<41..0> Size Bank Memory Location DIMM Type 001.0000.0000 16aa − 001.0FFF.FFFF16 256 MByte 4 SPARC/MEM−550 DIMM 2 001.1000.0000 16aa − 001.1FFF.FFFF16 256 MByte 5 aa aa 001.8000.0000 16a− 001.8FFF.FFFF16 256 MByte 6 aa DIMM 3 001.9000.0000 16a− 001.9FFF.
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Maps and Registers Physical Memory Map The PCI device PCIO, part of the UltraSPARC−IIi+ chip set, must be available at power up for booting and has a fixed PCI address space. It has an interface to the EBus, where the boot PROM is located. Additionally, it has an interface to the MII bus from where the twisted−pair Ethernet interfaces are generated.a Table 23: PCI Bus Address Map Address Range in PA<40:0> Size Description 1FE.0100.0100 16− 1FE.01FF.
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Physical Memory Map Maps and Registers Address Range in PA<40:0> Size EBus CS# Description 1FF.F010.000016a − 1FF.F0FF.FFFF16 15 MByte 0 User flash memory on the EBus (if SW1−1 is ON or if bit 0 of the Miscellaneous Control register is set to 1) 1FF.F100.600016a − 1FF.F100.7FFF16 8 KByte 1 RTC/NVRAM on the EBus 1FF.F110.000016a − 1FF.F11F.FFFF16 1 MByte 2 PLCC PROM mirror area (independent of SW2−1 and bit 0 of the Miscellaneous Control register) 1FF.F130.010016a − 1FF.F130.
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Maps and Registers System Configuration Registers System Configuration Registers The CPU board implements a set of system configuration registers via the field−programmable gate array (FPGA), which is accessible via the EBus. The CPU Board System Configuration registers are used to control the on−board functions and to receive status information of the board. It is subdivided into 16 areas with 16 Bytes, each provided with a special function or reserved for future use.
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System Configuration Registers Maps and Registers Address Range in PA<40:0> Size Access Default Description 1FF.F160.014816 1 Byte r/w 0016 Timer 1 Init Control register U 1FF.F160.014916 1 Byte r/w 0016 Timer 1 Init Control register L 1FF.F160.014A16 1 Byte r/w 0016 Timer 2 Init Control register U 1FF.F160.014B16 1 Byte r/w 0016 Timer 2 Init Control register L 1FF.F160.014C16 1 Byte r 0016 Timer 1 Counter Status register U 1FF.F160.
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Maps and Registers System Configuration Registers Address: 1FF.F160.010016 Table 26: Miscellaneous Control Register 116 Bit Name Description Default Access 0 TSOP EN Used to switch between PLCC PROM access and flash memory access in the address space for CS0#. After reset, this bit is cleared (0).a 0: If SW1−2 is OFF, the PLCC PROM is available in the CS0# address space. If SW1−2 is ON the flash memory is available in the CS0# address space.
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System Configuration Registers Maps and Registers Bit Name Description Default Access 6 ETH3 EN Status of Ethernet interface 3 0: Disableda 1: Enableda 02 r 7 Reserved Always zero 02 r User LED Control Registers The following registers control front panel LED related features.a LED Control Register 1 This register is used to switch between the different operation modes of LED 1. Address: 1FF.F160.011016 Table 27: LED Control Register 1 Bit Name Description Default Access 4..
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Maps and Registers System Configuration Registers LED Control Register 2 This register is used to switch between the different operation modes of LED 2. Address: 1FF.F160.011016 Table 28: LED Control Register 2 Bit Name Description Default Access 4..
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System Configuration Registers Maps and Registers Address: 1FF.F160.011216 Table 29: LED Control Register 3 Bit Name Description Default 4..0 LED_DISPLAY VME activity 000002 000002: Red: Universe II asserted VME SYSFAIL signal to the VMEbus.
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Maps and Registers System Configuration Registers Address: 1FF.F160.011316 Table 30: LED Control Register 4 Bit Name Description Default Access 4..
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System Configuration Registers Maps and Registers Bit Name Description Default Access 5..3 0 Reserved 0002 r 6 STAT ACFAIL This bit reflects the state of the VMEbus low active ACFAIL signal, i.e. whether a failure of the power supply occurred. 0: The ACFAIL# signal is inactive (high). 1: The ACFAIL# signal is active (low). 02 r 7 STAT SYSFAIL This bit reflects the state of the VMEbus low active SYSFAIL signal, i.e. whether a failure of the power supply occurred.
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Maps and Registers System Configuration Registers Address: 1FF.F160.013016 Table 32: Watchdog Timer Control Register Bit Name Description Default Access 4..0 WDOG LENGTH These bits are used to set the time−out for the watchdog timer. The tolerance of the time delay is 100ppm or +10 ms/−10 ms whichever is greater.
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System Configuration Registers Maps and Registers Watchdog Timer Status Register The Watchdog Timer Status register reflects the watchdog timer status. Address: 1FF.F160.013416 Table 34: Watchdog Timer Status Register Bit Name Description Default Access 0 STAT WDOG This bit reflects the status of the watchdog timer.a 0: The watchdog timer has not reached the interrupt time.a 1: The watchdog timer has exceeded the interrupt time. It is necessary to trigger the watchdog timer. 02 r 7..
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Maps and Registers System Configuration Registers Address: 1FF.F160.014016 Table 35: Timer Control Register Bit Name Description Default Access 0 EN TIM1 Controls timer 1 0: Timer disabled 1: Timer enabled 02 r/w 1 EN MOD32 Switches between two 16−bit−wide timers and one 32−bit−wide timer 0: 16−bit mode enabled 1: 32−bit mode enabled 02 r/w 2..3 − Reserveda 002 r 4 EN TIM2 Controls timer 2 0: Timer disabled 1: Timer enabled 02 r/w 7..
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System Configuration Registers Maps and Registers Address: 1FF.F160.014416 Table 37: Timer Status Register Bit Name Description Default Access 0 STAT TIM1 Indicates an underrun of timer 1. This can only occur if timer 1 is enabled and the initial value is greater than 0.a 0: No underrun of timer 1 has occurred. 1: An underrun of timer 1 has occurred. 02 r 1 ERR TIM1 Indicates that more than one timer underruns without clearance have occurred.
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Maps and Registers System Configuration Registers Address: 1FF.F160.014816 − 1FF.F160.014B16 Table 38: Timer Initial Control Registers Bit Name Description Default Access 15..0 TIMER2 INIT Initialization time of timer 2 in 16−bit mode 000016: Timer disabled 000116: Timer run−out time is 10 µs FFFF16: Timer run−out time is 655.35 ms 000016 r/w 31..
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System Configuration Registers Maps and Registers Address: 1FF.F160.014C16 − 1FF.F160.014F16 Table 39: Timer Counter Status Register Bit Name Description Default Access 15..0 TIMER2 VALUE Current value of timer 2 in 16−bit mode 000016: Timer 2 is not running. 000116: Timer 2 will initialize again during the next 10 µs. 7FFF16: Timer 2 needs 327.67 ms until next initialization. FFFF16: Timer 2 needs 655.35 ms until next initialization. 000016 r 31..
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Maps and Registers System Configuration Registers Address: 1FF.F160.018016 Table 40: Interrupt Enable Control Register Bit Name Description Default Access 0 IE_WDT Enables the watchdog timer interrupt.a 0: Watchdog timer interrupt is disabled. 1: Watchdog timer interrupt is enabled. 02 r/w 1 Reserved This bit is always zero. 02 r/w 2 IE_TEMP Enables the Temperature Interrupt.a 0: Temperature interrupt is disabled. 1: Temperature interrupt is enabled.
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System Configuration Registers Maps and Registers Bit Name Description Default Access 2 IP_TEMP Reflects if a temperature interrupt is pending 0: No temperature interrupt is pending. The temperature senors did not detect a temperature that exceeds the actual limit.a 1: The temperature interrupt is pending. The temperature sensor has detected a temperature above the actual limit.
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Maps and Registers System Configuration Registers Bit Name Description Default Access 2 RST WD Reflects whether the last reset has been generated through a watchdog timer time−out condition 0: No watchdog timer reset has been triggered. 1: The watchdog timer reset has been triggered. 02 r 3 RST RTB Reflects whether the last reset has been generated through a push−button reset on the board′s IOBP 0: No push−button reset from the CPU board′s IOBP has been triggered.
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System Configuration Registers Maps and Registers Bit Name Switch Setting/Functionality Default Access 3 SW1−4 Reset/Abort key enabling 0: ON (Reset/Abort key disabled) 1: OFF (Reset/Abort key enabled) 12 r 4 SW2−1 User−defined Switch 0: ON 1: OFF 12 r 5 SW2−2 User−defined Switch 0: ON 1: OFF 12 r 6 SW2−3 User−defined switch 0: ON 1: OFF 12 r 7 SW2−4 User−defined switch 0: ON 1: OFF 12 r Switch 3 and 4 Status Register This register is used to read the switch settings of switc
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Maps and Registers System Configuration Registers Bit Name Switch Setting/Functionality Default Access 5 ..
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System Configuration Registers Maps and Registers Bit Name Description Default Access 5 PMC3/4 VIO This bit is set to 1 if the PMC modules 3 and 4 are configured with a VI/O of 5V (if applicable) 0: PMC3/4 have a VI/O of 3.3V 1: PMC3/4 have a VI/O of 5V 02 r 6 FKBD/MSE−PRE SENT This bit shows which type of keyboard/mouse is plugged into the front connector. 0: No SUN style keyboard/mouse or a PS/2 style keyboard/mouse is plugged into the front connector.
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Maps and Registers System Configuration Registers Address: 1FF.F160.01EF16 Table 47: Hardware Revision Register Bit Name Description Access 7..0 HW REVISION Status of the Board 0016: PCB revision: 1.0 and FPGA revision: 016 0116: PCB revision: 1.0 and FPGA revision: 116 0216: PCB revision: 1.0 and FPGA revision: 216 1016: PCB revision: 1.1 and FPGA revision: 1016 1116: PCB revision: 1.1 and FPGA revision: 1116 1216: PCB revision 1.
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System Configuration Registers Maps and Registers Address: 1FF.F160.01FF16 Table 49: I2C 2 Register Bit Name Description Defaulta Access 0 I2C−DATAIN2 This register bit reflects the current status of the I2C−2 data line. 0: I2C−2 dataline is 0. 1: I2C−2 dataline is 1. − r 1 I2C−CLK2 This bit corresponds to the I2C clock line and must be set by software to toggle the I2C clock. 0: I2C−2 clock is 0. 1: I2C−2 clock is 1.
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A Troubleshooting 136 SPARC/CPU−56T
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Error List Troubleshooting Error List A typical VMEbus system is highly sophisticated. This chapter can be taken as an error list for detecting erroneous system configurations and strange behaviors. It cannot replace a serious and sophisticated presales and postsales support during application development. If it is not possible to fix a problem with the help of this chapter, contact your local sales representative or Field Application Engineer (FAE) for further support.
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Troubleshooting 138 Error List Problem Possible Reason Solution Board does not boot Wrong boot devicea Check the OpenBoot property boot−device. This property must be set to the device (disk, net, cdrom) from which you want to boot. Use the commands probe−scsi and probe−ide to examine the system for boot devices SCSI bus not terminateda Check the SCSI cable for proper termination. Check also switch SW−3 of the board for correct SCSI bus termination.
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B Battery Exchange SPARC/CPU−56T 139
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Battery Exchange Battery Exchange Battery Exchange The battery provides data retention of seven years summing up all periods of actual data use. Force Computers therefore assumes that there usually is no need to exchange the battery except, for example, in case of long−term spare part handling. S Board/System damage Incorrect exchange of lithium batteries can result in a hazardous explosion. Therefore, exchange the battery as described in this chapter.
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Battery Exchange Battery Exchange 4. Install battery in such a way that the dot marked on top of battery covers dot marked on chip.a 5.
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Index A Aborting the board . . . . . . . . . . . . . . . . . . . . . . 59 B banner . . . . . . . . . . . . Board register overview Boot parameters . . . . . . . . . . . . . . . . . . . . . . . 101 . . . . . . . . . . . . . . . . . . 114 . . . . . . . . . . . . . . . . . . . 97 C CPU features . . . . . . . . . . . . . . . . . . . . . . . . . . 75 D devalias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 E exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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I2C Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 L LED stati . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 M Memory modules . . . . . . . . . . . . . . . . . . . . . . . 44 O OBDIAG . . . . . . . . . . . . . OpenBoot Device aliases . . . . . . . . . . . . . . . . . 94 . . . . . . . . . . . . . . . . . 91 P PMC modules . . . . . . . . . Primary PCI bus . . . . . . . printenvs . . . . . . . . . . . . probe−ide . . . . . . . . . . . . probe−ide−all . . . . . . . . .
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watch−net 144 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Product Error Report Product: Serial No.: Date Of Purchase: Originator: Company: Point Of Contact: Tel.: Ext.