Datasheet
PD243X, PD353X, PD443X
2006-01-23 6
Timing Characteristics—Data “Write” Cycle
Notes:
1. Wait 1.0 µs between any Reads or Writes after writing a Control
Word with a Clear (D7=1). Wait 1.0 µs between any Reads or
Writes after Clearing a Control Word with a Clear (D7=0). All
other Reads and Writes can be back to back.
2. All input voltages are V
IL
=0.8 V, V
IH
=2.0 V.
Timing Characteristics—Data “Read” Cycle
3. These waveforms are not edge triggered.
4. Data out voltages are measured with 100 pF on the data bus
and the ability to source = –40 mA and sink=1.6 mA The rise and
fall times are 60 ns. V
OL
=0.4 V, V
OH
=2.4 V.
Switching Specifications (V
CC
=4.5 V)
Write Cycle Timing
Para-
meter
Description Specification Minimum
–40°C 25°C 85°C Units
T
CLR
(1)
Clear RAM 1.0 1.0 1.0 µs
T
CLRD
(1)
Clear RAM Disable 1.0 1.0 1.0 µs
T
AS
Address Setup 10 10 10 ns
T
CES
Chip Enable Setup 0 0 0 ns
T
RS
Read Enable Setup 10 10 10 ns
T
DS
Data Setup 20 30 50 ns
T
W
Write Pulse 60 70 90 ns
T
AH
Address Hold 20 30 40 ns
T
DH
Data Hold 20 30 40 ns
T
CEH
Chip Enable Hold 0 0 0 ns
T
RH
Read Enable Hold 20 30 40 ns
T
ACC
Total Access
Time = Setup
Time + Write
Time + Hold Time
90 110 140 ns
T
DS
T
DH
T
W
T
ACC
T
AH
T
AS
T
CEH
T
CES
2.0 V
0.8 V
CE0, CE1
A0, A1
RD
2.0 V
0.8 V
2.0 V
0.8 V
2.0 V
0.8 V
D0–D6
2.0 V
0.8 V
T
RS
T
RH
WR
*
*
*
*
*
Switching Specifications (V
CC
=4.5 V)
Read Cycle Timing
Para-
meter
Description Specification Minimum
–40°C 25°C 85°C Units
T
AS
Address Setup 0 0 0 ns
T
CES
Chip Enable 0 0 0 ns
T
WS
Write Enable Setup 20 30 40 ns
T
DD
Data Delay Time 100 150 175 ns
T
R
Read Pulse 150 175 200 ns
T
AH
Address Hold 0 0 0 ns
T
DH
Data Hold 0 0 0 ns
T
TRI
Time to Tristate
(Max. time)
30 40 50 ns
T
CEH
Chip Enable Hold 0 0 0 ns
T
WH
Write Enable Hold 30 40 50 ns
T
ACC
Total Access
Time = Setup
Time + Read
Time + Time to
Tristate
200 245 290 ns
T
WAIT
(1)
Wait Time between
Reads
0 0 0 ns
T
DD
T
R
T
AH
T
AS
T
CEH
T
CES
2.0 V
0.8 V
CE0, CE1
A0–A3
T
RACC
2.0 V
0.8 V
2.0 V
0.8 V
2.0 V
0.8 V
D0–D6
2.0 V
0.8 V
T
WS
T
WH
WR
RD
T
DH
T
RI
*
*
*
*
DATA OUT
*