Datasheet

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A
2008-07-22 5
Input/Output Circuits
Figures „Inputs“ and „Clock I/O“ show the input and output resis-
tor/diode networks used for ESD protection and to eliminate sub-
strate latch-up caused by input voltage over/under shoot.
Inputs
Top View
Clock I/O
Electrical Characteristics (over operating temperature)
Parameter Min. Typ. Max. Units Conditions
V
CC
4.5 5.0 5.5 V —
I
CC
(Pwr Dwn Mode)
(4)
— 50 — μA V
CC
=5.0 V, all inputs=0 V or V
CC
I
CC
10 digits 16 dots/character — 250 365 mA V
CC
=5.0 V, “#” displayed in all 10 digits
at 100% brightness at 25°C
I
IL
Input current — — –10 μA V
CC
=5.0 V, V
IN
=0 V (all inputs)
I
IH
Input current — — 10 μA V
CC
=V
IN
=5.0 V (all inputs)
V
IH
3.5 — — V V
CC
=4.5 V to 5.5 V
V
IL
— — 1.5 V V
CC
=4.5 V to 5.5 V
I
OH
(CLK I/O) — –8.9 — mA V
CC
=4.5 V, V
OH
=2.4 V
I
OL
(CLK I/O) — 1.6 — mA V
CC
=4.5 V, V
OL
=0.4 V
θ
JA
— — 31 °C/W —
F
ext
External Clock Input Frequency 120 — 347 kHz V
CC
=5.0 V, CLKSEL=0
F
osc
Internal Clock Input Frequency 120 — 347 kHz V
CC
=5.0 V, CLKSEL=1
Clock I/O Bus Loading — — 240 pF —
Clock Out Rise Time — — 500 ns V
CC
=4.5 V, V
OH
=2.4 V
Clock Out Fall Time — — 500 ns V
CC
=4.5 V, V
OH
=0.4 V
FM, Digit 375 768 1086 Hz —
Notes:
1)
Peak current
5
/3 x I
CC.
2)
Unused inputs must be tied high.
3)
Contact Infineon for 3.3 V operation.
4)
External oscillator must be stopped if being used to maintain an I
CC
<50 μA.
IDCD5021
GND
1 k
Ω Input
CC
V
114
28 15
IDPA5117
IDCD5026
GND
1 k
ΩInput/Output
CC
V