Datasheet
SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A
2008-07-22 6
Dot Matrix Format mm (inch)
Pin Assignment
Pin Function Pin Function
1 SDCLK 28 GND
2 LOAD 27 DATA
3 NP 26 NP
4 NP 25 NP
5 NP 24 NP
6 NP 23 NP
7 NP 22 NP
8 NP 21 NP
9 NP 20 NP
10 NP 19 V
CC
11 NP 18 NC
12 NP 17 NP
13 RST 16 CLKSEL
14 GND 15 CLK I/O
Switching Specifications
(over operating temperature range and V
CC
=4.5 V to 5.5 V)
Symbol Description Min. Units
T
RC
Reset Active Time 600 ns
T
LDS
Load Setup Time 50 ns
T
DS
Data Setup Time 50 ns
T
SDCLK
Clock Period 200 ns
T
SDCW
Clock Width 70 ns
T
LDH
Load Hold Time 0 ns
T
DH
Data Hold Time 25 ns
T
WR
Total Write Time 2.2 μs
T
BL
Time Between Loads 600 ns
Note: T
SDCW
is the minimum time the SDCLK may be low or high.
The SDCLK period must be a minimum of 200 ns.
IDOD5212
C0 C1 C2 C3 C4
R0
R1
R3
R4
R5
0.28 (0.011) typ. 0.84 (0.033) typ.
0.56 (0.022) typ.
3.68 (0.145)
2.03 (0.080)
Tolerance: ±0.25 (0.010)
Pin Definitions
Pin Function Definitions
1 SDCLK Loads data into the 8-bit serial data register
on a low to high transition.
2 LOAD Low input enables data clocking into 8-bit
serial shift register. When
LOAD goes high,
the contents of 8-bit serial Shift Register will
be decoded.
3 NP No Pin
4 NP No Pin
5 NP No Pin
6 NP No Pin
7 NP No pin
8 NP No pin
9 NP No Pin
10 NP No Pin
11 NP No Pin
12 NP No Pin
13 RST Asynchronous input, when low will clear the
Multiplex Counter, User RAM and Data
Register. Control Word Register is set to
100% brightness and the Address Register is
set to select Digit 0. The display is blanked.
14 GND Power supply ground
15 CLK I/O Outputs master clock or inputs external clock.
16 CLKSEL H=internal clock, L=external clock
17 NP No Pin
18 NC No connection
19 V
CC
Power supply/heat sink
20 NP No Pin
21 NP No pin
22 NP No pin
23 NP No Pin
24 NP No Pin
25 NP No Pin
26 NP No Pin
27 DATA Serial data input
28 GND Power supply ground