Datasheet

SCE5780
2006-01-23 13
Display Interface to Siemens/Intel 8031
Microprocessor (using serial port in mode 0)
Display Interface to Siemens/Intel 8031
Microprocessor (using one bit of parallel port as serial
port)
Display Interface with Motorola 68HC05C4
Microprocessor (using SPI port)
Cascading Multiple Displays
Multiple displays can be cascaded using the CLKSEL and CLK I/O
pins (Figure „Cascading Multiple Display“). The display designated
as the MasterClock source should have its CLKSEL pin tied high
and the slaves should have their CLKSEL pins tied low. All CLK I/O
pins should be tied together. One display CLK I/O can drive 15
slave CLK I/Os. Use RST to synchronize all display counters.
IDCD5227
XTAL2 RxD
18 10
19
XTAL1
RST
9
17
P3.7
13
P3.3
P3.4
14
8031
U1
TxD
11
SDCLK
RST
LD
GND CLKSEL
CLK I/O
CC
V
DATA
GND
CC
V
40
ID
+
0.01 µF
TAN
22 µF
CC
V
V
CC
IDCD5228
XTAL2 P3.0
18 10
19
XTAL1
RST
1
8031
U1
SDCLK
RST
LD
GND CLKSEL
CLK I/O
CC
V
DATA
GND
CC
V
40
ID
+
0.01 µF
TAN
22 µF
CC
V
V
CC
P1.0
9
20
P3.1
11
P3.6
16
P0.0
39
IDCD5229
OSC1 PA0
38 11
39
OSC2
RST
1
68HC05C4
U1
SDCLK
RST
LD
GND CS
CLK I/O
CC
V
DATA
GND
CC
V
40
ID
+
0.01 µF
TAN
22 µF
CC
V
V
CC
PA2
9
20
PA1
10
SCLK
33
MOSI
32
IDCD5030
RST CLK SEL
Intelligent Display
CC
V
DATA SDCLK LOAD
14 more displays
in between
DATA
SDCLK
Decoder
Address
Address Decode 1-14
A0
A1
A3
RST
CLK I/O
Intelligent Display
DATA
RST
SDCLK
CLK I/O
LOAD
CLK SEL
Chip
0
15
A2
LD
CE