User Manual
Table Of Contents
- 1 General Device Overview
- 2 Basic Operating Information
- 3 PAN1322-SPP Interfaces
- 4 General Device Capabilities
- 5 Ordering Information
- 6 Bluetooth Capabilities
- 7 Electrical Characteristics
- 8 Package Information
- 9 Bluetooth Qualification and Regulatory Certification
- 9.1 Reference Design
- 9.2 FCC Class B Digital Devices Regulatory Notice
- 9.3 FCC Wireless Notice
- 9.4 FCC Interference Statement
- 9.5 FCC Identifier
- 9.6 European R&TTE Declaration of Conformity
- 9.7 Bluetooth Qualified Design ID
- 9.8 Industry Canada Certification
- 9.9 Label Design of the Host Product
- 9.10 Regulatory Test House
- 10 Assembly Guidelines
- 11 Terminology
- 12 References
User’s Manual 11 Revision 1.3, 2013-08-14
Hardware Description
PAN1322-SPP
ENW89841A3KF
General Device Overview
F4 P0.14 LPmin I/O VDDUART Z Z Port 0.14
LPM wakup input
F5 P0.7 /
UARTCTS
I/O/OD VDDUART Z Z Port 0.7 or
UART CTS flow control
F7 P0.4 /
UARTTXD
I/O/OD VDDUART PU PU Port 0.4 or
UART transmit data
F8 P0.6 /
UARTRTS
I/O/OD VDDUART PU PU Port 0.6 or
UART RTS flow control
A4,
A5,
A6
VSUPPLY SI - - Power supply
C1 VREG SO - - Regulated Power supply
F6 VDDUART SI - - UART interface Power supply
C5 VDD1 SI - - Power supply
A1,
A7,
A9,
A11,
A12,
C8,
C9,
D7,
D8,
E8,
E9,
F1,
F9
F11,
F12
VSS - - Ground
B6,
B7,
B8,
C6,
C7,
D6,
D9,
E7
NC - - - - No connection
1) Fixed pull-up/pull-down if JTAG interface is selected, not affected by any chip reset. If JTAG interface is not selected the
port is tristate.
Table 1 Pin Description
Pin
No.
Symbol Input /
Output
Supply Voltage During
Reset
After
Reset
Function