MICROCOMPUTER MN1030 MN103001G/F01K LSI User’s Manual Pub.No.
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Table of Contents/List of Figures and Tables 1. General Specifications 2. CPU 3. Extension Instruction Specifications 4. Memory Modes 5. Operating Mode 6. Clock Generator 7. Internal Memory 8. Bus Controller (BC) 9. Interrupt Controller 10. 8-bit Timers 11. 16-bit Timers 12. Watchdog Timer 13.
14. A/D Converter 15. I/O Ports 16. Internal Flash Memory 17.
Table of Contents/List of Figures and Tables 0
Table of Contents 1. General Specifications 1.1 Overview ........................................................................................................................ 1-2 1.2 Features .......................................................................................................................... 1-2 1.3 Block Diagram ............................................................................................................... 1-4 1.4 Pin Description .............................
5. Operating Mode 5.1 Overview ........................................................................................................................ 5-2 5.2 Reset Mode .................................................................................................................... 5-3 5.3 Low Power Mode ........................................................................................................... 5-4 6. Clock Generator 6.1 Overview ..................................................
8.13.2 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode ...................................................................... 8-35 8.13.3 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode ............................................................................................ 8-37 8.13.4 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode ........................................................... 8-39 8.13.
10.6 Description of Operation ............................................................................................ 10-20 10.6.1 Interval Timers and Timer Output ............................................................ 10-20 10.6.2 Event Counting ......................................................................................... 10-24 10.6.3 Cascaded Connection ................................................................................ 10-26 10.6.4 PWM Output ..................
13.4.2 Block Diagram of UART Serial Interface ................................................ 13-37 13.4.3 Description of Registers for the UART Serial Interface ........................... 13-38 13.4.4 Description of Operation ........................................................................... 13-45 14. A/D Converter 14.1 Overview ...................................................................................................................... 14-2 14.2 Features ......................
.9.3 15.10 15.11 15.12 15.13 15.14 15.15 Pin Configurations .................................................................................... 15-44 Port 8 .......................................................................................................................... 15-45 15.10.1 Block Diagram .......................................................................................... 15-45 15.10.2 Register Descriptions ................................................................
List of Figures and Tables List of Figures 1. 2. 3. 4. 5. General Specifications Fig. 1-3-1 MN103001G Block Diagram .................................................................................... 1-4 Fig. 1-4-1 Pin Assignments Diagram ......................................................................................... 1-5 CPU Fig. 2-2-1 CPU Core Block Diagram ......................................................................................... 2-3 Fig. 2-3-1 CPU Registers .........
Fig. 8-7-1 Address Format When Accessing External Memory .............................................. 8-26 Fig. 8-7-2 Space Partitioning .................................................................................................... 8-27 Fig. 8-12-1 Internal I/O Space Access ....................................................................................... 8-31 Fig.
Fig. 8-13-21 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2) ................ 8-49 Fig. 8-13-22 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK) ......................................... 8-50 Fig. 8-13-23 Access Timing on a 16-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4) ................ 8-51 Fig.
10. 8-bit Timers Fig. 10-3-1 8-bit Timer Block Diagram (Timers 0 to 3) ............................................................ 10-3 Fig. 10-3-2 8-bit Timer Block Diagram (Timers 4 to B) ........................................................... 10-4 Fig. 10-3-3 8-bit Timer Connection Diagram (Overall)............................................................. 10-5 Fig. 10-3-4 8-bit Timer Connection Diagram (Timer 0 to 3 block) ........................................... 10-6 Fig.
12. Watchdog Timer Fig. 12-3-1 Block Diagram ........................................................................................................ 12-3 Fig. 12-5-1 Operation Diagram 1: When Reset Is Released ...................................................... 12-7 Fig. 12-5-2 Operation Diagram 2: When Recovering from STOP Mode .................................. 12-8 Fig. 12-5-3 Operation Diagram 3: Watchdog Operation ........................................................... 12-9 13.
Fig. 14-5-2 External Trigger Input Conversion Example (for Channels 0 to 2, One Time Each)..................................................................... 14-8 Fig. 14-5-3 External Trigger Input Conversion Example .......................................................... 14-9 Fig. 14-5-4 External Trigger Input Conversion Example (for Channels 0 to 2, Continuous Conversion) ...................................................... 14-10 Fig. 14-5-5 Conversion Timing When Using Two Sampling Cycles .
17. Ordering Mask ROM Fig. 17-2-1 ROM Ordering Method 1 ........................................................................................ 17-2 Fig. 17-2-2 ROM Ordering Method 2 ........................................................................................ 17-3 Appendix Fig. C-1 Memory Connection Example................................................................... Appendix-11 Fig. E-1 Package Outline ...............................................................................
List of Tables 1. 2. 3. General Specifications Table 1-4-1 Pin Assignments ........................................................................................................ 1-6 Table 1-4-2 Pin Function Table (1/2)............................................................................................ 1-7 Table 1-4-2 Pin Function Table (2/2)............................................................................................ 1-8 CPU Table 2-3-1 List of Control Registers ..........
10. 8-bit Timers Table 10-4-1 List of 8-bit Timer Functions .................................................................................. 10-9 Table 10-5-1 List of 8-bit Timer Registers (1/2) ........................................................................ 10-10 Table 10-5-1 List of 8-bit Timer Registers (2/2) ........................................................................ 10-11 Table 10-5-2 PWM Output Waves ..............................................................................
Table 15-13-1Port B Configuration ............................................................................................. 15-60 Table 15-14-1Port C Configuration ............................................................................................. 15-63 Table 15-15-1Treatment of Unused Pins ..................................................................................... 15-64 16. Internal Flash Memory Table 16-4-1 Mode Settings through the External Pins ..................................
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1.
General Specifications 1.1 Overview The MN1030 Series is a 32-bit microcontroller that maintains the software assets of Matsushita Electronics' 16-bit MN102 Series of microcontrollers by offering ease of use and excellent cost-performance with a simple, highperformance architecture.
General Specifications High-speed/high-performance bus interface ■ Can select either separate address/data buses or multiplex address/data bus • Address: 24 bits/Data: 8/16 bits ■ External memory space can be partitioned into four blocks • Chip select signal output for each block • Blocks 2 to 3 can be switched between fixed wait insertion or handshaking • Blocks 0 to 3 can be switched between synchronous mode and asynchronous mode • Blocks 1 and 2 can be used as DRAM space ■ DRAM control circuit on chip •
General Specifications ■ Input ports: • 4 (all multipurpose) ■ Output ports: • 15 (all multipurpose) ■ Input/output ports: • 53 (all multipurpose) Flash microcontroller specifications ■ Performance identical to that of a mask ROM product guaranteed ■ Overwriting while on board possible through serial communications ■ Batch/block erase possible Block units 8 KB (multiple blocks can be selected simultaneously) Package • LQFP100-P-1414 1.
General Specifications 1.4 Pin Description 1.4.1 Pin Assignments 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P40/SBT0 P41/SBI0 P42/SBO0 VSS P43/SBT1/DCAS0 P44/SBI1/DCAS1 VDD P45/SBO1/DWE P50/SBT2/TM0IO P51/SBI2/TM1IO P52/SBO2/TM2IO P53/SBT3/TM3IO/TM11IO P54/SBI3/TM4IO/TM12IO P55/SBO3/TM5IO/TM13IO NMIRQ VSS P60/IRQ0/TM6IO P61/IRQ1/TM7IO P62/IRQ2/TM10IOA P63/IRQ3/ADTRG/TM10IOB P70/CS0 VDD P71/RAS1/CS1 P72/RAS2/CS2 P73/A23/CS3 The pin assignments are shown in Fig.
General Specifications Table 1-4-1 Pin Assignments Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
General Specifications 1.4.2 Pin Functions Table 1-4-2 shows the function of each pin of this microcontroller. Table 1-4-2 Pin Function Table (1/2) Category Power supply Clock Pin name Input/ Output VDD Number of pins 8 Pin Function Digital system power supply (+3.3 V) VSS 7 Digital system GND VDD2(VPP) 1 “VDD2” in the case of the MN103001G, “VPP” in the case of the MN1030F01K. Connect to 5 V or 3.3 V. Always input 5 V to VPP when writing. OSCI I 1 Oscillator input (use input of 3.
General Specifications Table 1-4-2 Pin Function Table (2/2) Category Pin name Input/ Output Number of pins Pin Function Reset RST I 1 Reset input Interrupts NMIRQ I 1 External non-maskable interrupt input IRQ7 to 0 I 8 External interrupt 7 to 0 inputs (multipurpose) SBI3 to 0 I 4 Serial 3 to 0 data inputs (multipurpose) SBO3 to 0 I/O 4 Serial 3 to 0 data inputs/outputs (multipurpose) (SBO3 is output only.
2.
CPU 2.
CPU 2.2 Block Diagram The block diagram for this microcontroller, focusing on the CPU, is shown below.
CPU 2.3 Programming Model 2.3.1 CPU Registers • The register set is divided into data registers that are used for arithmetic operations, etc., address registers that are used for pointers, and a stack pointer. This arrangement contributes greatly to the improved performance of the internal architecture, through reduction of instruction code size, improved parallelism in pipeline processing, etc. • This register enables programming in C and other high-level languages.
CPU ■ Data Register (32-bit x 4) This register can be used generally for all operations. Operations are performed with a 32-bit length and the data size is converted when sending data to and from the memory or by executing the EXTB or EXTH instructions. When loading data, 8-bit data is zero-extended to 32 bits and sent to the register. When storing data, the lower 8 bits of the register are sent to the memory.
CPU Z: Zero Flag This flag is set when an operation result is all zeroes, and is cleared by any other result. This flag is also cleared by a reset. N: Negative Flag This flag is set if the MSB of an operation result is "1", and is cleared if the MSB is "0". This flag is also cleared by a reset. C: Carry Flag This flag is set when a carry or borrow to or from the MSB is generated in the course of executing an operation, and is cleared if no carry or borrow is generated. This flag is also cleared by a reset.
CPU 2.3.2 Control Registers This microcontroller uses the memory-mapped-I/O method and allocates the peripheral circuit registers to the internal I/O space between addresses x'20000000 and x'3FFFFFFF. The registers listed below are described in this section. For details on other control registers, refer to the respective sections that explain the various internal peripheral functions.
CPU Interrupt Vector Register (IVARn) (n = 0, 1, 2, 3, 4, 5, 6) The interrupt vector register (IVAR0 to IVAR6) contains the lower 16 bits of the start address of the interrupt handler for interrupts of the level accepted by the CPU. IVAR0 corresponds to level 0 interrupts; in similar fashion, IVAR1 to IVAR6 correspond to levels 1 to 6, respectively. IVAR0 to IVAR6 are allocated to the internal I/O space between addresses x'20000000 to x'20000018, respectively. Bit No. Bit name Reset Access Bit No.
CPU CPU Mode Register (CPUM) The CPU mode register (CPUM) sets the clock operating mode for the CPU and peripheral blocks. This register is allocated to the internal I/O space at address x'20000040. Bit No. 15 14 13 12 11 10 9 8 7 6 Bit name — — — — — — — — — — Reset Access 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R/W R/W Bit No.
CPU 2.4 Instructions 2.4.1 Addressing Modes The 32-bit microcontroller is equipped with the following 6 addressing modes which are frequently used with compilers. All 6 addressing modes of register direct, immediate value, register indirect, register indirect with displacement, absolute and register indirect with index can be used with data transfer group instructions. The 2 addressing modes of register direct and immediate addressing can be used with register operation instructions.
CPU 2.4.2 Data Types Data types can be processed in the four types of bit, byte, halfword and word data. Byte data, halfword data and word data can be handled as signed and unsigned data. The sign bit is MSB. The data in the memory must be aligned data. In other words, the two bits on the LSB side of addresses containing word data must be "00" (addresses which are a multiple of 4), and the LSB of addresses containing halfword data must be "0" (addresses which are a multiple of 2).
CPU 2.4.3 Instruction Set The instruction set has a simple organization, and features the generation of compact and optimized code through a C compiler. The instruction code size is reduced by making the basic instruction word length one byte. As a result, increases in the code size of the assembler program can be kept to a minimum even though the instruction set is simple, with data transfers to and from memory limited to load and store operations.
CPU • Bit instructions BTST BSET BCLR Bit Test Test and set (processing unit: byte) Test and clear (processing unit: byte) ASR LSR ASL ASL2 ROR ROL Shift Right Arithmetic Shift Right Logical Shift Left Arithmetic Shift Left 2-bit Arithmetic Rotate 1 bit to the right Rotate 1 bit to the left Bcc Lcc SETLB JMP CALL CALLS RET RETF RETS RTI TRAP NOP Branch on condition codes (PC relative) Loop on condition codes (PC relative) Set loop buffer Unconditional branch (PC relative, register indirect) Subroutine
CPU 2.5 Interrupts 2.5.1 Overview of Interrupts The most important key to real-time control is the ability to shift quickly to interrupt handler processing. If an interrupt is generated during the execution of an instruction that requires multiple cycles for execution (multiplication or division instructions, for example), interrupt response is improved by aborting the execution of the instruction and immediately accepting the interrupt.
CPU 2.5.2 Registers [Flags in the PSW] (CPU) Interrupt-related flags in the processor status word (PSW) include interrupt enable and interrupt mask level. IE (Interrupt Enable) R/W • This flag allows all interrupts to be accepted except for non-maskable interrupts and reset interrupts. Interrupts are allowed when IE = 1. IE = 0 when the system is reset. • When an interrupt is accepted, IE is cleared (interrupt prohibited). Set IE when accepting nested interrupts within the interrupt handler.
CPU LV2 to LV0 (Interrupt Priority Level) R/W • This 3-bit field sets the interrupt priority level. When the interrupt priority level set in LV2 to LV0 is higher than the interrupt mask level set in IM2 to IM0 in the PSW (i.e., the value set in LV2 to LV0 is smaller than the value set in IM2 to IM0), interrupts in the corresponding interrupt group are enabled. All interrupts (max. 4) in the same interrupt group have the interrupt priority level specified by LV2 to LV0.
CPU [Interrupt Accept Group Register (IAGR)] R halfword/byte access During a register read, the interrupt accept group register (IAGR) indicates the smallest group number of the groups that are generating an interrupt of the interrupt levels accepted by the CPU, which are indicated by IM2 to IM0 of the PSW. This register is allocated to address x'34000200 in the internal I/O space. The GN4 to GN0 field (5 bits) corresponds to the interrupt group number.
CPU 2.5.3 Interrupt Types The three types of interrupts are listed below: [Reset interrupt] The reset interrupt is the interrupt with the highest priority level, and is generated by setting the RST pin to "L" level. As a result of the reset interrupt, the registers, etc., are initialized. When the RST pin goes to "H" level, the microcontroller waits until the oscillation of the internal clock stabilizes, and then begins executing program instructions starting from address x'40000000.
CPU [Level interrupts] Level interrupts are interrupts for which the interrupt level can be controlled through the interrupt enable (IE) and interrupt mask (IM2 to IM0) bits in the PSW. Level interrupts are interrupts from the interrupt group controllers external to the CPU (in other words, peripheral interrupts). There are 18 groups, or 35 interrupt factors.
CPU (Example of pre-processing by the interrupt handler) 1. The registers are saved. The saved registers are those used by the interrupt handler. 2. The interrupt group analysis is executed. 2.1 The interrupt acknowledge sequence is executed. Interrupt acknowledge consists of reading out the interrupt accept group register (IAGR) to obtain the group number of the interrupt group with the highest priority among the specified interrupt levels. 2.
CPU An even higher interrupt response speed can be realized by assigning only one factor or only a few factors to a single interrupt level. Fig. 2-5-6 shows the interrupt sequence flow when assigning one factor to each interrupt level. Program Processing for each factor are w ard g es Interrupt t up r max. 11 Cycles sin h by ter p c ro s cle 1 y 3C Handler (pre-processing) In Interrupt handler RT I 5 6 Handler (post-processing) Fig.
CPU [Stack Frame] When an interrupt is accepted, a stack frame is allocated and the total 6 bytes of information in the PC and PSW are saved in order to return from the interrupt. However, since the transfer of data across the 32-bit boundary is prohibited, the SP value must constantly be set to a multiple of 4. Accordingly, a stack frame is allocated as shown in Fig. 2-5-7 so that the SP value is constantly set to a multiple of 4. Ultimately, an 8-byte area with a total of 6 bytes of information is saved.
3.
Extension Instruction Specifications 3.1 Operation Extension Function The MN1030 series 32-bit microcontrollers are provided with 32 extension instructions which can be defined by users. This allows the desired processing to be performed at high speed for each model expansion by assigning multiply, multiply-accumulate, saturation and other application-oriented operations to extension instructions and connecting extension function unit via the extension operation interface of the CPU core.
Extension Instruction Specifications 3.2 Extension Instructions 3.2.1 Explanation of Notations The notations used to describe instruction manual are shown below. OP: Am, An: Dm, Dn: SP: imm: imm8: imm16: imm32: d8: d16: d32: abs16: abs32: MDR: MDRQ: LIR: LAR: PSW: PC: ( ): regs: 0x....
Extension Instruction Specifications 3.2.2 Extension Block Register Set The extension block has the following dedicated registers in which it stores the results of high-speed multiplication operations and multiply-and-accumulate operations. Bit 31 Bit 0 MDRQ Multiply Register Multiply & Accumulate Register (Higher) Bit 31 Multiply & Accumulate Register (Lower) Bit 31 Bit 0 MCRH Bit 0 MCRL Multiply & Accumulate Overflow Detect Flag Register Bit 0 MCVF Fig.
Extension Instruction Specifications 3.2.3 Extension Instruction Details PUTX (Register transfer instruction for high-speed multiplication: Load) [Instruction Format (Macro Name)] PUTX Dm [Assembler Mnemonic] udf20 Dm, Dm [Operation] The contents of Dm are transferred to the high-speed multiply register MDRQ. [Flag Changes] Flag Change V – C N – – Z – Condition [Programming Cautions] When "udf20 Dm, Dn" is operated, Dn is ignored.
Extension Instruction Specifications PUTCX (Register transfer instruction for multiply-and-accumulate operation: Load) [Instruction Format (Macro Name)] PUTCX Dm, Dn [Assembler Mnemonic] udf21 Dm, Dn [Operation] This instruction transfers the contents of Dm to the multiply-and-accumulate register MCRH. This instruction also transfers the contents of Dn to the multiply-and-accumulate register MCRL. The contents of the V flag are set in the multiply-and-accumulate overflow detect register MCVF.
Extension Instruction Specifications GETX (Register transfer instruction for high-speed multiplication: Store) [Instruction Format (Macro Name)] GETX Dn [Assembler Mnemonic] udf15 Dn, Dn [Operation] The contents of the high-speed multiply register MDRQ are transferred to Dn.
Extension Instruction Specifications GETCHX (Register high-order 32-bit transfer instruction for multiply-and-accumulate operation: Store) [Instruction Format (Macro Name)] GETCHX Dn [Assembler Mnemonic] udf12 Dn, Dn [Operation] This instruction transfers the contents of the multiply-and-accumulate register MCRH to Dn. The content of the multiply-and-accumulate overflow detect register MCVF is set in the V flag.
Extension Instruction Specifications GETCLX (Register low-order 32-bit transfer instruction for multiply-and-accumulate operation: Store) [Instruction Format (Macro Name)] GETCLX Dn [Assembler Mnemonic] udf13 Dn, Dn [Operation] This instruction transfers the contents of the multiply-and-accumulate register MCRL to Dn. The contents of the multiply-and-accumulate overflow detect register MCVF are set in the V flag.
Extension Instruction Specifications CLRMAC (Register clear instruction for multiply-and-accumulate operation) [Instruction Format (Macro Name)] CLRMAC [Assembler Mnemonic] udf22 D0, D0 [Operation] This instruction clears the contents of the multiply-and-accumulate registers MCRH and MCRL. This instruction also clears the contents of the multiply-and-accumulate overflow detect register MCVF.
Extension Instruction Specifications MULQ (Signed high-speed multiplication instruction: between registers) [Instruction Format (Macro Name)] MULQ Dm, Dn [Assembler Mnemonic] udf00 Dm, Dn [Operation] This instruction performs multiplication quickly using the multiplier of the extension function unit.
Extension Instruction Specifications MULQI (Signed high-speed multiplication instruction: between immediate value and register) [Instruction Format (Macro Name)] MULQI imm, Dn [Assembler Mnemonic] udf00 imm8, Dn :imm8 is sign-extended udf00 imm16, Dn :imm16 is sign-extended udf00 imm32, Dn [Operation] This instruction performs multiplication quickly using the multiplier of the extension function unit.
Extension Instruction Specifications MULQU (Unsigned high-speed multiplication instruction: between registers) [Instruction Format (Macro Name)] MULQU Dm, Dn [Assembler Mnemonic] udf01 Dm, Dn [Operation] This instruction performs multiplication quickly using the multiplier of the extension function unit.
Extension Instruction Specifications MULQIU (Unsigned high-speed multiplication instruction: between immediate value and register) [Instruction Format (Macro Name)] MULQIU imm, Dn [Assembler Mnemonic] udfu01 imm8, Dn :imm8 is zero-extended udfu01 imm16, Dn :imm16 is zero-extended udfu01 imm32, Dn [Operation] This instruction performs multiplication quickly using the multiplier of the extension function unit.
Extension Instruction Specifications MAC (Signed multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MAC Dm, Dn [Assembler Mnemonic] udf28 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.
Extension Instruction Specifications MACH (Signed half word data multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACH Dm, Dn [Assembler Mnemonic] udf30 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.
Extension Instruction Specifications MACB (Signed byte data multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACB Dm, Dn [Assembler Mnemonic] udf32 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.
Extension Instruction Specifications MACU (Unsigned multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACU Dm, Dn [Assembler Mnemonic] udf29 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.
Extension Instruction Specifications MACHU (Unsigned half word data multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACHU Dm, Dn [Assembler Mnemonic] udf31 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.
Extension Instruction Specifications MACBU (Unsigned byte data multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACBU Dm, Dn [Assembler Mnemonic] udf33 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.
Extension Instruction Specifications SAT16 (16-bit saturation operation instruction) [Instruction Format (Macro Name)] SAT16 Dm, Dn [Assembler Mnemonic] udf04 Dm, Dn [Operation] When Dm is a 16-bit signed number which is the maximum positive value (0x00007fff) or more, the maximum positive value (0x00007fff) is written into Dn. When Dm is a 16-bit signed number which is the maximum negative value (0xffff8000) or less, the maximum negative value (0xffff8000) is stored in Dn.
Extension Instruction Specifications SAT24 (24-bit saturation operation instruction) [Instruction Format (Macro Name)] SAT24 Dm, Dn [Assembler Mnemonic] udf05 Dm, Dn [Operation] When Dm is a 24-bit signed number which is the maximum positive value (0x007fffff) or more, the maximum positive value (0x007fffff) is written into Dn. When Dm is a 24-bit signed number which is the maximum negative value (0xff800000) or less, the maximum negative value (0xff800000) is written into Dn.
Extension Instruction Specifications MCST (Multiply-and-accumulate operation results 8-, 16-, 32-bit saturation operation instruction) [Instruction Format (Macro Name)] MCST Dm, Dn MCST imm8, Dn [Assembler Mnemonic] udf02 Dm, Dn udf02 imm8, Dn : Only 0x20, 0x10, and 0x08 are valid as values for imm8 [Operation] This instruction sets the contents of the multiply-and-accumulate operation overflow detect register MCVF in the V flag.
Extension Instruction Specifications [Flag Changes] When multiply-and-accumulate operation overflow was not detected (MCVF = 0) Flag Change Condition V 0 Indicates that the multiply-and-accumulate operation is valid. C N Z 0 * * Always 0 Undefined Undefined When multiply-and-accumulate operation overflow was detected (MCVF = 1) Flag Change Condition V C N 1 0 * Indicates that the multiply-and-accumulate operation is invalid.
Extension Instruction Specifications MCST9 (Multiply-and-accumulate operation results 9-bit saturation operation instruction/positive value conversion instruction) [Instruction Format (Macro Name)] MCST9 Dn [Assembler Mnemonic] udf03 Dn, Dn [Operation] When the 32-bit result of the multiply-and-accumulate operation that is stored in the multiply-and-accumulate register MCRL is equal to or greater than the maximum positive value for a 9-bit signed numeric value (0x000000ff), the maximum positive value (0xff
Extension Instruction Specifications MCST48 (Multiply-and-accumulate operation results 48-bit saturation operation instruction) [Instruction Format (Macro Name)] MCST48 Dn [Assembler Mnemonic] udf06 Dn, Dn [Operation] When the 64-bit result of the multiply-and-accumulate operation that is stored in the multiply-and-accumulate registers MCRH and MCRL is equal to or greater than the maximum positive value for a 48-bit signed numeric value (0x00007fffffffffff), the maximum positive value (0x00007fffffffff
Extension Instruction Specifications BSCH (Bit search instruction) [Instruction Format (Macro Name)] BSCH Dm, Dn [Assembler Mnemonic] udf07 Dm, Dn [Operation] Bit search is performed within the bit string of the 32 bits contained in Dm from the bit position of the bit number indicated by the contents of Dn - 1 in the direction that the bit number becomes smaller. The bit number of the first bit position where a "1" is found is written into Dn.
Extension Instruction Specifications SWAP (Data swapping instruction that swaps bytes [high-order to low-order and vice versa] in four-byte data) [Instruction Format (Macro Name)] SWAP Dm, Dn [Assembler Mnemonic] udf08 Dm, Dn [Operation] This instruction swaps the positions of the high-order and low-order 8-bit bytes within the respective high- and low-order 16-bit half-words within the 32-bit data stored in Dm, and then swaps the positions of the high-order and low-order 16-bit half-words, and then st
Extension Instruction Specifications [Flag Changes] Flag Change Condition V * Undefined C N Z * * * Undefined Undefined Undefined [Programming Cautions] PSW updating by flag changes is delayed by one instruction. However, Bcc and Lcc instructions can evaluate flags without waiting for flag reflection to PSW. The operations of "udf08 imm8, Dn", "udf08 imm16, Dn" and "udf08 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases.
Extension Instruction Specifications SWAPH (Data swapping instruction [high-order to low-order and vice versa] in two-byte data) [Instruction Format (Macro Name)] SWAPH Dm, Dn [Assembler Mnemonic] udf09 Dm, Dn [Operation] This instruction swaps bits 15 through 8 of Dm with bits 7 through 0, and bits 31 through 24 with bits 23 through 16, and then stores the result in Dn.
Extension Instruction Specifications 3.2.4 Programming Notes ■ Notes on instruction description These programming notes address instruction descriptions as well as instruction placement and combinations. Failure to heed these notes will result in misoperation. A list of these notes is shown below.
Extension Instruction Specifications (a) Note on the description of word/half-word data multiply-and-accumulate instructions and multiply-andaccumulate instructions When executing a word/half-word data multiply-and-accumulate instruction followed by a multiply-and-accumulate instruction, the result produced by the word/half-word data multiply-and-accumulate instruction is used in the execution of the subsequent multiply-and-accumulate instruction.
Extension Instruction Specifications (b) Note on the description of word/half-word data multiply-and-accumulate instructions and MCRH, MCRL access instructions When executing a word/half-word data multiply-and-accumulate instruction followed by an MCRH, MCRL access instruction, the result produced by the word/half-word data multiply-and-accumulate instruction is used in the execution of the subsequent MCRH, MCRL access instruction.
Extension Instruction Specifications (c) Note on the description of byte data multiply-and-accumulate instructions and MCRH, MCRL access instructions When executing a byte data multiply-and-accumulate instruction followed by an MCRH, MCRL access instruction, the result produced by the byte data multiply-and-accumulate instruction is used in the execution of the subsequent MCRH, MCRL access instruction.
Extension Instruction Specifications (d) Note on the description of multiply-and-accumulate instructions and multiply-and-accumulate instructions or multiply-and-accumulate instructions and quick multiplication instructions When executing a multiply-and-accumulate instruction followed by another multiply-and-accumulate instruction or a quick multiplication instruction, at least three cycles must be inserted between the instructions.
Extension Instruction Specifications (e) Note on the description of memory access and multiply-and-accumulate instruction or high-speed multiplication instruction There is an error occasion - CPU hung-up - as written below, if High-speed multiplication instruction or Multiplyand-accumulate instruction is executed within 2 instructions after a memory access instruction that accesses to internal ROM, internal peripheral I/O space or external memory space (this space is referred to as "the space other than in
Extension Instruction Specifications Case 3: Instruction flow Branch High-speed multiplication instruction or Multiply-and-accumulate instruction Memory access instruction accesses to the space other than internal RAM The interrupt occurrence Lcc instruction The case where the High-speed multiplication instruction uses 32-bit immediate value is excluded. If a stack area is in the internal RAM, any error making potential condition shown on the following cases 4 to 12 is not generated.
Extension Instruction Specifications Case 9: Instruction flow High-speed multiplication instruction or Multiply-and-accumulate instruction Branch The interrupt occurrence CALLS or JSR instruction with stack area outside internal RAM area The case where the High-speed multiplication instruction uses 32-bit immediate value is excluded.
Extension Instruction Specifications In addition, please obey the following recommended conditions of 3 points when a program is developed by the assembler so that this error would not occur. As for the program developed by the PanaXSeries C compiler, the following recommended conditions are guaranteed. 1. Please use RTI instruction on a return from an interrupt. 2. Please use the value set by SETLB instruction for LIR and LAR which stores branch target of Lcc instruction. 3.
Extension Instruction Specifications 3-40
4.
Memory Modes 4.1 Memory Mode Types and Selection This microcontroller has a 32-bit linear address space of up to 4 Gbytes. The address space is comprised of internal memory space built into the chip and external memory space located outside the chip.
Memory Modes 4.2 Memory Mode Pin Processing Fix the input levels for the memory mode pins (MMOD0,1) as shown in Table 4-2-1 and Fig. 4-2-1 with pull-up/ pull-down resistors. For details on the pull-up/pull-down resistance, refer to “High-speed Serial Control Card Operation Manual”.
Memory Modes 4.3 Description of Memory Mode 4.3.1 Memory Extension Mode The memory mode which comprises a system from both internal and external memory is called memory extension mode. This mode enables configuration of a system where the program and data make the best use of the highspeed performance of internal memory and the large capacity of external memory.
Memory Modes 4.3.2 Processor Mode The memory mode which executes externally located instructions while using the internal data RAM and I/O ports is called processor mode. The internal instruction ROM and the internal flash memory are not used for this mode. Processor mode has memory space of up to 3 GB from addresses x'00000000 to x'BFFFFFFF.
Memory Modes 4-6
5.
Operating Mode 5.1 Overview The 32-bit microcontroller has the following three operating modes. Oscillator start/stop and CPU and peripheral circuit start/stop switching control functions are provided to support low power consumption. Operating modes 1. Reset mode (RESET) 2. Normal operation mode (NORMAL) 3.
Operating Mode 5.2 Reset Mode • The mode in which the reset (RST) pin is active (“L” level) is called “Reset Mode”. • When the reset pin is low, the chip is reset (initialized) internally. When the reset pin makes the transition to high, the oscillation stabilization wait time is started by an internal 18-bit (when CKSEL pin = “H”) or 19-bit (when CKSEL pin = “L”) binary counter based on the oscillation clock.
Operating Mode 5.3 Low Power Mode Low power consumption is achieved by stopping the oscillation of the oscillators and the clock generator (CG) and stopping the clocks supplied to the CPU and peripheral circuits. Low power mode contains the following three modes and transitions to the three modes are made through software. Stop mode (STOP) In this mode, the oscillation of oscillators as well as the CG oscillation are stopped.
6.
Clock Generator 6.1 Overview The CG has an internal PLL circuit; in addition to supplying clock pulses to this microcontroller at a frequency that is a multiple of the oscillating frequency of the oscillator, the CG also supplies clock pulses with the same frequency as the oscillating frequency of the oscillator, or that frequency divided by 2, to external devices. 6.2 Features The features of the CG are described below.
Clock Generator 6.4 Description of Operation 6.4.1 Input Frequency Setting The CG input frequency range is set by the external input pin CKSEL. When CKSEL is set “H”, use an oscillator or resonator with an input frequency fosci such that 8 MHz ≤ fosci ≤ 18 MHz. When CKSEL is set “L”, use an oscillator or resonator with an input frequency fosci such that 8 MHz ≤ fosci ≤ 20 MHz. Use of an oscillator or resonator that generates a frequency lower than 8 MHz, or higher than 20 MHz is prohibited.
Clock Generator The relationship between the input frequency (fosci) and the SYSCLK, MCLK, and IOCLK multiples and frequencies is shown in Table 6-4-2, and the relationship between the input frequency (fosci) and the SYSCLK, MCLK, and IOCLK multiples and frequencies when reset is released is shown in Table 6-4-3.
7.
Internal Memory 7.1 Overview The MN103001G has 128 Kbytes of instruction ROM and 8 Kbytes of internal data RAM. The MN1030F01K has 256 Kbytes of flash memory and 8 Kbytes of internal data RAM. The instruction ROM/flash memory and data RAM are connected to the CPU core via a 64-bit bus and a 32-bit bus, respectively. 7.2 Features The features of the internal memory are listed below.
Internal Memory 7.3 Internal Memory Configuration The internal instruction ROM is located in the internal memory space at address x'40000000 to x'4001FFFF, while the internal flash memory is located at address x'40000000 to x'4003FFFF and the internal data RAM is located at address x'00000000 to x'00001FFF. Each is connected to the CPU core independently by a dedicated bus in the Harvard architecture (in memory extension mode). Fig.
Internal Memory 7-4
8.
Bus Controller (BC) 8.1 Overview The bus controller (BC) controls interfacing between the CPU core, internal I/O (peripherals), and devices external to the chip. The bus controller also handles arbitration between the internal and external buses. In addition, in an interface with devices external to the chip, it is possible to select whether address pins and data pins are separate or multiplex.
Bus Controller (BC) 8.3 Bus Configuration Fig. 8-3-1 shows the bus configuration. The chip’s internal buses are the ROM bus between the CPU core and internal instruction ROM/internal flash memory, the RAM bus between the CPU core and internal data RAM, the BC bus between the CPU core and the bus controller, and the I/O bus between the bus controller and internal I/O. The EX bus is an external bus. Table 8-3-1 lists the characteristics of each bus.
8-4 Fig.
Bus Controller (BC) 8.5 Pin Functions The external pin functions relating to the bus controller are shown in Table 8-5-1.
Bus Controller (BC) Table 8-5-2 shows the operating status of the external pins concerning BC.
Bus Controller (BC) 8.6 Description of Registers Table 8-6-1 lists the bus controller registers. The settings of these registers are used in timing control, DRAM interface control, etc.
Bus Controller (BC) 8.6.1 Memory Block 0 Control Register Memory control register 0A/B is used to set the memory block 0 read/write timing and synchronous/asynchronous mode through software. Memory control register 0A Register symbol: MEMCTR0A Address: x’32000030 Purpose: Sets the access timing, etc., for external memory space block 0. Bit No.
Bus Controller (BC) Memory control register 0B Register symbol: MEMCTR0B Address: x’32000020 Purpose: Sets the bus mode, access timing, etc., for external memory space block 0.
Bus Controller (BC) 8.6.2 Memory Block 1 Control Register Memory control register 1A/B is used to set the memory block 1 read/write timing, synchronous/asynchronous mode, DRAM mode, page mode, and bus width through software. Memory control register 1A Register symbol: MEMCTR1A Address: x’32000032 Purpose: Sets the access timing, etc., for external memory space block 1. Bit No.
Bus Controller (BC) When using DRAM (Memory control register 1B B1DRAM = 1) Description Setting conditions 1 to 0 BCS1 to 0 Row address setup timing (use as ASR parameter) 00: prohibited 01: 1MCLK Column address setup timing (use as ASC parameter) 3MCLK 00: prohibited 01: 1MCLK 11: REN4 to 0 000: prohibited 001: 1MCLK CAS pulse width (use as CAS parameter) 11: 3MCLK ~ ~ RAS hold time (use as RSH parameter) ~ 00: prohibited 01: 1MCLK 111: 7MCLK 00000: prohibited 00001: 1MCLK ~ 15 to 1
Bus Controller (BC) Memory control register 1B Register symbol: MEMCTR1B Address: x’32000022 Purpose: Sets the bus mode, access timing, etc., for external memory space block 1. Bit No.
Bus Controller (BC) When using DRAM (Memory control register 1B B1DRAM = 1) Bit No. Bit name 0 DRAM 2 BM Block 1 bus mode 3 PE Block 1 software page mode enable 4 BW Block 1 bus width 0: 8 bits 1: 16 bits 7 to 6 ASA1 to 0 Always set to "01". Any setting other than "01" is prohibited. 10 to 8 ASN2 to 0 RAS precharge cycle (use as RP parameter) 1: Use as DRAM space.
Bus Controller (BC) 8.6.3 Memory Block 2 Control Register Memory control register 2A/B is used to set the memory block 2 read/write timing, synchronous/asynchronous mode, fixed wait/handshaking mode, DRAM mode, page mode, and bus width through software. Memory control register 2A Register symbol: MEMCTR2A Address: x’32000034 Purpose: Sets the access timing, etc., for external memory space block 2. Bit No.
Bus Controller (BC) When using handshaking mode (Memory control register 2B B2DRAM = 0, B2WM = 1) Description Setting conditions 1 to 0 BCS1 to 0 DK detection wait cycle (use as DW parameter) 00: prohibited 01: 1MCLK 10: 2MCLK 11: 3MCLK 3 to 2 EA1 to 0 RE/WE assert timing 00: prohibited 01: 1MCLK 10: 2MCLK 11: 3MCLK 5 to 4 ADE1 to 0 Address output end timing 00: 0MCLK ~ Bit name ~ Bit No.
Bus Controller (BC) Memory control register 2B Register symbol: MEMCTR2B Address: x’32000024 Purpose: Sets the bus mode, access timing, etc., for external memory space block 2. Bit No.
Bus Controller (BC) When using handshaking mode (Memory control register 2B B2DRAM = 0, B2WM = 1) Bit No. Bit name 0 DRAM 1 Description Setting conditions Block 2 DRAM space setting 0: Do not use as DRAM space.
Bus Controller (BC) After the reset is released, block 2 is set as follows: Address output end timing 3MCLK RE negate timing 29MCLK WE negate timing 29MCLK RE/WE assert timing 3MCLK Bus cycle start timing 0MCLK Bus cycle end timing 31MCLK AS assert timing 1MCLK AS negate timing 3MCLK The bus width is 16 bits, and synchronous fixed wait mode is set.
Bus Controller (BC) 8.6.4 Memory Block 3 Control Register Memory control register 3A/B is used to set the memory block 3 read/write timing, synchronous/asynchronous mode, fixed wait/handshaking mode, and bus width through software. However, the handshaking mode can only be set when (MCLK frequency/SYSCLK frequency) = 4. Memory control register 3A Register symbol: MEMCTR3A Address: x’32000036 Purpose: Sets the access timing, etc., for external memory space block 3. Bit No.
Bus Controller (BC) When using handshaking mode (Memory control register 3B B3WM = 1) Bit No.
Bus Controller (BC) When using handshaking mode (Memory control register 3B Bit No.
Bus Controller (BC) 8.6.5 DRAM control register DRAM control register Register symbol: DRAMCTR Address: x'32000040 Purpose: Stores various DRAM mode settings when DRAM is connected. Bit No. Bit name Reset Access 15 14 13 12 – – – – 0 R 0 R 0 R 0 R Bit No.
Bus Controller (BC) 8.6.6 Refresh count register Register symbol: REFCNT Address: x'32000042 Purpose: Sets the DRAM refresh interval when DRAM is connected.
Bus Controller (BC) 8.6.7 Page Row Address Register Page Row Address Register Register symbol: PRAR Address: x'32000044 Purpose: Sets the row address for DRAM software page mode. Bit No. Bit name Reset Access 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When DRAM software page mode is initiated (i.e.
Bus Controller (BC) Notes when switching the internal clock multiplier Be aware of the following points when setting the clock control register CKCTR and changing the internal clock multiplier. • If external memory is accessed immediately after setting the clock control register CKCTR, the multiplier for the internal clock MCLK may change in the middle of the access, resulting in a change in the external bus timing.
Bus Controller (BC) 8.7 Space Partitioning In extension memory mode (MMOD 1 to 0 = "LH"), the 1 GB memory space from x'80000000 to x'BFFFFFFF becomes external memory space; in processor mode (MMOD 1 to 0 = "HL"), the 2 GB memory space from x'40000000 to x'BFFFFFFF becomes external memory space. External memory space is partitioned into 4 blocks (block 0 to block 3). When any of these blocks are accessed, various signals (such as CSn) corresponding to the block in question are output. Fig.
Bus Controller (BC) Extension memory mode x'00000000 x'90000000 x'90800000 x'91000000 x'91800000 x'92000000 x'92800000 x'93000000 x'93800000 2 GB 8 MB space Address extension Block0 (64 MB) Block1 (64 MB) x'80000000 Block2 (64 MB) x'90000000 Block3 (64 MB) x'A0000000 1 GB x'B0000000 x'C0000000 System reserved 1 GB x'9C000000 x'9C800000 x'9D000000 x'9D800000 x'9E000000 x'9E800000 x'9F000000 x'9F800000 8 MB space There is no portion for address extension for block 3 x'FFFFFFFF Processor mode x'
Bus Controller (BC) 8.8 Operation Clocks MCLK, IOCLK, and SYSCLK are used as BC operation clocks. Table 8-8-1 shows the ratio of each clock versus the oscillation input clock (OSCI).
Bus Controller (BC) 8.10 Bus Cycle Depending on the value of the external input pin CKSEL and the internal registers, the MCLK frequency can be either 1/2, 1, 2, or 4 times the input frequency, and the IOCLK frequency can be either 1/8, 1/4, 1/2, or 1 times the input frequency. Note that SYSCLK is output with either 1/2 or 1 times the input frequency.
Bus Controller (BC) 8.11 Store Buffer The bus controller has one store buffer (with a 32-bit data width) built in, and is used to avoid a time penalty when conducting a store operation in internal I/O or external memory. The CPU store operation is completed storing the address, data, and access size in the store buffer, and is executed with no wait states. Writes from the store buffer to internal I/O or external memory are conducted in parallel with subsequent CPU operations.
Bus Controller (BC) 8.12 Accessing the Internal I/O Space Accesses to the internal I/O space (I/O register) are performed through the I/O bus, with the bus controller controlling the interface for read/write requests from the CPU. Accesses between the bus controller and the internal I/O space are executed in synchronization with IOCLK. Fig. 8-12-1 shows the timing chart when accessing the internal I/O space. MCLK IOCLK I/O Bus Address RR WR DSn I/O Bus Data Read Write Fig.
Bus Controller (BC) 8.13 External Memory Space Access (Non-DRAM Spaces) During an access to external memory, the BC controls the interface for the read/write request from the CPU. Table 8-13-1 lists the transactions that are supported for the external bus.
Bus Controller (BC) 8.13.1 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode Setting of the various parameters for external memory access is performed in memory control registers 0 to 3, corresponding to each block. In synchronous mode, the bus access is initiated in synchronization with SYSCLK. When fixed wait insertion is specified, the bus access ends to the timing set in the memory control register. Fig.
Bus Controller (BC) MCLK SYSCLK BCE BCS BCS BCE An CSn REN RE EA WEN WEn EA Dn Read Write :Undefined Fig. 8-13-2 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.” MCLK SYSCLK BCS=0 BCE BCS=0 BCE An CSn REN RE EA WEN WEn EA Dn Read Write : Undefined Fig.
Bus Controller (BC) 8.13.2 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode When using handshaking, bus access starts once synchronization with SYSCLK is achieved, and after the data acknowledge signal (DK) is asserted, 2 MCLK cycles are consumed by the BC internally and then the access is completed according to the specified parameters. The various parameters for external memory access are set in memory control registers 2 and 3, corresponding to each block.
Bus Controller (BC) MCLK SYSCLK An BCE CS2 EA Consumed internally by the BC DW RE BCE Consumed internally by the BC DK detection start REN EA DW WEn DK detection start WEN DK Dn Write Read : Undefined Fig. 8-13-5 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.
Bus Controller (BC) 8.13.3 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode Asynchronous mode is used for accessing external memory at high speed; the address signals, CSn signals, etc., are output asynchronously with the SYSCLK but in synchronization with the internal MCLK. In asynchronous mode, accesses are all by fixed wait insertion. Fig.
Bus Controller (BC) MCLK SYSCLK BCE BCE An CSn REN RE EA WEN WEn EA Dn Read Write : Undefined Fig. 8-13-8 Access Timing on a 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.” MCLK SYSCLK BCE BCE An CSn REN RE EA WEN WEn EA Dn Read Write : Undefined Fig.
Bus Controller (BC) 8.13.4 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode 8-bit bus mode is set for block 0 by setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, and for blocks 1 to 3 by setting the BnBW bit to "0" in the corresponding memory control register. In 8-bit bus mode, half-word access (16 bits) is performed by means of two external accesses, with A[0] = "0" for the low-order byte and A[0] = "1" for the high-order byte.
Bus Controller (BC) MCLK SYSCLK BCS BCS An BCS BCS BCE BCE BCE BCE A[0]=0 A[0]=1 A[0]=0 A[0]=1 CSn REN REN RE EA EA WEN WEN WE0 EA EA D7-0 Read loworder side Read highorder side Write loworder side Write highorder side : Undefined Fig.
Bus Controller (BC) 8.13.5 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode 8-bit bus mode is set for blocks 2 and 3 by setting the BnBW bit to “0” in the corresponding memory control register. In 8-bit bus mode, half-word access (16 bits) is performed by means of two external accesses, with A[0] = "0" for the low-order byte and A[0] = "1" for the high-order byte.
Bus Controller (BC) MCLK SYSCLK An A[0]=1 A[0]=0 BCE BCE CSn EA Consumed internally by the BC DW RE EA Consumed internally by the BC DW DK detection start DK detection start REN “H” REN WE0 DK D7-0 Read low-order side Read high-order side : Undefined (a) Read Timing MCLK SYSCLK An A[0]=0 A[0]=1 CSn RE Consumed internally by the BC EA WE0 BCE BCE “H” DW EA DW Consumed internally by the BC DK detection start DK detection start WEN WEN DK D7-0 Write high-order side Wr
Bus Controller (BC) MCLK SYSCLK An A[0]=1 A[0]=0 BCE BCE CS2 EA Consumed internally by the BC DW RE EA DW DK detection start Consumed internally by the BC DK detection start REN “H” REN WE0 DK D7-0 Read low-order side Read high-order side : Undefined (a) Read Timing MCLK SYSCLK An A[0]=0 A[0]=1 CS2 BCE “H” RE EA WE0 BCE Consumed internally by the BC Consumed internally by the BC EA DW DW DK detection start DK detection start WEN WEN DK D7-0 : Undefined Write high-or
Bus Controller (BC) MCLK SYSCLK An A[0]=1 A[0]=0 BCE BCE CS2 EA Consumed internally by the BC DW RE EA Consumed internally by the BC DW DK detection start DK detection start REN “H” REN WE0 DK D7-0 Read high-order side Read low-order side : Undefined (a) Read Timing MCLK SYSCLK An A[0]=0 A[0]=1 CS2 “H” RE EA WE0 BCE BCE Consumed internally by the BC Consumed internally by the BC DW EA DW DK detection start DK detection start WEN WEN DK D7-0 Write high-order side Wri
Bus Controller (BC) 8.13.6 8-bit Bus in Asynchronous Mode and in Address/Data Separate Mode 8-bit bus mode is set for block 0 by setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, and for blocks 1 to 3 by setting the BnBW bit to “0” in the corresponding memory control register. In 8-bit bus mode, half-word access (16 bits) is performed by means of two external accesses, with A[0] = "0" for the low-order byte and A[0] = "1" for the high-order byte.
Bus Controller (BC) 8.13.7 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use common pins for the memory address and memory data signals (pins ADM15 to 0). In synchronous mode, the bus access starts in synchronization with SYSCLK, and when fixed wait states are inserted, the access ends according to the timing that was set in the memory control register.
Bus Controller (BC) MCLK SYSCLK BCS BCE BCS BCE A23* to 16 addr “0”( “L” ) addr “0”( “L” ) ADM15 to 0 addr data in addr data out ADE ADE ASA ASA CSn AS ASN ASN RWSEL EA RE REN WEN WEn EA : Undefined : * Undefined or Hi-Z : A23 also serves as CS3 Fig.
Bus Controller (BC) 8.13.8 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 2 and 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0).
Bus Controller (BC) MCLK SYSCLK A23* to 16 addr ADM15 to 0 addr “0”( “L” ) data in ADE addr “0”( “L” ) addr data out ADE CSn ASA BCE ASA BCE AS ASN RWSEL ASN EA DW RE Consumed internally by the BC DK detection start EA REN DW WEn Consumed internally by the BC DK detection start WEN DK * : Undefined : Undefined or Hi-Z Read Write : A23 also serves as CS3 Fig.
Bus Controller (BC) MCLK SYSCLK A23* to 16 addr ADM15 to 0 addr “0”( “L” ) data in addr “0”( “L” ) addr data out ADE ADE CS2 ASA BCE ASA BCE AS ASN ASN RWSEL EA DW RE Consumed internally by the BC DK detection start REN EA DW WEn Consumed internally by the BC DK detection start WEN DK : Undefined : Undefined or Hi-Z * : A23 also serves as CS3 Read Write Fig.
Bus Controller (BC) 8.13.9 16-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0). Asynchronous mode is used for accessing external memory at high speed; the address signals, CS signals, etc., are output asynchronously with SYSCLK but in synchronization with the internal MCLK.
Bus Controller (BC) 8.13.10 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0). 8-bit bus mode is set for block 0 by setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, and for blocks 1 to 3 by setting the BnBW bit to “0” in the corresponding memory control register.
Bus Controller (BC) MCLK SYSCLK BCS BCS BCE BCE A23* to 16 A[0]=0 “0”( “L” ) A[0]=1 ADM15 to 0 A[0]=0 data in A[0]=1 ADE ADE ASA ASA “0”( “L” ) data in CSn AS ASN ASN RWSEL EA EA RE REN REN “H” WE0 * Read high-order side Read low-order side : Undefined : Undefined or Hi-Z : A23 also serves as CS3 (a) Read Timing MCLK SYSCLK BCS BCS BCE BCE A23* to 16 A[0]=0 “0”( “L” ) A[0]=1 “0”( “L” ) ADM15 to 0 A[0]=0 data out A[0]=1 data out ADE ADE CSn ASA ASA AS ASN ASN
Bus Controller (BC) MCLK SYSCLK BCE BCS BCE BCS A23* to 16 A[0]=0 “0”( “L” ) A[0]=1 “0”( “L” ) ADM15 to 0 A[0]=0 data in A[0]=1 data in ADE ADE CSn ASA ASA AS ASN ASN RWSEL EA EA RE REN “H” REN WE0 * : Undefined : Undefined or Hi-Z Read low-order side Read high-order side : A23 also serves as CS3 (a) Read Timing MCLK SYSCLK BCS BCE BCE BCS A23* to 16 A[0]=0 “0”(“L”) A[0]=1 “0”(“L”) ADM15 to 0 A[0]=0 data out A[0]=1 data out ADE ADE CSn ASA ASA AS ASN ASN R
Bus Controller (BC) MCLK SYSCLK BCS=0 BCE BCE A23* to 16 A[0]=0 “0” (“L”) A[0]=1 “0” (“L”) ADM15 to 0 A[0]=0 data in A[0]=1 data in ADE ADE ASA ASA CSn AS ASN ASN RWSEL EA EA RE REN REN “H” WE0 * : Undefined : Undefined or Hi-Z Read low-order side Read high-order side : A23 also serves as CS3 (a) Read Timing MCLK SYSCLK BCS=0 BCE BCE A23* to 16 A[0]=0 “0”(“L”) A[0]=1 “0”(“L”) ADM15 to 0 A[0]=0 data out A[0]=1 data out ADE ADE ASA ASA CSn AS ASN ASN RWSEL RE
Bus Controller (BC) 8.13.11 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 2 and 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0). 8-bit bus mode is set for blocks 2 and 3 by setting the BnBW bit to “0” in the corresponding memory control register.
Bus Controller (BC) MCLK SYSCLK A23* to 16 A[0]=0 ADM15 to 0 A[0]=0 “0” (“L”) “0” (“L”) A[0]=1 data in data in A[0]=1 ADE ADE CSn ASA BCE BCE ASA AS ASN RWSEL ASN Consumed internally by the BC DW RE DK detection start DK detection start REN EA “H” Consumed internally by the BC DW REN EA WE0 DK * : Undefined : Undefined or Hi-Z Read high-order side Read low-order side : A23 also serves as CS3 (a) Read Timing MCLK SYSCLK A23* to 16 A[0]=0 “0” (“L”) A[0]=1 “0” (“L”) AD
Bus Controller (BC) MCLK SYSCLK A23* to 16 A[0]=0 ADM15 to 0 A[0]=0 “0”( “L” ) A[0]=1 “0”( “L” ) data in data in A[0]=1 ADE ADE CS2 ASA BCE ASA BCE AS ASN ASN RWSEL EA Consumed internally by the BC DW RE EA DK detection start DW Consumed internally by the BC DK detection start REN REN “H” WE0 DK : Undefined * Read high-order side Read low-order side : Undefined or Hi-Z : A23 also serves as CS3 (a) Read Timing MCLK SYSCLK A23* to 16 A[0]=0 “0” (“L”) A[0]=1 “0” (“L”) A
Bus Controller (BC) MCLK SYSCLK A23* to 16 A[0]=0 ADM15 to 0 A[0]=0 “0” (“L”) A[0]=1 “0” (“L”) data in data in A[0]=1 ADE ADE CS2 ASA BCE ASA BCE AS ASN RWSEL ASN EA RE Consumed internally by the BC DW EA DK detection start DW Consumed internally by the BC DK detection start REN REN “H” WE0 DK : Undefined : Undefined or Hi-Z * : A23 also serves as CS3 Read low-order side Read high-order side (a) Read Timing MCLK SYSCLK A23* to 16 A[0]=0 “0” (“L”) A[0]=1 “0” (“L”) ADM1
Bus Controller (BC) 8.13.12 8-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0). 8-bit bus mode is set for block 0 by setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, and for blocks 1 to 3 by setting the BnBW bit to “0” in the corresponding memory control register.
Bus Controller (BC) MCLK SYSCLK BCE BCE A23* to 16 A[0]=0 “0” (“L”) A[0]=1 “0” (“L”) ADM15 to 0 A[0]=0 data in A[0]=1 data in ADE ADE ASA ASA CSn AS ASN ASN RWSEL EA EA RE REN “H” REN WE0 : Undefined * : Undefined or Hi-Z : A23 also serves as CS3 Read low-order side Read high-order side (a) Read Timing MCLK SYSCLK BCE BCE A23* to 16 A[0]=0 “0” (“L”) A[0]=1 “0” (“L”) ADM15 to 0 A[0]=0 data out A[0]=1 data out ADE ADE ASA ASA CSn AS ASN ASN RWSEL RE “H” WEN WEN
Bus Controller (BC) 8.14 External Memory Space Access (DRAM Space) 8.14.1 DRAM Space Blocks 1 and 2 can be used as DRAM space by setting the BnDRAM bits in memory control registers 1B/2B and setting the DRAME bit in DRAM control register. The DRAM bus cycle is always not synchronized the external clock (but is synchronized with MCLK), and performs address multiplexed output, RAS/CAS signal output, etc. Note: When common pins are used for addresses and data, DRAM cannot be supported.
Bus Controller (BC) ■ Minimum value for the RAS Precharge interval When consecutive DRAM accesses are performed, the RAS precharge interval is shortest when performing an access of type (1) or (2) below while the PAGE bit is set to “0” in the DRAM control register: (1) Word/half-word access while the bus width is set to 8 bits (2) Word access while the bus width is set to 16 bits Because the minimum value for the RAS precharge interval is: RP + ASR as shown in Fig.
Bus Controller (BC) ■ 2 WE control/2 CAS control DRAM that permits byte/word control can be supported by selecting either one of the following two methods: • 2 WE control: The two pins WE1 and WE0 are used for byte/word control. • 2 CAS control: The two pins DCAS1 and DCAS0 are used for byte/word control. Fig. 8-14-3 illustrates an example of a write using 2 WE control, and Fig. 8-14-4 illustrates an example of a write using 2 CAS control. MCLK An Row Column Row Column RASn CAS WE1 WE0 Dn Fig.
Bus Controller (BC) 8.14.2 DRAM page mode If the PAGE bit in the DRAM control register is set to “1”, page mode access is enabled, making high-speed access in page mode possible for following accesses to DRAM. (1) Word/half-word access when the bus width is set to 8 bits (2) Word access when the bus width is set to 16 bits Fig. 8-14-5 shows the page mode read timing and write timing.
Bus Controller (BC) 8.14.3 Software Page Mode Software page mode is a mode that forcibly initiates page mode by setting the control register. Operation within software page mode is as described below. Refer to Fig. 8-14-6. • When the mode is initiated, the contents of PRAR are output as the row address. • While the mode is in effect, RASn for the block corresponding to the memory control register that initiated the mode is maintained in the asserted state.
Bus Controller (BC) MCLK An Row Column Column Column CAO+1 ASR RASn ASC ASC ASC CAS CAS CAS CAS RE Dn (a) Read Timing MCLK An Row Column Column Column ASC ASC ASC CAO+1 ASR RASn CAS CAS CAS CAS WEn Dn (b) Write Timing Fig. 8-14-6 Software Page Mode Read/Write Timing For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.
Bus Controller (BC) [Restrictions on Use] (1) While software page mode is in effect, external access outside of the block in question is prohibited. Cancel software page mode before accessing an external memory space other than the block for which software page mode is set. (2) While software page mode is in effect, the bus will not be released, regardless of any accesses to DRAM, even if the bus request signal BR is asserted.
Bus Controller (BC) Refresh count value REFC 0 REFC Count interval Refresh is executed during idle cycle 0 REFC Count interval Refresh is executed with highest priority REFE bit is set Fig. 8-14-7 DRAM Refresh Operation MCLK SYSCLK An RERS RAS1 RAS2 ASR RP ASR CAS “H” RE “H” WEn Dn “Hi-Z” Refresh Fig. 8-14-8 DRAM Refresh Timing For details on the ASR and RP settings, refer to the explanations in section 8.6.2, “Memory Block 1 Control Register,” and section 8.6.
Bus Controller (BC) 8.15 Bus Arbitration In this microcontroller, bus arbitration is implemented through the bus authority request signal (BR) and the bus authority release signal (BG). If an external device asserts the BR signal, then once the current bus access that is being executed is completed, the BG signal is asserted and the bus authority is released to the external device. Once the BR signal is negated, this LSI negates the BG signal in order to re-acquire the bus authority.
Bus Controller (BC) MCLK SYSCLK An “Hi-Z” CSn “Hi-Z” RE “Hi-Z” WEn “Hi-Z” RASn “Hi-Z” CAS “Hi-Z” Dn “Hi-Z” BR BG CPU External device Standby Bus access Fig. 8-15-1 Bus Arbitration Timing 1 (Bus Authority Release/Bus Authority Acquisition, nfr = 4) MCLK SYSCLK An “Hi-Z” CSn “Hi-Z” RE “Hi-Z” WEn “Hi-Z” RASn “Hi-Z” CAS “Hi-Z” Dn “Hi-Z” BR BG CPU Standby External device Bus access Fig.
Bus Controller (BC) MCLK SYSCLK An “Hi-Z” CSn “Hi-Z” RE “Hi-Z” WEn “Hi-Z” RASn “Hi-Z” CAS “Hi-Z” Dn “Hi-Z” BR BG CPU External device Standby Bus access Fig. 8-15-3 Bus Arbitration Timing 3 (Bus Authority Release/Bus Authority Acquisition, nfr = 1) MCLK SYSCLK An CSn RE WEn RASn CAS Dn “Hi-Z” “Hi-Z” “Hi-Z” “Hi-Z” “Hi-Z” “Hi-Z” “Hi-Z” BR BG External device Standby Refresh Fig.
Bus Controller (BC) 8.16 Cautions These cautions concern the BC. These cautions must be heeded, since failure to do so may result in misoperation. 1. Do not change the contents of the relevant memory control register and the DRAM control register while accessing external memory space, except when software page mode is not in effect. 2. Do not overwrite the refresh counter register while the REFE bit is “1” in the DRAM control register. 3.
Bus Controller (BC) _____ 2. Designate the bus authority request pin (BR) as a general-purpose input port, and the bus authority release _____ pin (BG) as a general-purpose output port, for instance, so that bus requests cannot be accepted during execution of a BSET or BCLR instruction.
9.
Interrupt Controller 9.1 Overview The interrupt controller processes non-maskable interrupts and level interrupts (internal interrupts and external interrupts). For external pins, the microcontroller has eight external interrupt pins and one non-maskable interrupt pin. 9.2 Features • Up to four interrupt requests can be accepted by each group. • Interrupt priority level: Can be set for each interrupt group.
Interrupt Controller 9.
Interrupt Controller Interrupt control register address GROUP 7 GROUP 8 GROUP 9 GROUP 10 GROUP 11 GROUP 12 GROUP 13 0 Serial 0 reception 1 Serial 0 transmission 2 — 3 — 0 Serial 1 reception 1 Serial 1 transmission 2 — 3 — 0 Serial 2 reception 1 Serial 2 transmission 2 — 3 — 0 Serial 3 reception 1 Serial 3 transmission 2 — 3 — 0 External interrupt 0 1 — 2 — 3 — 0 External interrupt 1 1 — 2 — 3 — 0 External interrupt 2 1 — 2 — 3 — x'34000120 x'
Interrupt Controller Interrupt control register address GROUP 14 GROUP 15 GROUP 16 GROUP 17 GROUP 18 GROUP 19 0 External interrupt 3 1 — 2 — 3 — 0 External interrupt 4 1 — 2 — 3 — 0 External interrupt 5 1 — 2 — 3 — 0 External interrupt 6 1 — 2 — 3 — 0 External interrupt 7 1 — 2 — 3 — 0 A/D conversion end 1 — 2 — 3 — x'34000138 x'3400013C x'34000140 x'34000144 x'34000148 x'3400014C Fig.
Interrupt Controller 9.5 Description of Registers This interrupt controller includes an interrupt control registers, an interrupt accepted group register, and an external interrupt condition specification register. Table 9-5-1 lists the interrupt controller registers.
Interrupt Controller Non-maskable interrupt control register Register symbol: G0ICR (NMICR) Address: x'34000100 Purpose: This register determines whether a non-maskable interrupt has been generated. Bit No. Bit name Reset Access 15 14 13 12 11 10 9 8 7 6 5 4 3 - - - - - - - - - - - - - SYSEF SYSE WDIF NMIF 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group n interrupt control register GnICR (n = 2 to 19) Registers G2ICR to G19ICR control level interrupts for groups 2 to 19, respectively. Each register confirms the group interrupt level as well as the enabling, request, and detection of interrupts within the respective group. The explanation on this page applies to registers G2ICR to G19ICR. The interrupt control registers for group 2 to 19 are described starting on page 9-10. Bit No.
Interrupt Controller Bit No. 11 to 8 Bit name IE3 to 0 14 to 12 LV2 to 0 Description Group n interrupt enable register • This register is used to specify whether an interrupt is enabled or not. • When an IEn(n=3 to 0) bit is set to "1", the corresponding interrupt is enabled. • Setting an IEn bit while the corresponding IRn(n=3 to 0) bit is set generates an interrupt. Group n interrupt priority level register • This register sets the interrupt priority levels.
Interrupt Controller Group 2 interrupt control register Register symbol: G2ICR Address: x'34000108 Purpose: This register is used to enable group 2 interrupts, and to confirm interrupt requests and detection. Bit No. 15 Bit name Reset Access 0 R 14 12 11 10 9 8 7 6 5 4 3 2 1 0 G2 G2 G2 TM3 TM2 TM1 TM0 TM3 TM2 TM1 TM0 TM3 TM2 TM1 TM0 LV2 LV1 LV0 IE IE IE IE IR IR IR IR ID ID ID ID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit No.
Interrupt Controller Group 3 interrupt control register Register symbol: G3ICR Address: x'3400010C Purpose: This register is used to enable group 3 interrupts, and to confirm interrupt requests and detection. Bit No. 15 Bit name Reset Access 0 R 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G3 G3 G3 TM7 TM6 TM5 TM4 TM7 TM6 TM5 TM4 TM7 TM6 TM5 TM4 LV2 LV1 LV0 IE IE IE IE IR IR IR IR ID ID ID ID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit No.
Interrupt Controller Group 4 interrupt control register Register symbol: G4ICR Address: x'34000110 Purpose: This register is used to enable group 4 interrupts, and to confirm interrupt requests and detection. Bit No. 15 Bit name Reset Access 0 R 14 12 11 10 9 8 7 6 5 4 3 2 1 0 G4 G4 G4 TMB TMA TM9 TM8 TMB TMA TM9 TM8 TMB TMA TM9 TM8 LV2 LV1 LV0 IE IE IE IE IR IR IR IR ID ID ID ID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit No.
Interrupt Controller Group 5 interrupt control register Register symbol: G5ICR Address: x'34000114 Purpose: This register is used to enable group 5 interrupts, and to confirm interrupt requests and detection. Bit No. 15 Bit name Reset Access 0 R 14 13 12 G5 G5 G5 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group 6 interrupt control register Register symbol: G6ICR Address: x'34000118 Purpose: This register is used to enable group 6 interrupts, and to confirm interrupt requests and detection. Bit No. 15 Bit name Reset Access 0 R 14 12 G6 G6 G6 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group 7 interrupt control register Register symbol: G7ICR Address: x'3400011C This register is used to enable group 7 interrupts, and to confirm interrupt requests and detection. Purpose: Bit No. 15 Bit name Reset Access 0 R 14 13 12 G7 G7 G7 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group 8 interrupt control register Register symbol: G8ICR Address: x'34000120 This register is used to enable group 8 interrupts, and to confirm interrupt requests and detection. Purpose: Bit No. 15 Bit name Reset Access 0 R 14 12 G8 G8 G8 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group 9 interrupt control register Register symbol: G9ICR Address: x'34000124 This register is used to enable group 9 interrupts, and to confirm interrupt requests and detection. Purpose: Bit No. 15 Bit name Reset Access 0 R 14 13 12 G9 G9 G9 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group 10 interrupt control register Register symbol: G10ICR Address: x'34000128 This register is used to enable group 10 interrupts, and to confirm interrupt requests and detection. Purpose: Bit No. 15 Bit name Reset Access 0 R 14 12 G10 G10 G10 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group 11 interrupt control register Register symbol: G11ICR Address: x'3400012C This register is used to enable group 11 interrupts, and to confirm interrupt requests and detection. Purpose: Bit No. 15 Bit name Reset Access 0 R 14 13 12 G11 G11 G11 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group 12 interrupt control register Register symbol: G12ICR Address: x'34000130 This register is used to enable group 12 interrupts, and to confirm interrupt requests and detection. Purpose: Bit No. 15 Bit name Reset Access 0 R 14 12 G12 G12 G12 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group 13 interrupt control register Register symbol: G13ICR Address: x'34000134 This register is used to enable group 13 interrupts, and to confirm interrupt requests and detection. Purpose: Bit No. 15 Bit name Reset Access 0 R 14 13 12 G13 G13 G13 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group 14 interrupt control register Register symbol: G14ICR Address: x'34000138 This register is used to enable group 14 interrupts, and to confirm interrupt requests and detection. Purpose: Bit No. 15 Bit name Reset Access 0 R 14 12 G14 G14 G14 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group 15 interrupt control register Register symbol: G15ICR Address: x'3400013C This register is used to enable group 15 interrupts, and to confirm interrupt requests and detection. Purpose: Bit No. 15 Bit name Reset Access 0 R 14 13 12 G15 G15 G15 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group 16 interrupt control register Register symbol: G16ICR Address: x'34000140 This register is used to enable group 16 interrupts, and to confirm interrupt requests and detection. Purpose: Bit No. 15 Bit name Reset Access 0 R 14 12 G16 G16 G16 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group 17 interrupt control register Register symbol: G17ICR Address: x'34000144 This register is used to enable group 17 interrupts, and to confirm interrupt requests and detection. Purpose: Bit No. 15 Bit name Reset Access 0 R 14 13 12 G17 G17 G17 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group 18 interrupt control register Register symbol: G18ICR Address: x'34000148 This register is used to enable group 18 interrupts, and to confirm interrupt requests and detection. Purpose: Bit No. 15 Bit name Reset Access 0 R 14 12 G18 G18 G18 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Group 19 interrupt control register Register symbol: G19ICR Address: x'3400014C This register is used to enable group 19 interrupts, and to confirm interrupt requests and detection. Purpose: Bit No. 15 Bit name Reset Access 0 R 14 13 12 G19 G19 G19 LV2 LV1 LV0 0 0 0 R/W R/W R/W Bit No.
Interrupt Controller Interrupt accepted group register Register symbol: IAGR Address: x'34000200 Purpose: This register is used to read the group number that generated the interrupt request. Bit No. Bit name Reset Access Bit No.
Interrupt Controller External interrupt condition specification register Register symbol: EXTMD Address: x'34000280 Purpose: This register specifies the external interrupt generation conditions. Set the desired level or edge for each pin. Bit No.
Interrupt Controller 9.6 Description of Operation The following interrupt processing is performed. • Non-maskable interrupts NMIRQ pin interrupt Watchdog timer overflow interrupt System error interrupt • Level interrupts • Internal interrupts Peripheral interrupts from timer, serial, A/D • External interrupts External pin interrupts x 8 In the event of a level interrupt, an interrupt group determination is made, and an interrupt request is sent to the CPU.
Interrupt Controller [Cautions] 1. Maintain external pin interrupt signals for at least 10, 5, or 2.5 SYSCLK cycles when nfr = (MCLK frequency/ SYSCLK frequency) = 1, 2, or 4, respectively. The interrupt cannot be detected if the signal is not maintained for at least that long. However, when recovering from HALT mode in response to an external pin interrupt signal, maintain the signal for at least 22, 11, or 5.5 SYSCLK cycles when nfr = 1, 2, or 4, respectively.
Interrupt Controller 9-32
10.
8-bit Timers 10.1 Overview This device has 12 reload timers built in. All are down counters that can be used as interval timers and event counters. Eight of the timers are also capable of PWM output. 10.2 Features The features of the 8-bit timers are described below. • Clock source: An internal clock or external clock can be selected as the clock source. (Timers 0 to B) • Internal clock: IOCLK, 1/8 IOCLK, 1/32 IOCLK, timer 0 to 3 underflow • External clock: Counts at the rising edge of the pin input.
8-bit Timers 10.3 Block Diagram Fig. 10-3-1 shows a block diagram for timers 0 to 3. Fig. 10-3-2 shows a block diagram for timers 4 to B. Figures 10-3-3 to 10-3-6 show connection diagrams for the 8-bit timers.
8-bit Timers Timer n (n = 4, 5, 6, 7, 8, 9, A, B) TMnIN0 TMnIN1 TMnIN2 TMnIN3 TMnIN4 TMnIN5 TMnIN6 TMnIN7 TMnCLK Clock output TMnBR base register TMnCI Cascaded signal from higher order timer Reload Count operation enabled TMnCO Load CK0 CK1 CK2 OM0 — OM1 CNE LDE Cascaded signal TMnBC Underflow TMnIRQ binary counter Underflow interrupt Output control TMnMD mode register TMnOUT Match Output waveform control Compare register Load Reload Compare register buffer TMnCMP Compare regis
8-bit Timers Reset Prescaler 1/32 IOCLK 1/8 TMPSCNT Prescaler control register TMnIN0 TMnIN1 TMnIN2 TMnIN4 TMnIN5 TMnIN6 Timer 0 Timer 1 Timer 2 Timer 3 Block Timer 0 to 3 TM0IRQ TM0IRQ Timer interrupt 0 TM1IRQ TM1IRQ Timer interrupt 1 TM2IRQ TM2IRQ Timer interrupt 2 TM3IRQ TM3IRQ Timer interrupt 3 TM0IN7 TM1IN7 TM2IN7 TM3IN7 I/O port block TM0OUT TM1OUT TM2OUT TM3OUT Edge detection Edge detection Edge detection Timer output selection register Edge detection TMOSL TMnIN0 TMnIN1 TMnIN2
TM2IRQ TM1IRQ TM0IRQ IOCLK/32 IOCLK/8 IOCLK 8-bit Timers TM0IO pin input TM0IN0 TM0IN1 TM0IN2 TM0IN3 TM0IN4 TM0IN5 TM0IN6 TM0IN7 TM1IO pin input TM1IN0 TM1IN1 TM1IN2 TM1IN3 TM1IN4 TM1IN5 TM1IN6 TM1IN7 TM2IO pin input TM2IN0 TM2IN1 TM2IN2 TM2IN3 TM2IN4 TM2IN5 TM2IN6 TM2IN7 TM3IO pin input TM3IN0 TM3IN1 TM3IN2 TM3IN3 TM3IN4 TM3IN5 TM3IN6 TM3IN7 TM0CI TM0IRQ Timer 0 TM0OUT TM0CLK TM0IRQ Timer interrupt 0 TM0OUT Timer output 0 TM0CO TM1CI TM1IRQ Timer 1 TM1OUT TM1CLK TM1IRQ Timer interrupt 1 T
TM2IRQ TM1IRQ TM0IRQ IOCLK/32 IOCLK/8 IOCLK 8-bit Timers TM4IO pin input TM4IN0 TM4IN1 TM4IN2 TM4IN3 TM4IN4 TM4IN5 TM4IN6 TM4IN7 TM5IO pin input TM5IN0 TM5IN1 TM5IN2 TM5IN3 TM5IN4 TM5IN5 TM5IN6 TM5IN7 TM6IO pin input TM6IN0 TM6IN1 TM6IN2 TM6IN3 TM6IN4 TM6IN5 TM6IN6 TM6IN7 TM7IO pin input TM7IN0 TM7IN1 TM7IN2 TM7IN3 TM7IN4 TM7IN5 TM7IN6 TM7IN7 TM4CI TM4IRQ Timer 4 TM4OUT TM4CLK TM4IRQ Timer interrupt 4 TM4OUT Timer output 4 TM4CO TM5CI TM5IRQ Timer 5 TM5OUT TM5CLK TM5IRQ Timer interrupt 5 T
TM3IRQ TM1IRQ TM0IRQ IOCLK/32 IOCLK/8 IOCLK 8-bit Timers TM0IO pin input TM8IN0 TM8IN1 TM8IN2 TM8IN3 TM8IN4 TM8IN5 TM8IN6 TM8IN7 TM1IO pin input TM9IN0 TM9IN1 TM9IN2 TM9IN3 TM9IN4 TM9IN5 TM9IN6 TM9IN7 TM2IO pin input TMAIN0 TMAIN1 TMAIN2 TMAIN3 TMAIN4 TMAIN5 TMAIN6 TMAIN7 TM3IO pin input TMBIN0 TMBIN1 TMBIN2 TMBIN3 TMBIN4 TMBIN5 TMBIN6 TMBIN7 TM8CI TM8IRQ Timer 8 TM8OUT TM8CLK TM8IRQ Timer interrupt 8 TM8OUT Timer output 8 TM8CO TM9CI TM9IRQ Timer 9 TM9OUT TM9CLK TM9IRQ Timer interrupt 9 T
8-bit Timers 10.4 Functions Table 10-4-1 lists the functions of each 8-bit timer.
8-bit Timers 10.5 Description of Registers Table 10-5-1 lists the 8-bit timer registers.
8-bit Timers Table 10-5-1 List of 8-bit Timer Registers (2/2) Address Name Symbol Number of bits Initial value Access size x'34001034 Timer 4 compare register TM4CMP 8 x'00 8, 16, 32 x'34001035 Timer 5 compare register TM5CMP 8 x'00 8 x'34001036 Timer 6 compare register TM6CMP 8 x'00 8, 16 x'34001037 Timer 7 compare register TM7CMP 8 x'00 8 x'34001038 Timer 8 compare register TM8CMP 8 x'00 8, 16, 32 x'34001039 Timer 9 compare register TM9CMP 8 x'00 8 x'3400103A Timer A com
8-bit Timers Timer n mode register (n = 0, 1, 2, 3) Register symbol: TMnMD Address: x'34001000 (n=0), x'34001001 (n=1), x'34001002 (n=2), x'34001003 (n=3) Purpose: This register controls the operation of timer n. Bit No. Bit name Reset Access Bit No.
8-bit Timers Timer n mode register (n = 4, 5, 6, 7, 8, 9, A, B) Register symbol: TMnMD Address: x'34001004 (n=4), x'34001005 (n=5), x'34001006 (n=6), x'34001007 (n=7), x'34001008 (n=8), x'34001009 (n=9), x'3400100A (n=A), x'3400100B (n=B) Purpose: This register controls the operation of timer n. Bit No. 7 6 5 4 3 2 1 0 Bit name Reset TMn TMn TMn TMn CNE LDE OM1 OM0 0 0 0 0 0 TMn TMn TMn CK2 CK1 CK0 0 0 0 Access R/W R/W R/W R/W R R/W R/W R/W Bit No.
8-bit Timers [Note] When setting TMnCNE to "1", do so while TMnLDE is set to "0". When setting TMnLDE to "1", do so while TMnCNE is set to "0". Operation is not guaranteed if TMnCNE and TMnLDE are both set to "1" at the same time.
8-bit Timers Table 10-5-3 TMnCK[2:0] Setting Timer 0 8-bit Timer Clock Sources Timer 1 Timer 2 Timer 3 000 IOCLK IOCLK IOCLK IOCLK 001 IOCLK/8 IOCLK/8 IOCLK/8 IOCLK/8 010 IOCLK/32 IOCLK/32 IOCLK/32 IOCLK/32 011 Setting prohibited Cascaded with timer 0 Cascaded with timer 1 Cascaded with timer 2 100 Setting prohibited Timer 0 underflow Timer 0 underflow Timer 0 underflow 101 Timer 1 underflow Setting prohibited Timer 1 underflow Timer 1 underflow 110 Timer 2 underflow T
8-bit Timers Timer n base register (n = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B) Register symbol: TMnBR Address: x'34001010 (n = 0), x'34001011 (n = 1), x'34001012 (n = 2), x'34001013 (n = 3), x'34001014 (n = 4), x'34001015 (n = 5), x'34001016 (n = 6), x'34001017 (n = 7), x'34001018 (n = 8), x'34001019 (n = 9), x'3400101A (n =A), x'3400101B (n = B) Purpose: This register sets the initial value of the timer n binary counter and the underflow cycle. Bit No.
8-bit Timers Timer n compare register (n = 4, 5, 6, 7, 8, 9, A, B) Register symbol: TMnCMP Address: x'34001034 (n = 4), x'34001035 (n = 5), x'34001036 (n = 6), x'34001037 (n = 7), x'34001038 (n = 8), x'34001039 (n = 9), x'3400103A (n = A), x'3400103B (n = B) Purpose: This is the timer n compare register. Bit No.
8-bit Timers Timer output selection register Register symbol: TMOSL Address: x'34001070 Purpose: This register selects the 8-bit timer output signal. Bit No. Bit name Reset Access 7 6 5 4 - - - - 0 R 0 R 0 R 0 R Bit No. 0 Bit name TMOSL0 1 TMOSL1 2 TMOSL2 3 TMOSL3 7 to 4 — 10-18 3 2 1 0 TM TM TM TM OSL3 OSL2 OSL1 OSL0 0 0 0 0 R/W R/W R/W R/W Description Timer output selection flag 0 Selects the output signal for the TM0IO pin. 0: Selects the timer 0 output.
8-bit Timers Prescaler control register Register symbol: TMPSCNT Address: x'34001071 Purpose: This register controls the prescaler operation. Bit No. Bit name Reset Access Bit No. 6 to 0 7 7 TMPS CNE 0 R/W 6 5 4 3 2 1 0 - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit name – TMPSCNE Description "0" is returned when these bits are read. Prescaler operation enable flag. Enables/disables operation of the 1/8 IOCLK and 1/32 IOCLK prescaler.
8-bit Timers 10.6 Description of Operation This section describes the operation of the 8-bit timers. 10.6.1 Interval Timers and Timer Output When using an 8-bit timer as an interval timer, make the appropriate settings according to the procedure described below. The timer in question then operates as an interval timer that generates interrupts on the set cycle. (Refer to Figs. 10-6-1 to 10-6-3.) When using the timers as a 16-, 24- or 32-bit timer by means of a cascaded connection, refer to section 10.6.
8-bit Timers (6) Enable the timer counting operation. Once TMnCNE is set to "1" in the TMnMD register, the counting operation starts. Once the counting operation is enabled, an underflow interrupt request is generated at fixed intervals. In addition, the pin output is inverted each time that this interrupt is generated, and the value that is set in TMnBR is loaded into TMnBC.
8-bit Timers TMnBC value TMnBR setting value TMnCNE Interrupt request Timer output Fig 10-6-1 Interval Timer Operation IOCLK TMnBC value x'01 x'00 TMnBR value TMnBR value-1 x'00 TMnBR value TMnBR value-1 Interrupt request signal (TMnIRQ) Timer output (TMnOUT) (value in TMnBR + 1) x IOCLK Fig 10-6-2 Interval Timer Operation (When Clock Source = IOCLK) 10-22
8-bit Timers IOCLK Counter clock TMnBC value x'01 x'00 TMnBR value TMnBR value-1 TMnBR value-2 Interrupt request signal (TMnIRQ) Timer output (TMnOUT) Fig.
8-bit Timers 10.6.2 Event Counting When using an 8-bit timer for event counting, make the settings according to the procedure described below. When using the timers as a 16-, 24- or 32-bit timer by means of a cascaded connection, refer to section 10.6.3, "Cascaded Connection." ■ Procedure for initiating operation (1) Set the timer division ratio. Set the division ratio in TMnBR. An interrupt request is then generated when the rising edge on the pin input is counted (value set in TMnBR + 1) times.
8-bit Timers [Note] Pin input is sampled according to IOCLK. Input a signal with a pulse width of at least 6, 3, or 1.5 SYSCLK cycles when (MCLK frequency/SYSCLK frequency) = 1, 2, or 4, respectively. Event counting is not possible when IOCLK is stopped (in HALT or STOP mode). IOCLK Pin input (TMnIO) Count clock TMnBC value x'01 x'00 TMnBR value TMnBR value-1 Interrupt request signal (TMnIRQ) Fig.
8-bit Timers 10.6.3 Cascaded Connection The 8-bit timers can be cascaded together in the combinations shown in Fig. 10-6-5.
8-bit Timers Make the settings described below when cascading 8-bit timers. (1) Set the timer division ratio. Set the timer division ratio in TMnBR. (Example 1) When using timers 0 and 1 as 16-bit timers and setting the interrupt cycle to x'1234: In order to set the interrupt cycle to x'1234, x'1234 - 1 = x'1233 must be set in TMnBR. Set x'33 in the low-order byte, TM0BR, and x'12 in the high-order byte, TM1BR.
8-bit Timers (4) Enable counting operation Enable the counting operation by either one of the following two methods: 1) Enable the counting operation for each of the cascaded timers one at a time, in order, starting from the highest timer. 2) Enable the counting operation for all of the cascaded timers simultaneously.
8-bit Timers Differences between using a timer as a prescaler and when cascaded The following explanation of these differences uses the cases where the clock source for timer 1 is set to "timer 0 underflow" and to "cascaded with timer 0" as examples. When "timer 0 underflow" is set, operation is as shown in Fig. 10-6-6. (IOCLK is selected as the clock source for timer 0.) When TM0BC underflows, the value that is set in TM0BR is loaded into TM0BC, and the value in TM1BC is decremented by one.
8-bit Timers When "cascaded with timer 0" is set, operation is as shown in Fig. 10-6-7. (IOCLK is selected as the clock source for timer 0.) If TM1BC does not equal x'00, then when TM0BC underflows, the value in TM0BC is x'FF and the value in TM1BC is decremented by one. If TM1BC does equal x'00, then when TM0BC underflows, the values that are set in TM0BR and TM1BR are loaded into TM0BC and TM1BC, respectively, and a timer 1 interrupt request is generated.
8-bit Timers 10.6.4 PWM Output Make the settings as described below when using an 8-bit timer to output a PWM waveform. (Timers 4 to B) The timers cannot be cascaded when outputting a PWM waveform. ■ Procedure for initiating operation (1) Set the PWM output cycle. Set the cycle in TMnBR. The PWM output cycle is: (value set in TMnBR + 1) x clock source cycle (2) Set the PWM output duty ratio. Set the duty ratio in TMnCMP.
8-bit Timers Once the counting operation is enabled, the PWM waveform is output and an underflow interrupt request is generated. (Refer to Fig. 10-6-8 and 10-6-9.) If the value in the TMnBR register is changed while the counting operation is in progress, that value is loaded as the initial value when the next underflow is generated, and the cycle of the PWM waveform changes.
8-bit Timers IOCLK x'00 TMnBR value TMnCMP value x'00 TMnBR value TMnBC value Interrupt request signal (TMnIRQ) Timer output (TMnOUT) TMnCMP value x IOCLK (TMnBR value +1) x IOCLK Fig. 10-6-8 PWM Output (When Clock Source = IOCLK, and "L" Level Is Output Upon Initialization) IOCLK Counter clock x'00 TMnBR value TMnCMP value x'00 TMnBR value TMnBC value Interrupt request signal (TMnIRQ) Timer output (TMnOUT) TMnCMP value x counter clock (TMnBR value + 1) x counter clock Fig.
8-bit Timers 10-34
11.
16-bit Timers 11.1 Overview This microcontroller has four 16-bit timers built in. Three are reload timers (down-counters) that can be used as interval timers or event counters. The other is an up-counter that has two compare/capture registers built in. 11.2 Features The features of the 16-bit timers are described below. Timer 10 • Up-counter • Clock sources An internal clock or an external clock can be selected as the clock source.
16-bit Timers 11.3 Block Diagram Fig. 11-3-1 shows the block diagram for timer 10, and Fig. 11-3-2 shows the block diagram for timers 11 to 13. Timer 10 TM10IN0 TM10IN1 TM10IN2 TM10IN4 TM10IN5 TM10IN6 TM10IN7 TM10BC TM10IRQ Binary counter Capture Overflow interrupt Match TM10AIRQ TM10INB TM10CA Compare/capture A register Capture Match TM10BIRQ Compare/capture interrupt B TM10CB Compare/capture B register Fig.
16-bit Timers Timer n (n = 11, 12, 13) TMnIN0 TMnIN1 TMnIN2 TMnIN4 TMnIN5 TMnIN6 TMnIN7 TMnBR Base register Counting operation enable CK1 CK0 — CK2 — LDE — CNE Load Reload TMnBC Underflow TMnIRQ Binary counter Underflow interrupt TMnMD T Q Mode register TMnOUT Timer output R Reset Fig.
Timer 2 underflow Timer 1 underflow Timer 0 underflow 16-bit Timers Prescaler control register TMPSCNT Reset IOCLK prescaler 1/32 TM10IN0 TM10IN1 TM10IN2 TM10IN4 TM10IN5 TM10IN6 TM10IN7 IOCLK 1/8 TM10IRQ TM10AIRQ Timer 10 TM10BIRQ Timer 10 overflow interrupt Timer 10 compare/capture A interrupt Timer 10 compare/capture B interrupt TM10OA TM10IA TM10IB I/O port block TM10IOA TM10OB Edge detection TM10IOB Edge detection TM11IN0 TM11IN1 TM11IN2 TM11IN4 TM11IN5 TM11IN6 TM11IN7 TM11IRQ Timer
16-bit Timers Fig. 11-3-4 shows the block diagram for the timer 10 compare/capture registers. Timer 10 compare/capture registers ( TM10CA, TM10CB ) TM10BC Binary counter Match interrupt request Capture timing Compare/capture A (B) register TM10CA (TM10CB) Capture enable Capture register mode Compare/capture register Double-buffer mode Load timing Single-buffer mode Initialization flag (TM10LDE) Compare register buffer Compare register mode Register read Register write Data bus Fig.
16-bit Timers 11.4 Functions Table 11-4-1 lists the functions of each 16-bit timer.
16-bit Timers 11.5 Description of Registers Table 11-5-1 lists the 16-bit timer registers.
16-bit Timers Timer 10 mode register Register symbol: TM10MD Address: x'34001080 Purpose: This register controls the operation of timer 10. Bit No. 15 14 13 12 11 Bit name Reset TM10 TM10 TM10 TM10 TM10 CNE LDE PME PM1 PM0 0 0 0 0 0 Access R/W R/W R/W R/W R/W Bit No.
16-bit Timers Bit No. 7 Bit name TM10TGE 10 to 8 11 12 — TM10PM0 TM10PM1 13 TM10PME 14 TM10LDE 15 TM10CNE Description External trigger start enable flag Enables/disables timer start by an external trigger. 0: Disables timer start by an external trigger. (The trigger input is ignored.) 1: Enables timer start by an external trigger. When the specified edge is input to the TM10IOB pin, the TM10CNE flag is set and the timer starts.
16-bit Timers Timer n mode register (n = 11, 12, 13) Register symbol: TMnMD Address: x'34001082 (n=11), x'34001084 (n=12), x'34001086 (n=13) Purpose: This register controls the operation of timer n. Bit No. 7 6 Bit name Reset TMn TMn CNE LDE 0 0 Access R/W R/W Bit No.
16-bit Timers Timer n base register (n = 11, 12, 13) Register symbol: TMnBR Address: x'34001092 (n=11), x'34001094 (n=12), x'34001096 (n=13) Purpose: This register sets the initial value and the underflow cycle for the timer n binary counter. Bit No.
16-bit Timers Timer 10 compare/capture A mode register Register symbol: TM10MDA Address: x'340010B0 Purpose: This register controls the operation of the timer 10 compare/capture A register. This register also sets the waveform that is output to the TM10IOA pin. Bit No. Bit name Reset Access 7 6 5 4 TM10 TM10 TM10 TM10 AM1 AM0 AEG ACE 0 0 0 0 R/W R/W R/W R/W Bit No.
16-bit Timers Timer 10 compare/capture B mode register Register symbol: TM10MDB Address: x'340010B1 Purpose: This register controls the operation of the timer 10 compare/capture B register. This register also sets the waveform that is output to TM10IOB pin. Bit No. Bit name Reset Access 7 6 5 4 TM10 TM10 TM10 TM10 BM1 BM0 BEG BCE 0 0 0 0 R/W R/W R/W R/W Bit No.
16-bit Timers Timer 10 compare/capture A register Register symbol: TM10CA Address: x'340010C0 Purpose: This is the timer 10 compare/capture A register. Bit No.
16-bit Timers Timer 10 compare/capture B register Register symbol: TM10CB Address: x'340010D0 Purpose: This is the timer 10 compare/capture B register. Bit No.
16-bit Timers Prescaler control register Register symbol: TMPSCNT Address: x'34001071 Purpose: This register controls prescaler operations. Bit No. 7 Bit name Reset TMPS CNE 0 Access R/W Bit No. 6 to 0 7 6 5 4 3 2 1 0 – – – – – – – 0 0 0 0 0 0 0 R R R R R R R Bit name — TMPSCNE Description "0" is returned when these bits are read. Prescaler operation enable flag Enables/disables 1/8 IOCLK and 1/32 IOCLK prescaler operation.
16-bit Timers 11.6 Description of Operation of Timer 10 This section describes the operation of timer 10. Timer 10 includes an up-counter and two compare/capture registers. The compare/capture registers are independent of each other, and can each be used as either a compare register or a capture register. 11.6.
16-bit Timers IOCLK TM10BC value (when TM10CAE = 1) TM10BC value (when TM10CAE = 0) TM10CA value-2 TM10CA value-1 TM10CA value TM10CA value-2 TM10CA value-1 TM10CA value x'0000 x'0001 TM10CA value+1 TM10CA value+2 x'0002 TM10CA value+3 Compare/capture A interrupt request Fig. 11-6-1 Compare Register Operation (When Clock Source = IOCLK) 11.6.
16-bit Timers If dual-edge was selected, the capture operation is performed when either a rising or falling edge is input. It is not possible to determine which edge was input. (The pin input level cannot be read.) The capture operation can be disabled even while counting is in progress by setting TM10ACE to "0". When TM10CAE is set to "1" in the TM10MD register and TM10CA is set as a capture register, TM10BC is cleared when the value is captured in TM10CA.
16-bit Timers 11.6.3 Pin Output Settings Timer 10 can be used to output a variety of waveforms to the TM10IOA and TM10IOB pins. (1) Setting the output level upon initialization If the TM10LDE flag in the TM10MD register is set to "1", thus initializing timer 10, the output level on the TM10IOA pin is the value that is set for the TM10AEG flag in the TM10MDA register. The output level on the TM10IOB pin is the value that is set for the TM10BEG flag in the TM10MDB register.
16-bit Timers Examples of TM10IOA pin output waveforms are shown below. Output for the TM10IOB pin is similar. Fig. 11-6-3 shows the output waveform for the TM10IOA pin when "Set when TM10BC matches TM10CA, and reset when TM10BC matches TM10CB" is set. If the set and reset conditions occur simultaneously, the reset takes precedence. TM10CNE Match between TM10BC and TM10CA Match between TM10BC and TM10CB TM10IOA pin output (when TM10AEG = 0) TM10IOA pin output (when TM10AEG = 1) Fig.
16-bit Timers Fig. 11-6-5 shows the output waveform for the TM10IOA pin when "Set when TM10BC matches TM10CA" is set. Match between TM10BC and TM10CA TM10IOA pin output (when TM10AEG = 0) Don' t Care TM10IOA pin output (when TM10AEG = 1) Don' t Care Fig. 11-6-5 Pin Output Waveform (3) Fig. 11-6-6 shows the output waveform for the TM10IOA pin when "Reset when TM10BC matches TM10CA" is set.
16-bit Timers 11.6.4 Starting by an External Trigger Timer 10 can be started up by input on the TM10IOB pin. Fig. 11-6-8 illustrates the startup operation. The compare/capture A and B registers can be used as compare registers or as capture registers. ■ Procedure for initiating operation (1) Select the input edge on which timer 10 is to start. Select the input edge through TM10BEG in the TM10MDB register. The starting edge is the opposite of the normal setting.
16-bit Timers ■ Procedure for ending operation (1) Disable timer startup by an external trigger. Set TM10TGE in the TM10MD register to "0". (2) Stop the counting operation. Set TM10CNE in the TM10MD register to "0". If TM10TGE and TM10CNE are both set to "0" simultaneously, there is a possibility that TM10CNE will be set again, depending on the pin input timing. Therefore, always be sure to set TM10TGE to "0" first, and then set TM10CNE to "0".
16-bit Timers 11.6.5 One-shot Operation It is possible to stop timer 10 when TM10BC and TM10CA match. Figs. 11-6-9 and 11-6-10 illustrate the operation that stops timer 10. The compare/capture B register can be used as a compare register or as a capture register. ■ Procedure for initiating operation (1) Set the compare/capture A register mode.
16-bit Timers ■ Procedure for ending operation • When the timer was started by a program (TM10TGE = 0) (1) Stop the counting operation. Set TM10CNE in the TM10MD register to "0". • When the timer was started by an external trigger (TM10TGE = 1) (1) Disable timer startup by an external trigger. Set TM10TGE in the TM10MD register to "0". (2) Stop the counting operation. Set TM10CNE in the TM10MD register to "0".
16-bit Timers 11.6.6 Interval Timer When using timer 10 as an interval timer, make the settings according to the procedure described below. This interval timer generates a compare/capture A interrupt request on the cycle that is set. (Refer to Figs. 11-6-11 to 11-6-14.) The compare/capture B register can be used as a compare register or as a capture register. Note: For details on the settings, refer to section 11.6.1, "Compare Register Settings," or section 11.6.2, "Capture Register Settings.
16-bit Timers If the value in the TM10CA register is changed while the counting operation is in progress, the value in the buffer is loaded into the compare register the next time that TM10BC is cleared, and the interrupt cycle is then changed. If the interrupt cycle will be changed while the counting operation is in progress, set TM10CA as a double-buffer compare register. ■ Procedure for ending operation (1) Stop the timer counting operation.
16-bit Timers IOCLK TM10BC value x'0000 x'0001 TM10CA value-1 TM10CA value x'0000 x'0001 Compare/capture A interrupt request (TM10CA value + 1) x IOCLK Compare/capture A register (TM10CA) Set value 1 Compare register A buffer Set value 1 Fig. 11-6-13 Set value 2 Set value 2 If “double-buffer” is set, the set value is loaded from the buffer at the same time that TM10BC is cleared.
16-bit Timers 11.6.7 Event Counting When using timer 10 as an event counter, make the settings according to the procedure described below. This event counter generates a compare/capture A interrupt when it has counted the specified number of edges. (Refer to Fig. 11-6-15.) The compare/capture B register can be used as a compare register or as a capture register. Note: For details on the settings, refer to section 11.6.1, "Compare Register Settings.
16-bit Timers Once the counting operation is enabled, TM10BC is incremented each time that the specified edge is input to the TM10IOB pin. Once (value in compare/capture A register + 1) edges are counted, TM10BC is cleared and a compare/capture A register interrupt request is generated.
16-bit Timers 11.7 Description of Operation of Timers 11, 12, and 13 This section describes the operation of timers 11, 12, and 13. Timers 11, 12, and 13 have built-in registers for setting the initial values, and down-counters. These timers can be used as interval timers and as event counters. 11.7.1 Interval Timer and Timer Output When using timers 11, 12, or 13 as an interval timer, make the settings according to the procedure described below.
16-bit Timers Once the counting operation is enabled, an underflow interrupt request is generated on a regular cycle. In addition, with each interrupt the pin output is inverted and the value in TMnBR is loaded into TMnBC. If the value in the TMnBR register is changed while the counting operation is in progress, this changed value is loaded as the initial value the next time that an underflow is generated, and the interrupt cycle is then changed.
16-bit Timers IOCLK TMnBC value x'0001 x'0000 TMnBR value TMnBR value -1 x'0000 TMnBR value TMnBR value -1 Interrupt request signal (TMnIRQ) Timer output (TMnOUT) (TMnBR value +1) x IOCLK Fig. 11-7-2 Interval Timer Operation (When Clock Source = IOCLK) IOCLK Count clock TMnBC value x'0001 x'0000 TMnBR value TMnBR value -1 TMnBR value -2 Interrupt request signal (TMnIRQ) Timer output (TMnOUT) Fig.
16-bit Timers 11.7.2 Event Counting When using timer 11, 12, or 13 as an event counter, make the settings according to the procedure described below. ■ Procedure for initiating operation (1) Set the timer division ratio. Set the division ratio in TMnBR. An interrupt request is then generated when the rising edge is counted (value set in TMnBR + 1) times in the pin input. (2) Select the clock source. Select the clock source through TMnCK[2:0] in the TMnMD register to "TMnIO pin input.
16-bit Timers [Note] The pin input is sampled according to IOCLK. Input a signal with a pulse width of at least 6, 3, or 1.5 SYSCLK cycles when (MCLK frequency/SYSCLK frequency) = 1, 2, or 4, respectively. Also note that event counting is not possible when IOCLK is stopped (in HALT or STOP mode). IOCLK Pin input (TMnIO) Count clock TMnBC value x'0001 x'0000 TMnBR value TMnBR value -1 Interrupt request signal (TMnIRQ) Fig.
16-bit Timers 11-38
12.
Watchdog Timer 12.1 Overview This microcontroller has a 25-bit binary counter built in that can be used as a 16- to 25-bit watchdog timer. A watchdog timer overflow generates a nonmaskable interrupt, enabling the watchdog timer overflow to be identified. The watchdog timer is also used as an oscillation stabilization wait timer. 12.2 Features • The number of bits in the binary counter is selectable.
Watchdog Timer 12.
Watchdog Timer 12.4 Description of Registers Table 12-4-1 lists the watchdog timer registers.
Watchdog Timer Watchdog timer control register Register symbol: WDCTR Address: x'34004008 Purpose: This register sets the watchdog timer operation control conditions. Bit No. Bit name Reset Access Bit No.
Watchdog Timer 3 4 5 — WDOVF WDOVT 6 WDRST 7 WDCNE When this bit is read, a "0" is returned. The value of the watchdog timer overflow output. Watchdog timer overflow output selection 0: Pulse output 1: Level output Binary counter reset, watchdog timer overflow output (WDOVF flag) reset 0: No reset 1: Reset When a "1" is written to this bit, the reset pulse is generated for the width of one clock pulse, and then this bit returns to "0". "0" is returned whenever this bit is read.
Watchdog Timer 12.5 Description of Operation Oscillation stabilization wait operation The watchdog timer operates as an oscillation stabilization wait timer after the reset state is released or when the microcontroller recovers from STOP mode (Fig. 12-5-1). The watchdog timer operates in this capacity even if the WDCNE flag is "0". When recovering from STOP mode, the watchdog timer operates as a counter of the number of bits specified by WDCK2 to 0 (Fig. 12-5-2).
Watchdog Timer Interrupt Stop mode release request (external pin interrupt) OSCI input SYSCLK Internal clock, SYSCLK supply enabled Overflow Watchdog timer count value Oscillation stabilization wait time 4.369 ms to 1118.481 ms (when CKSEL = “H” and the oscillating input frequency is 15 MHz) Fig.
Watchdog Timer Watchdog operation If the WDCNE flag is set to "1" and the watchdog operation is enabled, a non-maskable interrupt is generated if a watchdog timer overflow occurs. When an overflow occurs, the watchdog timer overflow output is output to the WDOVF flag. Pulse output or level output can be selected through the WDOVT flag. When level output is selected, the watchdog timer overflow output (WDOVF flag) is cleared by writing a "1" to the WDRST flag or by reset (RST) pin "L" level input.
Watchdog Timer 12-10
13.
Serial Interface 13.1 Overview This microcontroller has three types of internal serial interfaces. One is a general-purpose serial interface for which clock synchronous mode, UART mode, or I2C mode can be specified; this interface supports one channel. The second interface is a clock synchronous serial interface that supports two channels. The third interface is UART serial interface that supports one channel.
Serial Interface 13.2 General-purpose serial interface 13.2.1 Features Serial interface 0 is a general-purpose serial interface for which clock sync mode, UART mode, or I2C mode can be specified. The features of each mode are described below.
Serial Interface • Parity None, 0 fixed, 1 fixed, even, odd • Character length 7 bits, 8 bits • Transmission and reception bit sequence LSB or MSB selectable • Clock source 1/8 or 1/32 of IOCLK 1/8 of timer 3 or timer 9 underflow 1/8 of external clock • Maximum bit rate 19.
Serial Interface 13.2.2 Block Diagram of General-Purpose Serial Interface Fig 13-2-1 shows the block diagram for the general-purpose serial interface section.
Serial Interface 13.2.3 Description of Registers for the General-Purpose Serial Interface The general-purpose serial interface includes the registers listed in Table 13-2-1. These registers are used for settings such as clock source selection, parity bit selection, and protocol selection.
Serial Interface 6 SC0PB2 7 SC0CLN 8 SC0TOE 9 SC0OD 10 11 SC0MD0 SC0MD1 12 SC0IIC 13 SC0BKE 14 SC0RXE 15 SC0TXE Parity bit selection (MSB) 000: None 001, 010, 011: Setting prohibited 100: 0 fixed 101: 1 fixed 110: Even (even number of ones) 111: Odd (odd number of ones) Character length selection 0: 7 bits 1: 8 bits SBT0 pin output control 0: When the internal clock is selected, the SBT0 pin is an output only while transmission is in progress (the SBT0 pin is an input when in standby mode
Serial Interface Serial 0 interrupt mode register Register symbol: SC0ICR Address: x'34000804 Purpose: This register selects the sources for transmission interrupts and reception interrupts for serial interface 0. Bit No. 7 Bit name Reset SC0 DMD 0 6 5 - - 0 0 Access R/W R 4 SC0 TI 0 R/W R/W Bit No.
Serial Interface Serial 0 reception buffer Register symbol: SC0RXB Address: x'34000809 Purpose: This register reads in the reception data of serial interface 0. Bit No. Bit name Reset Access 7 6 5 4 3 2 1 0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 0 0 0 0 0 0 0 0 R R R R R R R R Reception data is gotten by reading this buffer at the end of reception. In the case of a 7-bit transfer, the MSB (bit 7) is "0".
Serial Interface 13.2.4 Description of Operation ■ Clock synchronous mode connection Two different connection methods are possible, one for unidirectional transfer, and the other for bi-directional transfer. When SBT pin is an output only during transmission (SC0TOE = "0"), it is necessary to pull up SBT pin. In addition, when using SBO pin as a data input/output (SC0MD1 and 0 = "11"), it is necessary to pull up SBO pin. Connect a pull-up resistor externally.
Serial Interface ■ Clock synchronous mode timing • One-byte transfer with 8-bit data length and parity on SBO pin bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 PTY SBT pin Data write SC0TXF flag SC0TBF flag Interrupt request (when set to “transmission end”) Interrupt request (when set to “transmission buffer empty”) Fig.
Serial Interface • One-byte transfer with 8-bit data length and parity on SBI pin bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 PTY SBT pin SC0RXF flag SC0RBF flag Interrupt request Data read Fig. 13-2-5 Timing Chart (3) • Two-byte transfer with 8-bit data length and parity off SBI pin bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 SBT pin SC0RXF flag SC0RBF flag Interrupt request Data read Fig.
Serial Interface ■ When a reception error is generated • Transfer in clock synchronous mode with 8-bit data length, parity on. SBI pin bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 PTY SBT pin SC0RXF flag SC0RBF flag “H” SC0OEF flag SC0PEF flag Interrupt request Fig. 13-2-7 Timing Chart (5) When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends, regardless of whether or not an error occurred.
Serial Interface ■ UART mode connection Two different connection methods are possible, one for unidirectional transfer, and the other for bi-directional transfer. The SBO pin is always an output, and the SBI pin is always an input. SBO SBO SBO SBO SBI SBI SBI SBI SBT SBT Transmission External clock SBT Reception Transmission/ reception Undirectional transfer SBT External clock Transmission/ reception Bi-directional transfer Fig.
Serial Interface Table 13-2-2 Bit rates (1) (When IOCLK = 15 MHz) Bit rate (bit/s) 19 200 9 600 4 800 2 400 1 200 When cascaded Timer division ratio Bit rate error 98 195 391 781 1 563 0.35 % 0.16 % 0.10 % 0.03 % 0.03 % When using prescalers Timer division ratio Bit rate error Not using Not using 195 x 2 195 x 4 195 x 8 — — 0.16 % 0.16 % 0.
Serial Interface ■ UART mode timing • Transfer with 8-bit data length, parity on, and 1 stop bit SBO pin ST bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 PTY SP Data write SC0TXF flag SC0TBF flag Interrupt request (when set to “transmission end”) Interrupt request (when set to “transmission buffer empty”) Fig.
Serial Interface • Transfer with 8-bit data length, parity on, and 1 stop bit SBI pin ST bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 PTY SP SC0RXF flag SC0RBF flag Interrupt request Data read Fig. 13-2-11 Timing Chart (8) • Two-byte transfer with 7-bit data length, parity on, and 1 stop bit SBI pin ST bp0 bp1 bp2 bp3 bp4 bp5 bp6 PTY SP ST bp0 bp1 bp2 bp3 bp4 bp5 bp6 PTY SP SC0RXF flag SC0RBF flag Interrupt request Data read Fig.
Serial Interface ■ When a reception error is generated • Transfer in UART mode with 8-bit data length, parity on, and 1 stop bit ST SBI pin bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 PTY SP SC0RXF flag SC0RBF flag “H” SC0OEF flag SC0PEF flag SC0FEF flag Interrupt request Fig. 13-2-13 Timing Chart (10) When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends, regardless of whether or not an error occurred.
Serial Interface ■ I2C mode connection It is possible to connect a device that is capable of slave transmission and slave reception. SDA and SCL require pull-up resistors. Connect pull-up resistors externally. The SBO pin is an open-drain input/output, and the SBT pin is an open drain output. SDA SBO SBI SBT Master transmission/ reception SCL Slave transmission/reception Slave transmission/reception Fig.
Serial Interface ■ I2C mode transmission/reception The transmission/reception procedure in I2C mode is described below. (Refer to Fig. 13-2-15.) • Make the initial settings as described below. (1) I/O port setting Set the SBT and SBO pins as general-purpose input ports. For details on the settings, refer to the chapter on I/O ports. (2) Transmission/reception mode setting (SC0CTR register) Be certain to set the flags listed below to the specified values.
Serial Interface • Perform data transmission/reception (B) according to the procedure described below: (1) Ack setting "Ack" is represented by the parity bits. Set the parity bit selection flags (SC0PB2 to 0) to "1 fixed" or "0 fixed" in accordance with the communications protocol for the device that is connected. (When sending "Ack", set "0 fixed"; when sending NO-Ack, set "1 fixed ".
Serial Interface If the above procedures do not satisfy the AC timing of the device that is connected, send the stop sequence according to the procedure described below. (1)' SBT pin setting Set the SBT pin as a general-purpose input port. When the pin switches to a general-purpose input port, SCL goes high. (2)' SBO pin setting Set the SBO pin as a general-purpose input port. When the pin switches to a general-purpose input port, SDA goes high and the stop sequence is generated.
Serial Interface • Resend the start sequence (D) according to the procedure described below. (Refer to Fig. 13-2-16.) (1) SBO pin setting Set the SBO pin as a general-purpose input port. When the pin switches to a general-purpose input port, SDA goes high. (2) SBT pin setting Set the SBT pin as a general-purpose input port. When the pin switches to a general-purpose input port, SCL goes high. (3) Control register setting Disable the transmission operation and the reception operation.
Serial Interface 13.3 Clock Synchronous Serial Interface 13.3.1 Features Serial interfaces 1 and 2 are clock synchronous serial interfaces. Their features are described below.
Serial Interface 13.3.2 Block Diagram of Clock Synchronous Serial Interface Fig 13-3-1 shows the block diagram for the clock synchronous serial interface sections. I/O Port Block Serial interface n (n = 1, 2) Transmission buffer write Set the serial signals in the I/O port control register. However, some pins may need to be set as general-purpose inputs, depending on the transmission/reception procedure.
Serial Interface 13.3.3 Description of Registers for the Clock Synchronous Serial Interface The clock synchronous serial interfaces include the registers listed in Table 13-3-1. These registers are used for settings such as clock source selection, parity bit selection, and protocol selection.
Serial Interface Serial n control register (n = 1, 2) Register symbol: SCnCTR Address: x'34000810 (n =1), x'34000820 (n =2) Purpose: This register sets the serial interface n operation control conditions. Bit No. Bit name Reset Access 15 14 SCn SCn TXE RXE 0 0 R/W R/W Bit No.
Serial Interface Bit No.
Serial Interface Serial n interrupt mode register (n = 1, 2) Register symbol: SCnICR Address: x'34000814 (n = 1), x'34000824 (n = 2) Purpose: This register selects the sources for transmission interrupts and reception interrupts for serial interface n. Bit No. 7 Bit name Reset SCn DMD 0 6 Access R/W 5 – – 0 0 R 4 SCn TI 0 R/W R/W Bit No.
Serial Interface Serial n transmission buffer (n = 1, 2) Register symbol SCnTXB Address: x'34000818 (n=1), x'34000828 (n=2) Purpose: This register writes the transmission data to serial interface n. Bit No. Bit name Reset Access 7 6 5 4 3 2 1 0 SCn SCn SCn SCn SCn SCn SCn SCn TXB7 TXB6 TXB5 TXB4 TXB3 TXB2 TXB1 TXB0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Data is transmitted by writing it to this buffer.
Serial Interface Serial n status register (n=1,2) Register symbol: SCnSTR Address: x'3400081C (n=1), x'3400082C (n=2) Purpose: This register indicates the status of serial interface n. Bit No. Bit name Reset Access 7 6 5 4 SCn SCn SCn SCn TXF RXF TBF RBF 0 0 0 0 R R R R Bit No.
Serial Interface 13.3.4 Description of Operation ■ Clock synchronous serial interface n connection (n=1,2) Two different connection methods are possible, one for unidirectional transfer, and the other for bi-directional transfer. When SBT pin is an output only during transmission (SCnTOE = "0"), it is necessary to pull up SBT pin. In addition, when using SBO pin as a data input/output (SCnMD0 = "1"), it is necessary to pull up SBO pin. Connect a pull-up resistor externally.
Serial Interface ■ Clock synchronous serial interface timing • One-byte transfer with 8-bit data length and parity off SBO pin bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 SBT pin Data write SCnTXF flag SCnTBF flag Interrupt request (when set to “transmission end”) Interrupt request (when set to “transmission buffer empty”) Fig.
Serial Interface • One-byte transfer with 7-bit data length and parity on SBI pin bp0 bp1 bp2 bp3 bp4 bp5 bp6 PTY SBT pin SCnRXF flag SCnRBF flag Interrupt request Data read Fig. 13-3-5 Timing Chart (15) • Two-byte transfer with 8-bit data length and parity on SBI pin bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 PTYbp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 PTY SBT pin SCnRXF flag SCnRBF flag Interrupt request Data read Fig.
Serial Interface ■ When a reception error is generated • Transfer with 7-bit data length, parity on SBI pin bp0 bp1 bp2 bp3 bp4 bp5 bp6 PTY SBT pin SCnRXF flag SCnRBF flag “H” SCnOEF flag SCnPEF flag Interrupt request Fig. 13-3-7 Timing Chart (17) When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends, regardless of whether or not an error occurred.
Serial Interface 13.4 Universal Asynchronous Receiver-Transceiver Serial Interface 13.4.1 Features Serial interface 3 is a UART serial interface. Its features are described below.
Serial Interface 13.4.2 Block Diagram of UART Serial Interface Fig 13-4-1 shows the block diagram for the UART serial interface sections. I/O Port Block Serial interface 3 IRQ7 Transmission buffer write When using IRQ7, digital input must be selected.
Serial Interface 13.4.3 Description of Registers for the UART Serial Interface The UART serial interface includes the registers listed in Table 13-4-1. These registers are used for settings such as clock source selection, parity bit selection, and protocol selection.
Serial Interface Serial 3 control register Register symbol: SC3CTR Address: x'34000830 Purpose: This register sets the serial interface 3 operation control conditions. Bit No. Bit name Reset Access 15 14 13 12 SC3 SC3 SC3 SC3 TXE RXE BKE TWS 0 0 0 0 R/W R/W R/W R/W Bit No.
Serial Interface Bit No.
Serial Interface Serial 3 interrupt mode register Register symbol: SC3ICR Address: x'34000834 Purpose: This register selects the sources for transmission interrupts and reception interrupts for serial interface 3. Bit No. Bit name Reset Access 7 6 5 – – – 0 0 0 R R 4 SC3 TI 0 R/W R/W Bit No.
Serial Interface Serial 3 transmission buffer Register symbol: SC3TXB Address: x'34000838 Purpose: This register writes the transmission data of serial interface 3. Bit No. Bit name Reset Access 7 6 5 4 3 2 1 0 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 TXB7 TXB6 TXB5 TXB4 TXB3 TXB2 TXB1 TXB0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Data is transmitted by writing it to this buffer.
Serial Interface Serial 3 status register Register symbol: SC3STR Address: x'3400083C Purpose: This register indicates the status of serial interface 3. Bit No. Bit name Reset Access 7 6 SC3 SC3 TXF RXF 0 0 R R 5 4 SC3 SC3 TBF RBF 0 0 R R Bit No.
Serial Interface Serial 3 timer register Register symbol: SC3TIM Address: x'3400083D Purpose: This register sets the timer that is used for internal division for serial interface 3. Bit No. Bit name Reset Access 7 – 0 R 6 5 4 3 2 1 0 SC3 SC3 SC3 SC3 SC3 SC3 SC3 TIM6 TIM5 TIM4 TIM3 TIM2 TIM1 TIM0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Set the value that corresponds to the required division ratio - 1.
Serial Interface 13.4.4 Description of Operation ■ UART Serial Interface connection Two different connection methods are possible, one for unidirectional transfer, and the other for bi-directional transfer. The SBO pin is always an output, and the SBI pin is always an input. SBO SBO SBO SBO SBI SBI SBI SBI SBT SBT Transmission External clock SBT Reception Transmission/ reception Unidirectional transfer SBT External clock Transmission/ reception Bi-directional transfer Fig.
Serial Interface Division ratio 1 = INT (IOCLK frequency / bit rate/127) + 1 Division ratio 2 = INT (IOCLK frequency / bit rate/division ratio 1 + 0.5) Subtract 1 from the value for division ratio 2 that was derived through the above equations, and write the result in SC3TIM. If the value of division ratio 1 is 2 or higher, timer 2 or timer 8 must be used to divide the clock.
Serial Interface Table 13-4-3 Bit Rates (2) (When IOCLK = 12 MHz) Bit rate (bit/s) Division ratio 1 Division ratio 2 Bit rate error 230 400 1 52 0.16 % 115 200 1 104 0.16 % 56 000 2 107 0.13 % 38 400 3 104 0.16 % 19 200 5 125 0.00 % 9 600 10 125 0.00 % 4 800 20 125 0.00 % 2 400 40 125 0.00 % 1 200 79 127 0.33 % 600 158 127 0.33 % 300 315 127 0.01 % 150 630 127 0.
Serial Interface [Notes on Usage] 1 2 3 4 Set SC3CTR before setting the other registers, and do not change the setting while transmitting or receiving, or while there is data in the transmission buffer. Operation is not guaranteed if the setting of the SC3CTR register is changed. Before writing to the transmission buffer SC3TXB, confirm that the transmission buffer is empty.
Serial Interface ■ UART Serial Interface timing • Transfer with 7-bit data length, parity off, and 2 stop bit SBO pin ST bp0 bp1 bp2 bp3 bp4 bp5 bp6 SP SP Data write SC3TXF flag SC3TBF flag Interrupt request (when set to “transmission end”) Interrupt request (when set to “transmission buffer empty”) Fig.
Serial Interface • Transfer with 7-bit data length, parity on, and 2 stop bit SBI pin ST bp0 bp1 bp2 bp3 bp4 bp5 bp6 PTY SP SP SC3RXF flag SC3RBF flag Interrupt request Data read Fig. 13-4-5 Timing Chart (20) • Two-byte transfer with 8-bit data length, parity off, and 1 stop bit SBI pin ST bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 SP ST bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 SP SC3RXF flag SC3RBF flag Interrupt request Data read Fig.
Serial Interface ■ When a reception error is generated • Transfer with 7-bit data length, parity on, and 2 stop bit SBI pin ST bp0 bp1 bp2 bp3 bp4 bp5 bp6 PTY SP SP SC3RXF flag SC3RBF flag “H” SC3OEF flag SC3PEF flag SC3FEF flag Interrupt request Fig. 13-4-7 Timing Chart (22) When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends, regardless of whether or not an error occurred.
Serial Interface 13-52
14.
A/D Converter 14.1 Overview The A/D converter is a 10-bit charge redistribution-type A/D converter that can process analog signals on a maximum of four channels. The A/D conversion reference clock can be selected from 1/2, 1/4, 1/8, or 1/16 of IOCLK. When IOCLK = 10 MHz, A/D conversion is performed with a maximum conversion speed of 2.8 µs/ch. (1/2 x IOCLK is selected as the A/D conversion reference clock, and the number of sampling cycles is 2 cycles.
A/D Converter 14.2 Features • S/H Built in • Conversion accuracy 10 bits ± 5 LSB (Linearity error) The value of VREFH divided into 1024 steps is stored in AD0BUF to AD3BUF. • Conversion reference clock Selectable from 1/2, 1/4, 1/8, or 1/16 of IOCLK Set this parameter so that one cycle is at least 200 ns. (Example: When IOCLK is 15 MHz, set this parameter 1/4 or 1/8 or 1/16.) • Number of sampling cycles Select either two or four conversion reference clock cycles.
A/D Converter 14.3 Block Diagram AN0 512 AN2 128 64 32 16 8 4 2 1 1 Selector AN1 256 VREFH AN3 Shift registers for states ADnBUF A/D conversion trigger IOCLK Divider Data buffer selection Results writing Comparator For multiplechannel conversion MD0 MD1 CK0 CK1 ST0 SHC ST1 SC0 INC EN SC1 MC0 ADCTR MC1 Timer 2 underflow Conversion reference clock ADTRG Interrupt generator A/D interrupt request Fig.
A/D Converter 14.4 Description of Registers Table 14-4-1 lists the registers for this A/D converter.
A/D Converter 7 ADEN 8 ADSC0 9 ADSC1 10 11 12 13 — — ADMC0 ADMC1 14 15 — — Conversion start/execution flag (conversion can be started by writing a "1" to this flag) 0: Conversion stopped 1: Conversion start/in progress Selection of conversion channel when converting any one channel/ indicator of current conversion channel when converting multiple channels (LSB) Selection of conversion channel when converting any one channel/ indicator of current conversion channel when converting multiple channel
A/D Converter 14.5 Description of Operation ■ Operating mode selection (1) Any one channel/one-time conversion If "any one channel/one-time conversion" is selected as the operating mode (ADMD1 to 0), one AN input is converted one time only. Set the conversion channel in the conversion channel selection bits (ADSC1 to 0). (ADMC1 to 0 are ignored.) An A/D interrupt request is generated simultaneously with the completion of conversion.
A/D Converter (2) Multiple channels/one-time conversion for each channel If "multiple channels/one-time conversion for each channel" is selected as the operating mode (ADMD1 to 0), a number of AN inputs, starting from AN0, are converted one time only. Set channel 0 in the conversion channel selection bits used for converting any one channel (ADSC1 to 0), and set the number of channels to be converted in the conversion channel selection bits (ADMC1 to 0). (Conversion starts with channel 0.
A/D Converter (3) Any one channel/continuous conversion If "any one channel/continuous conversion" is selected as the operating mode (ADMD1 to 0), one AN input is converted continuously. Set the conversion channel in the conversion channel selection bits (ADSC1 to 0). (ADMC1 to 0 are ignored.) An A/D interrupt request is generated each time conversion is completed.
A/D Converter (4) Multiple channels/continuous conversion If "multiple channels/continuous conversion" is selected as the operating mode (ADMD1 to 0), a number of AN inputs, starting from AN0, are converted continuously. Set channel 0 in the conversion channel selection bits used for converting any one channel (ADSC1 to 0), and set the number of channels to be converted in the conversion channel selection bits (ADMC1 to 0). (Conversion starts with channel 0.
A/D Converter ■ Conversion reference clock selection, sampling cycle number selection The A/D conversion time is [(12 + number of sampling cycles) x IOCLK/clock selection]/channel. For example, if the conversion reference clock is set as 1/8 of IOCLK and the number of sampling cycles is set as two cycles, the A/D conversion time is IOCLK x 112 cycles/channel.
A/D Converter [Notes] If a falling edge is input to the ADTRG pin before the conversion start trigger selection (ADST1 to 0) is switched to "external trigger" ("01"), the ADEN flag is set at the same time that the switch is made, and A/D conversion starts. Fig. 14-5-7 shows an example of a single conversion. In this case, the ADEN conversion start/execution flag is set at the same time that ADST1 to 0 are switched, and is reset when A/D conversion is completed.
15.
I/O Ports 15.1 Overview The MN103001G and MN1030F01K have a total of 13 internal I/O ports: 0 to 9, A, B and C. These ports can all be accessed by programs as internal I/O memory space.
I/O Ports Port 7 (P7) This port is also used for address bus signal A23; DRAM RAS signals RAS2 and RAS1; and chip select signals CS3 to CS0. Port 8 (P8) This port is also used for analog signal inputs AN3 to AN0 and external interrupt inputs IRQ7 to I RQ4. Port 9 (P9) This port is also used for extension mode setting signals EXMOD1 and EXMOD0; memory write signals WE1 and WE0; memory read signal RE; bus authority request signal BR; data acknowledge signal DK; and system clock SYSCLK.
I/O Ports The I/O ports are provided with the registers listed in Table 15-1-1.
I/O Ports Table 15-1-1 List of Registers (2/2) Address x'36008081 x'36008084 x'36008085 x'36008088 x'36008089 x'3600808C x'36008090 x'36008091 x'36008094 x'36008095 Name Port 1 pin register Port 2 pin register Port 3 pin register Port 4 pin register Port 5 pin register Port 6 pin register Port 8 pin register Port 9 pin register Port A pin register Port B pin register Symbol P1IN P2IN P3IN P4IN P5IN P6IN P8IN P9IN PAIN PBIN Number of bits Initial value Access size 8 x'XX 8 8 x'XX 8, 16 8 x'0X 8 8 x'XX 8,
I/O Ports 15.2 Port 0 15.2.1 Block Diagram Fig. 15-2-1 and Fig 15-2-2 show block diagrams for port 0. Internal data bus P0OUT P02O M P X P02 CAS M P X A22 Control signal from BC Output control A23 to A16 Output enable signals P0SS P02S P0MD P02MD P... Fig. 15-2-1 Port 0 Block Diagram (P02) 15-6 Represents one bit of each register.
I/O Ports Internal data bus P0OUT P0nO M P X P0n (n=1,0) A21(n=1), A20(n=0) A23 to A16 Output enable signals P0MD P0nMD P... Represents one bit of each register. Fig. 15-2-2 Port 0 Block Diagram (P01, P00) 15.2.2 Register Descriptions Port 0 is a general-purpose output port that is also used for address bus A [22:20], DRAM CAS signal CAS. Each register for port 0 is described below.
I/O Ports Port 0 output mode register Register symbol: P0MD Address: x'36008020 Purpose: This register selects the content output on the port 0 pins with P0SS. Bit No. 7 6 5 4 3 Bit name Reset Access 0 R 0 R 0 R 0 R 0 R 2 1 0 P02MD P01MD P00MD 0 0 0 R/W R/W R/W Port 0 dedicated output control register Register symbol: P0SS Address: x'36008040 Purpose: This register selects the content output on the port 0 pins. Valid when the P0nMD bit is "0". Bit No.
I/O Ports 15.2.3 Pin Configurations Table 15-2-1 shows the pin configurations for port 0. Table 15-2-1 Port 0 Configuration Port Pin No.
I/O Ports 15.3 Port 1 15.3.1 Block Diagram Figs. 15-3-1 and 15-3-2 show block diagrams for port 1. Internal data bus P1OUT P1nO M P X P1n (n=7,6,5,4,3,2) P1DIR P1nD D7 to D0 Output enable signal M P X P1MD P1M P1PU D7(n=7) to D2(n=2) P1IN P1nI P... Represents one bit of each register. Fig.
I/O Ports Internal data bus RWSEL(n=1), AS(n=0) P1OUT P1nO Control Signal from BC M P X P1DIR P1nD D7 to D0 Output enable signal M P X M P X P1n (n=1,0) M P X P1MD P1M P1PU Address/data multiplex mode D1(n=1), D0(n=0) P1IN P1nI P... Represents one bit of each register. Fig.
I/O Ports 15.3.2 Register Descriptions Port 1 is a general-purpose input/output port that is also used for data bus signals D[7:0], address strobe signal AS, and read/write select RWSEL. Each register for port 1 is described below. Port 1 output register Register symbol: P1OUT Address: x'36008001 Purpose: This register sets the data to be output on port 1. Bit No.
I/O Ports Port 1 input/output control register Register symbol: P1DIR Address: x'36008061 Purpose: This register sets the port 1 pins for input or output. (0:input; 1: output) Bit No.
I/O Ports 15.3.3 Pin Configurations Table 15-3-1 shows the pin configurations for port 1. Table 15-3-1 Port 1 Configuration Port Pin No.
I/O Ports 15.4 Port 2 15.4.1 Block Diagram Figs. 15-4-1 shows a block diagrams for port 2. Internal data bus P2OUT P2nO M P X P2n (n=7,6,5,4,3,2,1,0) P2DIR P2nD D15 to D8 output enable signal M P X P2MD P2M P2PU D15(n=7) to D8(n=0) P2IN P2nI P... Represents one bit of each register. Fig.
I/O Ports 15.4.2 Register Descriptions Port 2 is a general-purpose input/output port that is also used for data bus signals D[15:8]. Each register for port 2 is described below. Port 2 output register Register symbol: P2OUT Address: x'36008004 Purpose: This register sets the data to be output on port 2. Bit No.
I/O Ports Port 2 input/output control register Register symbol: P2DIR Address: x'36008064 Purpose: This register sets the port 2 pins for input or output. (0: input; 1: output) Bit No.
I/O Ports 15.4.3 Pin Configurations Table 15-4-1 shows the pin configurations for port 2. Table 15-4-1 Port 2 Configuration Port Pin No.
I/O Ports 15.5 Port 3 15.5.1 Block Diagram Fig. 15-5-1 shows a block diagram for port 3. Internal data bus P3OUT P30O M P X P30 BG P3DIR P30D M P X P3MD P3M P3IN P30I P... Represents one bit of each register. Fig.
I/O Ports 15.5.2 Register Descriptions Port 3 is a general-purpose input/output port that is also used for the bus grant signal BG. Each register for port 3 is described below. Port 3 output register Register symbol: P3OUT Address: x'36008005 Purpose: This register sets the data to be output on port 3. Bit No.
I/O Ports Port 3 output mode register Register symbol: P3MD Address: x'36008025 Purpose: This register selects the content output on the port 3 pin. Bit No. 7 6 5 4 3 2 1 0 Bit name Reset Access 0 R 0 R 0 R 0 R 0 R 0 R 0 R P3M 1 R/W P3M 0: Bus grant signal output (BG) 1: General-purpose input/output port (P30) Note: When BG is selected in the P3MD register, this control signal is output regardless of the value in the P3DIR register.
I/O Ports 15.6 Port 4 15.6.1 Block Diagram Figs. 15-6-1 to 15-6-4 show block diagrams for port 4. Internal data bus P4OUT P4nO M P X DWE(n=5), DCAS0(n=3) P4n (n=5,3) M P X SBO1(n=5), SBT1(n=3) P4DIR P4nD M P X Control signal from BC M P X SBO1 output enable (n=5), SBT1 output enable (n=3) P4SS P4nS P4MD P4nM SBO1(n=5), SBT1(n=3) P4IN P4nI P... Represents one bit of each register. Fig.
I/O Ports Internal data bus P4OUT P44O M P X P44 DCAS1 P4DIR P44D M P X Control signal from BC M P X P4SS P44S P4MD P44M SBI1 P4IN P44I P... Represents one bit of each register. Fig.
I/O Ports Internal data bus P4OUT P4nO M P X P4n (n=2,0) SBO0(n=2), SBT0(n=0) P4DIR P4nD M P X SBO0 output enable(n=2), SBT0 output enable (n=0) P4MD P4nM SBO0(n=2), SBT0(n=0) P4IN P4nI P... Represents one bit of each register. Fig. 15-6-3 Port 4 Block Diagram (P42, P40) Internal data bus P4OUT P41 P41O P4DIR P41D P4MD P41M SBI0 P4IN P41I P... Fig. 15-6-4 Port 4 Block Diagram (P41) 15-24 Represents one bit of each register.
I/O Ports 15.6.2 Register Descriptions Port 4 is a general-purpose input/output port that is also used for serial interface input/output signals SBI1, SBO1, SBT1, SBI0, SBO0, and SBT0; the DRAM CAS signals (for 2CAS) DCAS1 and DCAS0; and the DRAM write signal (for 2CAS) DWE. Each register for port 4 is described below. Port 4 output register Register symbol: P4OUT Address: x'36008008 Purpose: This register sets the data to be output on port 4. Bit No.
I/O Ports Port 4 input/output control register Register symbol: P4DIR Address: x'36008068 Purpose: This register sets the port 4 pins for input or output. (0: input; 1: output) Bit No. 7 6 Bit name Reset Access 0 R 0 R 5 4 3 2 1 0 P45D P44D P43D P42D P41D P40D 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Port 4 output mode register Register symbol: P4MD Address: x'36008028 Purpose: Along with P4SS, this register selects the content output on the port 4 pins. Bit No.
I/O Ports Port 4 dedicated output control register Register symbol: P4SS Address: x'36008048 Purpose: Along with P4MD, this register selects the content output on the port 4 pins. Bit No. 7 6 Bit name Reset Access 0 R 0 R 5 4 3 P45S P44S P43S 0 0 0 R/W R/W R/W 2 1 0 0 R 0 R 0 R P45M; P45S 00: Serial 1 data input/output (SBO1) * The input/output setting is made through the serial interface 1 settings.
I/O Ports 15.6.3 Pin Configurations Table 15-6-1 shows the pin configurations for port 4. Table 15-6-1 Port 4 Configuration Port Pin P4n No.
I/O Ports 15.7 Port 5 15.7.1 Block Diagram Figs. 15-7-1 to 15-7-5 show block diagrams for port 5. Internal data bus P5OUT P55O M P X TM13IO M P X TM5IO P55 M P X SBO3 P5DIR P55D P5SS P55S P5MD P55M TM13IO/TM5IO P5IN P55I P... Represents one bit of each register. Fig.
I/O Ports Internal data bus P5OUT P54O M P X M P X TM12IO P54 TM4IO P5DIR P54D M P X P5SS P54S P5MD P54M TM12IO/TM4IO/SBI3 P5IN P54I P... Fig. 15-7-2 Port 5 Block Diagram (P54) 15-30 Represents one bit of each register.
I/O Ports Internal data bus P5OUT P53O M P X M P X TM11IO P53 TM3IO P5DIR P53D M P X P5SS P53S P5MD P53M TM11IO/TM3IO/SBT3 P5IN P53I P... Represents one bit of each register. Fig.
I/O Ports Internal data bus P5OUT P5nO M P X TM2IO(n=2), TM0IO(n=0) P5n (n=2,0) M P X SBO2(n=2), SBT2(n=0) P5DIR P5nD M P X SBO2 output enable (n=2), SBT2 output enable (n=0) P5SS P5nS P5MD P5nM TM2IO/SBO2(n=2), TM0IO/SBT2(n=0) P5IN P5nI P... Fig. 15-7-4 Port 5 Block Diagram (P52, P50) 15-32 Represents one bit of each register.
I/O Ports Internal data bus P5OUT P51O M P X P51 TM1IO P5DIR P51D M P X P5SS P51S P5MD P51M TM1IO/SBI2 P5IN P51I P... Represents one bit of each register. Fig.
I/O Ports 15.7.2 Register Descriptions Port 5 is a general-purpose input/output port that is also used for the serial interface input/output signals SBI3, SBO3, SBT3, SBI2, SBO2, SBT2; and the timer input/output signals TM13IO, TM12IO, TM11IO, TM5IO, TM4IO, TM3IO, TM2IO, TM1IO, and TM0IO. Each register for port 5 is described below. Port 5 output register Register symbol: P5OUT Address: x'36008009 Purpose: This register sets the data to be output on port 5. Bit No.
I/O Ports Port 5 input/output control register Register symbol: P5DIR Address: x'36008069 Purpose: This register sets the port 5 pins for input or output. (0: input; 1: output) Bit No. 7 6 Bit name Reset 0 0 P55D P54D P53D P52D P51D P50D 0 0 0 0 0 0 5 4 3 2 1 0 Access R R R/W R/W R/W R/W R/W R/W Port 5 output mode register Register symbol: P5MD Address: x'36008029 Purpose: Along with P5SS, this register selects the content output on the port 5 pins. Bit No.
I/O Ports Port 5 dedicated output control register Register symbol: P5SS Address: x'36008049 Purpose: Along with P5MD, this register selects the content output on the port 5 pins. Bit No.
I/O Ports 15.7.3 Pin Configurations Table 15-7-1 shows the pin configurations for port 5. Table 15-7-1 Port 5 Configuration Port Pin No.
I/O Ports 15.8 Port 6 15.8.1 Block Diagram Figs. 15-8-1 shows the block diagrams for port 6. Internal data bus P6OUT P6nO TM10IOB(n=3), TM10IOA(n=2), TM7IO(n=1), TM6IO(n=0) M P X P6n (n=3,2,1,0) P6DIR P6nD P6MD P6nM ADTRG/IRQ3/TM10IOB(n=3), IRQ2/TM10IOA(n=2), IRQ1/TM7IO(n=1), IRQ0/TM6IO(n=0) P6IN P6nI P... Represents one bit of each register. Fig.
I/O Ports 15.8.2 Register Descriptions Port 6 is a general-purpose input/output port that is also used for external interrupt inputs IRQ3 to IRQ0; the timer input/output signals TM6IO, TM7IO, TM10IOA, TM10IOB; and the A/D conversion trigger input ADTRG. Each register for port 6 is described below. Port 6 output register Register symbol: P6OUT Address: x'3600800C Purpose: This register sets the data to be output on port 6. Bit No.
I/O Ports Port 6 output mode register Register symbol: P6MD Address: x'3600802C Purpose: This register selects the content output on the port 6 pins. Bit No. 7 6 5 4 Bit name Reset Access 0 R 0 R 0 R 0 R 3 2 1 0 P63M P62M P61M P60M 1 1 1 1 R/W R/W R/W R/W When P6nM is "0", the timer input/output signal is selected. The input/output setting for the timer input/output signal is also changed by P6nD. 15.8.3 Pin Configurations Table 15-8-1 shows the pin configurations for port 6.
I/O Ports 15.9 Port 7 15.9.1 Block Diagram Fig. 15-9-1 and Fig. 15-9-2 show block diagrams for port 7. Internal data bus P7OUT P73O A23 M P X P73 M P X CS3 P7SS P73S Control signal from BC P7MD P73M P... Represents one bit of each register. Fig. 15-9-1 Port 7 Block Diagram (P73) Internal data bus P7OUT P7nO CS2/RAS2(n=2), CS1/RAS1(n=1), CS0(n=0) M P X P7n (n=2,1,0) P7MD P7nM Control signal from BC P... Represents one bit of each register. Fig.
I/O Ports 15.9.2 Register Descriptions Port 7 is a general-purpose output port that is also used for address bus signal A23, DRAM RAS signals RAS2 and RAS1, chip select signals CS3 to CS0. Each register for port 7 is described below. Port 7 output register Register symbol: P7OUT Address: x'3600800D Purpose: This register sets the data to be output on port 7. Bit No.
I/O Ports Port 7 dedicated output control register Register symbol: P7SS Address: x'3600804D Purpose: This register selects the content output on the port 7 pins. Valid when the P7nM is “0”. Bit No.
I/O Ports 15.9.3 Pin Configurations Table 15-9-1 shows the pin configurations for port 7. Table 15-9-1 Port 7 Configuration Port Pin P7n No.
I/O Ports 15.10 Port 8 15.10.1 Block Diagram Figs. 15-10-1 shows the block diagrams for port 8. Internal data bus AN3(n=3) to AN0(n=0) P8n (n=3,2,1,0) P8AD P8nA IRQ7(n=3) to IRQ4(n=0) P8IN P8nI P... Represents one bit of each register. Fig.
I/O Ports 15.10.2 Register Descriptions Port 8 is a general-purpose input port that is also used for analog signal inputs AN3 to AN0 and external interrupt inputs IRQ7 to IRQ4. Each register for port 8 is described below. Port 8 analog/digital input control register Register symbol: P8AD Address: x'36008030 Purpose: This register selects the analog/digital input on the port 8 pins. (0: digital; 1: analog) Bit No.
I/O Ports 15.10.3 Pin Configurations Table 15-10-1 shows the pin configurations for port 8. Table 15-10-1 Port 8 Configuration Port Port 8 Pin No.
I/O Ports 15.11 Port 9 15.11.1 Block Diagram Fig. 15-11-1 to Fig. 15-11-4 show block diagrams for port 9. Internal data bus P9OUT P97O M P X P97 SYSCLK P9MD P97M P... Represents one bit of each register. Fig. 15-11-1 Port 9 Block Diagram (P97) Internal data bus P9OUT P96 P96O P9DIR P96D P9MD P96M BR P9IN P96I P... Fig. 15-11-2 Port 9 Block Diagram (P96) 15-48 Represents one bit of each register.
I/O Ports Internal data bus P9OUT P9n (n=5,1,0) P9nO P9DIR P9nD P9MD P9nM DK (n=5), EXMOD1 (n=1), EXMOD0 (n=0) P9IN P9nI P... Represents one bit of each register. Fig. 15-11-3 Port 9 Block Diagram (P95, P91, P90) Internal data bus P9OUT P9nO WE1(n=4), WE0(n=3), RE(n=2) M P X P9n (n=4,3,2) P9MD P9nM Control signal from BC P... Represents one bit of each register. Fig.
I/O Ports 15.11.2 Register Descriptions Port 9 is also used for extension mode setting signals EXMOD1 and EXMOD0; memory write signals WE1 and WE0; memory read signal RE; bus authority request signal BR; data acknowledge signal DK; and system clock SYSCLK. P96, P95, P91, and P90 are general-purpose input/output ports, and P97 and P94 to P92 are generalpurpose output ports. Each register for port 9 is described below.
I/O Ports Port 9 output mode register Register symbol: P9MD Address: x'36008031 Purpose: This register selects the content output on the port 9 pins. Bit No.
I/O Ports 15.11.3 Pin Configurations Table 15-11-1 shows the pin configurations for port 9. Table 15-11-1 Port 9 Configuration Port Pin No.
I/O Ports 15.12 Port A 15.12.1 Block Diagram Fig. 15-12-1 shows a block diagram for port A. Internal data bus PAOUT PAnO M P X PAn (n=7,6,5,4,3,2,1,0) PADIR PAnD A7 to A0 Output enable signal M P X PAMD PAM PAPU A7(n=7) to A0(n=0) or ADM7(n=7) to ADM0(n=0) PAIN PAnI P... Represents one bit of each register. Fig.
I/O Ports 15.12.2 Register Descriptions Port A is a general-purpose input/output port that is also used for address bus signals A[7:0], and address/ data signals ADM[7:0]. Each register for port A is described below. Port A output register Register symbol: PAOUT Address: x'36008014 Purpose: This register sets the data to be output on port A. Bit No.
I/O Ports Port A input/output control register Register symbol: PADIR Address: x'36008074 Purpose: This register sets the port A pins for input or output. Valid when the PAM is "1". (0: input; 1: output) Bit No.
I/O Ports 15.12.3 Pin Configurations Table 15-12-1 shows the pin configurations for port A. Table 15-12-1 Port A Configuration Port Pin PAn PAM = "1" PAM = "0" No.
I/O Ports 15.13 Port B 15.13.1 Block Diagram Fig. 15-13-1 shows a block diagram for port B. Internal data bus PBOUT PBnO M P X PBn (n=7,6,5,4,3,2,1,0) PBDIR PBnD A15 to A8 output enable signal M P X PBMD PBM PBPU A15 (n=7) to A8 (n=0) or ADM15 (n=7) to ADM8 (n=0) PBIN PBnI P... Represents one bit of each register. Fig.
I/O Ports 15.13.2 Register Descriptions Port B is a general-purpose input/output port that is also used for address bus signals A[15:8], and address/ data signals ADM[15:8]. Each register for port B is described below. Port B output register Register symbol: PBOUT Address: x'36008015 Purpose: This register sets the data to be output on port B. Bit No.
I/O Ports Port B input/output control register Register symbol: PBDIR Address: x'36008075 Purpose: This register sets the port B pins for input or output. Valid when PBM is "1". (0: input; 1: output) Bit No.
I/O Ports 15.13.3 Pin Configurations Table 15-13-1 shows the pin configurations for port B. Table 15-13-1 Port B Configuration Port Port B Pin PBn PBM = "1" PBM = "0" No.
I/O Ports 15.14 Port C 15.14.1 Block Diagram Fig. 15-14-1 shows a block diagram for port C. Internal data bus PCOUT PCnO M P X PCn (n=3,2,1,0) A19 (n=3) to A16(n=0) A23 to A16 Output enable signal M P X PCMD PCnM P... Represents one bit of each register. Fig.
I/O Ports 15.14.2 Register Descriptions Port C is a general-purpose output port that is also used for address bus signals A[19:16]. Each register for port C is described below. Port C output register Register symbol: PCOUT Address: x'36008018 Purpose: This register sets the data to be output on port C. Bit No.
I/O Ports 15.14.3 Pin Configurations Table 15-14-1 shows the pin configurations for port C. Table 15-14-1 Port C Configuration Port Port C Pin No.
I/O Ports 15.15 Treatment of Unused Pins Unused pins should be treated as shown in Table 15-15-1 below. Table 15-15-1 Treatment of Unused Pins Pin name Treatment PC3/A19, PC2/A18, PC1/A17, PC0/A16 Set as port and leave open.
16.
Internal Flash Memory 16.1 Overview The MN1030F01K has 256 KB of internal flash memory for use as instruction memory in place of instruction ROM. Using flash memory makes it easy to make changes to a stored program, which makes it possible to reduce program development time and permits the creation of a highly flexible system. 16.2 Features The features of the internal flash memory are described below. ■ ■ ■ ■ ■ 16.
Internal Flash Memory 16.4 Flash Memory Overwrite Mode and Settings There are two flash memory overwrite modes: flash memory mode and on-board write mode. Table 16-4-1 lists the mode settings through the external pins. Flash memory mode is used to overwrite the internal flash memory with a ROM writer. In this mode, the flash memory inputs and outputs are connected to external pins. On-board write mode is used to overwrite the internal flash memory via software.
Internal Flash Memory 16.5 Flash Memory Mode 16.5.1 Description of External Pins VDD VSS VDD 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS Fig. 16-5-1 and Table 16-5-1 show the pin assignments for the MN1030F01K in flash memory mode.
Internal Flash Memory Table 16-5-1 MN1030F01K Pin Assignments Pin No. Pin Name I/O Pin No. Pin Name I/O Pin No. Pin Name I/O Pin Pin Name No.
Internal Flash Memory Table 16-5-2 lists the functions of the external pins in flash memory mode. Table 16-5-2 Pin Functions Pin Name Input/Output PA[17:1] Input PD[15:0] Input/Output Description Address Data NCE Input Chip enable MODE Input Mode NOE Input Output enable NWE Input Write enable E Input Erase enable FROM Input Flash memory/microcontroller mode switch TEST[3:0] Input Test signal * Input x'0.
Internal Flash Memory 16.5.2 Erasure Blocks The flash memory is partitioned into 32 8 KB erasure blocks. Fig. 16-5-2 shows the configuration of the flash memory erasure blocks and their correspondence with each of the bits in the erasure block registers that are used to specify which blocks to erase. After setting the erasure block registers in erasure block setting mode, block erase mode is used to erase the blocks that correspond to the bits for which "1" was specified in the erasure block registers.
Internal Flash Memory 16.6 On-board Write Mode In on-board write mode, flash memory is overwritten by manipulating the control registers through software. Table 16-6-1 lists the control registers to be used in on-board write mode.
17.
Ordering Mask ROM 17.1 Overview This chapter describes the procedure for ordering mask ROM. This chapter also describes the difference in programming when using a product that has on-chip flash memory versus a mask product, and explains how to order ROM, etc. 17.
Ordering Mask ROM Program in flash memory x'40000000 x'40000000 JMP x'40002000 Loader program 8 KB Program in mask ROM x'40002000 x'40000008 JMP x'40002008 8 KB x'40002000 User program User program (When the user program starts in x'40002000 and the non-maskable interrupt processing routine starts in x'40002008) Fig.
Ordering Mask ROM 17-4
Appendix
Appendix-2 C B A 9 IVAR6 IVAR2 8 7 6 IVAR1 IVAR5 5 4 2 MEMCTR1B 3 1 IVAR4 IVAR0 0 G10ICR G14ICR G11ICR G15ICR G19ICR x'3400012X x'3400013X x'3400014X AD1BUF AD0BUF Note: Accessing areas that are not mounted is prohibited. Operation is not guaranteed if an area that is not mounted is accessed.
C SC3 STR TM9 BR TM9 BC TM9 CMP WDCTR TM8 BR TM8 BC TM8 CMP TM8 MD TM7 BR TM7 BC TM7 CMP TM7 MD 7 TM13 MD TM6 BR TM6 BC TM6 CMP TM6 MD 6 TM5 BR TM5 BC TM5 CMP TM5 MD 5 TM12 MD TM4 BR TM4 BC TM4 CMP TM4 MD SC3 ICR SC0 ICR SC1 ICR SC2 ICR 4 TM0 BR TM0 BC TM0 MD TM10 MDA FAREG FL MODR FDREG FBEWER FCREG Flash memory control WDBC Watchdog timer 16-bit timer 8-bit timer Serial interface :This register is installed only for versions with a flash memory.
Appendix-4 F E C P7SS P7MD P6IN P6DIR P6MD P7OUT P6OUT D B A P5IN P5DIR P5SS P5MD P4IN P4DIR P4SS PCMD P4MD PBIN P1IN P9IN P2IN PAIN P9DIR PBDIR PADIR P3IN P1DIR P3DIR P2DIR P3MD P8IN P0SS P8AD P0MD P9MD 0 PBMD PAMD 1 P1MD 2 P2MD 3 P9OUT 4 PBOUT PAOUT 5 PCOUT 6 P1OUT P0OUT I/O port 7 P3OUT P2OUT 8 P5OUT P4OUT 9 Note: Accessing areas that are not mounted is prohibited. Operation is not guaranteed if an area that is not mounted is accessed.
Appendix Appendix B.
Appendix Instruction MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVBU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU MOVHU EXT EXT EXTB EXTB EXTBU EXTBU EXTH EXTH EXTHU EXTHU MOVM MOVM MOVM Appendix-6 Source (Am) (d8,Am) (d16,Am) (d32,Am) (d8,SP) (d16,SP) (d32,SP) (Di,Am) (abs16) (abs32) Dm Dm Dm Dm Dm Dm Dm Dm Dm Dm (Am) (d8,Am) (d16,Am) (d32,Am) (d8,SP
Appendix Instruction Source Destination Format Code length Execution Cycle MOVM CLR ADD ADDC SUB SUBC MUL MULU DIV DIVU INC INC4 CMP CLR ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADDC SUB SUB SUB SUB SUB SUB SUBC MUL MULU DIV DIVU INC INC INC4 CMP CMP CMP CMP CMP CMP CMP CMP CMP CMP Dm Dm Am Am imm8 imm16 imm32 imm8 imm16 imm32 imm8 imm16 imm32 Dm Dm Dm Am Am imm32 imm32 Dm Dm Dm Dm Dm Dm Dm Am Am imm8 imm16 imm32 imm8 imm16 imm32 Dn Dn An Dn An Dn Dn Dn An An An SP SP SP Dn
Appendix Instruction AND OR XOR NOT BTST BSET BCLR ASR LSR ASL ASL2 ROR ROL Bcc Lcc AND AND AND AND AND OR OR OR OR OR XOR XOR XOR NOT BTST BTST BTST BTST BTST BSET BSET BSET BCLR BCLR BCLR ASR ASR LSR LSR ASL ASL ASL2 ROR ROL BEQ BNE BGT BGE BLE BLT BHI BCC BLS BCS BVC BVS BNC BNS BRA LEQ LNE LGT LGE LLE LLT LHI LCC LLS LCS LRA Source Dm imm8 imm16 imm32 imm16 Dm imm8 imm16 imm32 imm16 Dm imm16 imm32 imm8 imm16 imm32 imm8 imm8 Dm imm8 imm8 Dm imm8 imm8 Dm imm8 Dm imm8 Dm imm8 (d8,PC) (d8,PC) (
Appendix Instruction SETLB JMP Source CALL SETLB JMP JMP JMP CALL (An) (d16,PC) (d32,PC) (d16,PC) CALL CALL (d32,PC) CALLS RET CALLS CALLS CALLS RET RETF RETF RETS RTI TRAP NOP UDF RETS RTI TRAP NOP UDF20~35 UDF00~15 UDF00~15 UDF00~15 UDF00~15 UDFU00~15 UDFU00~15 UDFU00~15 Destination Format Code length Execution Cycle regs,imm8 S0 D0 S2 S4 S4 1 2 3 5 5 regs,imm8 S6 7 (An) (d16,PC) (d32,PC) regs,imm8 D0 D2 D4 S2 2 4 6 3 regs,imm8 S2 3 Dm Dm imm8 imm16 imm32 imm8 imm16 imm32 D
Appendix List of Extension Instructions ( Code Length, Execution Cycle) Instruction PUTX PUTCX GETX GETX GETCHX GETCLX CLRMAC CLRMAC MULQ MULQ PUTX MULQU MAC MACU SAT16 SAT24 MCST BSCH SWAP Source Dm Dm Dm MULQI MULQI MULQI imm8 imm16 imm32 MULQU Dm MULQIU MULQIU MULQIU imm8 imm16 imm32 MAC MACH MACB MACU MACHU MACBU SAT16 SAT24 MCST MCST MCST9 MCST48 BSCH SWAP SWAPH Dm Dm Dm Dm Dm Dm Dm Dm Dm imm8 Appendix-10 Dm Dm Dm Destination Format Code length Execution cycle Remarks D0 2 2 Dn D0 2
Appendix Appendix C. Memory Connection Example Fig. C-1 shows a connection example for the memory configuration described below.
Appendix Appendix D. Pins and Their Operating Statuses upon Reset In the address/data separate mode Pin No. Pin name Operating status Pin No. Pin name Operating status Pin No. Pin name Operating status Pin No.
Appendix In the address/data multiplex mode Pin No. Pin name Operating status Pin No. Pin name Operating status Pin No. Pin name Operating status Pin No.
Appendix Appendix E. Package Outline The package outline and dimensions of this microcontroller are shown below. 14.00 ± 0.10 Fig. E-1 Package Outline Appendix-14 ± 0.20 ± 0.20 16.00 16.00 ± 0.10 Unit: mm 14.
The correction table in The Revised Edition of MN103001G/F01K LSI User's Manual (From 2nd Edition (or 2nd Edition 1st printing) to 5th Edition) Errors Page Corrections Page _____________ P.1-3 - External interrupts: 9 sources (8 individual IRQs, and 1 external NMI) P.1-3 - External interrupts: 9 sources (IRQn (n=7 to 0) x 8, and NMIRQ x 1 ) _________ _________ P.1-8 (The column of "Pin Function" such as "Pin name" is "NMIRQ" in the table.) P.
Page Errors P.3-8 P.3-9 P.3-10 P.3-21 P.3-22 P.3-23 [Instruction Format (Macro Name)] MCST32, MCST16, MCST8 P.3-23 (From 2nd line of [Operation]) In addition, depending on the value of Dm, ... P.3-8 (Following sentences are added to [Programming Cautions] of GETCHX.) When "udf12 Dm, Dn" is operated, Dm is ignored. The operations of "udf12 imm8, Dn", "udf12 imm16, Dn" and "udf12 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases. P.
Errors Page Corrections Page P.3-30 P.3-30 (Following sentence is added to [Programming Cautions] of SWAPH.) The operations of "udf09 imm8, Dn", "udf09 imm16, Dn" and "udf09 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases. P.3-31 (One note is added in the table 3-2-1.) P.3-31 (Omit) Preceding instruction Following instruction Placement relationship : : : (◆ For details, refer to note (e) on page 3-36.) P.5-4 STOP ...
Errors Page Corrections Page P.6-3 P.6-3 Input frequency range PLL Input frequency range PLL 8 fosci 15 MHz When using 8 MHz fosci 18 MHz When using 8 fosci 30 MHz When not using 8 MHz fosci 20 MHz When not using P.6-3 When the reset state is released, SYSCLK, MCLK, and IOCLK are P.6-3 When the reset state is released, SYSCLK, MCLK, and IOCLK are supplied starting after a certain oscillation stabilization wait time. supplied starting after a certain oscillation stabilization wait time.
Page Errors Page Corrections ____ P.8-42 P.8-43 to P.8-44 P.8-48 P.8-49 P.8-49 P.8-50 P.8-56 P.8-57 P.8-42 (In figure 8-13-13 (a) and (b), the DK signal asserted by the loworder side access was changed so as to be negated before the highorder side access.) ____ P.8-43 (In figure 8-13-14 (a), (b) and figure 8-13-15 (a), (b), the DK signal to asserted by the low- order side access was changed so as to be P.8-44 negated before the high-order side access.
Errors Page Corrections Page P.9-3 (In fig. 9-4-1.) P.9-3 (In fig. 9-4-1.) 0 Non-maskable interrupts NMI GROUP 0 1 0 GROUP 0 1 P.9-7 (Register's purpose) P.9-7 (Register's purpose) This register determines whether an NMI interrupt has been generated. This register determines whether a non-maskable interrupt has been generated. P.9-7 Bit name Description P.9-7 Bit name Description NMIF External NMI request flag NMIF External non-maskable interrupt request flag P.
Errors Page Corrections Page P.12-5 (In the table of Example.) P.12-5 (In the table of Example.) Overflow cycle When CKSEL is "H" and oscillation frequency is 15 MHz (or when CKSEL is "L" and oscillating frequency is 30 MHz) Overflow cycle When CKSEL is "H" and oscillation frequency is 15 MHz P.12-7 (The 2nd line from the bottom.) P.12-7 (The 2nd line from the bottom.) An oscillation stabilization wait time of at least 17ms is An oscillation stabilization wait time of at least 14 ms is recommended.
Page - Errors Page Corrections - (All of the series name in this manual is changed as shown below: • "MN10300 Series" is changed the name into "MN1030 Series". • "MN10200 Series" is changed the name into "MN102 Series". ) Warning (Deleted.) Warning The MN1030F01K is manufactured and marketed under a licensing agreement with Bull CP8 Corporation. Note that the MN1030F01K cannot be used on IC cards.
MN103001G/F01K LSI User's Manual February, 2002 5th Edition Issued by Matsushita Electric Industrial Co., Ltd. © Matsushita Electric Industrial Co., Ltd.
Semiconductor Company, Matsushita Electric Industrial Co., Ltd. Nagaokakyo, Kyoto 617-8520, Japan Tel: (075) 951-8151 http://www.panasonic.co.jp/semicon/ SALES OFFICES ■ NORTH AMERICA ●U.S.A. Sales Office: Panasonic Industrial Company [PIC] • New Jersey Office: Two Panasonic Way Secaucus, New Jersey 07094 U.S.A. Tel: 1-201-348-5257 Fax:1-201-392-4652 • Chicago Office: 1707 N. Randall Road Elgin, Illinois 60123-7847 U.S.A.
