Propeller Manual
Table Of Contents
- Preface
- Chapter 1 : Introducing the Propeller Chip
- Concept
- Package Types
- Pin Descriptions
- Specifications
- Hardware Connections
- Boot Up Procedure
- Run-Time Procedure
- Shutdown Procedure
- Block Diagram
- Shared Resources
- System Clock
- Cogs (processors)
- Hub
- I/O Pins
- System Counter
- CLK Register
- Locks
- Main Memory
- Main RAM
- Main ROM
- Character Definitions
- Log and Anti-Log Tables
- Sine Table
- Boot Loader and Spin Interpreter
- Chapter 2 : Spin Language Reference
- Structure of Propeller Objects/Spin
- Categorical Listing of Propeller Spin Language
- Spin Language Elements
- ABORT
- BYTE
- BYTEFILL
- BYTEMOVE
- CASE
- CHIPVER
- CLKFREQ
- _CLKFREQ
- CLKMODE
- _CLKMODE
- CLKSET
- CNT
- COGID
- COGINIT
- COGNEW
- COGSTOP
- CON
- CONSTANT
- Constants (pre-defined)
- CTRA, CTRB
- DAT
- DIRA, DIRB
- FILE
- FLOAT
- _FREE
- FRQA, FRQB
- IF
- IFNOT
- INA, INB
- LOCKCLR
- LOCKNEW
- LOCKRET
- LOCKSET
- LONG
- LONGFILL
- LONGMOVE
- LOOKDOWN, LOOKDOWNZ
- LOOKUP, LOOKUPZ
- NEXT
- OBJ
- Operators
- Expression Workspace
- Operator Attributes
- Unary / Binary
- Normal / Assignment
- Constant and/or Variable Expression
- Level of Precedence
- Intermediate Assignments
- Constant Assignment ‘=’
- Variable Assignment ‘:=’
- Add ‘+’, ‘+=’
- Positive ‘+’ (unary form of Add)
- Subtract ‘-’, ‘-=’
- Negate ‘-’ (unary form of Subtract)
- Decrement, pre- or post- ‘- -’
- Increment, pre- or post- ‘+ +’
- Multiply, Return Low ‘*’, ‘*=’
- Multiply, Return High ‘**’, ‘**=’
- Divide ‘/’, ‘/=’
- Modulus ‘//’, ‘//=’
- Limit Minimum ‘#>’, ‘#>=’
- Limit Maximum ‘<#’, ‘<#=’
- Square Root ‘^^’
- Absolute Value ‘||’
- Sign-Extend 7 or Post-Clear ‘~’
- Sign-Extend 15 or Post-Set ‘~~’
- Shift Arithmetic Right ‘~>’, ‘~>=’
- Random ‘?’
- Bitwise Decode ‘|<’
- Bitwise Encode ‘>|’
- Bitwise Shift Left ‘<<’, ‘<<=’
- Bitwise Shift Right ‘>>’, ‘>>=’
- Bitwise Rotate Left ‘<-’, ‘<-=’
- Bitwise Rotate Right ‘->’, ‘->=’
- Bitwise Reverse ‘><’, ‘><=’
- Bitwise AND ‘&’, ‘&=’
- Bitwise OR ‘|’, ‘|=’
- Bitwise XOR ‘^’, ‘^=’
- Bitwise NOT ‘!’
- Boolean AND ‘AND’, ‘AND=’
- Boolean OR ‘OR’, ‘OR=’
- Boolean NOT ‘NOT’
- Boolean Is Equal ‘==’, ‘===’
- Boolean Is Not Equal ‘<>’, ‘<>=’
- Boolean Is Less Than ‘<’, ‘<=’
- Boolean Is Greater Than ‘>’, ‘>=’
- Boolean Is Equal or Less ‘=<’, ‘=<=’
- Boolean Is Equal or Greater ‘=>’, ‘=>=’
- Symbol Address ‘@’
- Object Address Plus Symbol ‘@@’
- OUTA, OUTB
- PAR
- PHSA, PHSB
- PRI
- PUB
- QUIT
- REBOOT
- REPEAT
- RESULT
- RETURN
- ROUND
- SPR
- _STACK
- STRCOMP
- STRING
- STRSIZE
- Symbols
- TRUNC
- VAR
- VCFG
- VSCL
- WAITCNT
- WAITPEQ
- WAITPNE
- WAITVID
- WORD
- WORDFILL
- WORDMOVE
- _XINFREQ
- Chapter 3 : Assembly Language Reference
- The Structure of Propeller Assembly
- Categorical Listing of Propeller Assembly Language
- Assembly Language Elements
- ABS
- ABSNEG
- ADD
- ADDABS
- ADDS
- ADDSX
- ADDX
- AND
- ANDN
- CALL
- CLKSET
- CMP
- CMPS
- CMPSUB
- CMPSX
- CMPX
- CNT
- COGID
- COGINIT
- COGSTOP
- Conditions ( IF_x )
- CTRA, CTRB
- DIRA, DIRB
- DJNZ
- Effects ( WC, WZ, WR, NR )
- FIT
- FRQA, FRQB
- HUBOP
- IF_x (Conditions)
- INA, INB
- JMP
- JMPRET
- LOCKCLR
- LOCKNEW
- LOCKRET
- LOCKSET
- MAX
- MAXS
- MIN
- MINS
- MOV
- MOVD
- MOVI
- MOVS
- MUXC
- MUXNC
- MUXNZ
- MUXZ
- NEG
- NEGC
- NEGNC
- NEGNZ
- NEGZ
- NOP
- NR
- Operators
- OR
- ORG
- OUTA, OUTB
- PAR
- PHSA, PHSB
- RCL
- RCR
- RDBYTE
- RDLONG
- RDWORD
- Registers
- RES
- RET
- REV
- ROL
- ROR
- SAR
- SHL
- SHR
- SUB
- SUBABS
- SUBS
- SUBSX
- SUBX
- SUMC
- SUMNC
- SUMZ
- Symbols
- TEST
- TESTN
- TJNZ
- TJZ
- VCFG
- VSCL
- WAITCNT
- WAITPEQ
- WAITPNE
- WAITVID
- WC
- WR
- WRBYTE
- WRLONG
- WRWORD
- WZ
- XOR
- Appendix A: Reserved Word List
- Appendix B: Math Samples and Function Tables
- Index
1: Introducing the Propeller Chip
Propeller Manual v1.1 · Page 29
Table 1-7: CLK Register PLLENA (Bit 6)
Bit Effect
0
Disables the PLL circuit. The
RCFAST and RCSLOW settings of the _CLKMODE declaration
configure PLLENA this way.
1
Enables the PLL circuit. Each of the PLLxx settings of the _CLKMODE declaration
configures PLLENA this way at compile time. The Clock PLL internally multiplies the
XIN pin frequency by 16. OSCENA must also be ‘1’ to propagate the XIN signal to the
Clock PLL. The Clock PLL's internal frequency must be kept within 64 MHz to 128 MHz
– this translates to an XIN frequency range of 4 MHz to 8 MHz. Allow 100 µs for the
Clock PLL to stabilize before switching to one of its outputs via the CLKSELx bits.
Once the Crystal Oscillator and Clock PLL circuits are enabled and stabilized, you can
switch freely among all clock sources by changing the CLKSELx bits.
Table 1-8: CLK Register OSCENA (Bit 5)
Bit Effect
0
Disables the Crystal Oscillator circuit. The
RCFAST and T RCSLOW settings of the
_CLKMODE declaration configure OSCENA this way.
1
Enables the Crystal Oscillator circuit so that a clock signal can be input to XIN, or so
that XIN and XOUT can function together as a feedback oscillator. The XINPUT and
XTALx settings of the _CLKMODE declaration configure OSCENA this way. The OSCMx
bits select the operating mode of the Crystal Oscillator circuit. Note that no external
resistors or capacitors are required for crystals and resonators. Allow a crystal or
resonator 10 ms to stabilize before switching to a Crystal Oscillator or Clock PLL output
via the CLKSELx bits. When enabling the Crystal Oscillator circuit, the Clock PLL may
be enabled at the same time so that they can share the stabilization period.
Table 1-9: CLK Register OSCMx (Bits 4:3)
OSCMx
1 0
_CLKMODE
Setting
XOUT
Resistance
XIN/XOUT
Capacitance
Frequency Range
0 0
XINPUT
Infinite 6 pF (pad only) DC to 80 MHz Input
0 1
XTAL1
2000 36 pF 4 to 16 MHz Crystal/Resonator
1 0
XTAL2
1000 26 pF 8 to 32 MHz Crystal/Resonator
1 1
XTAL3
500 16 pF 20 to 60 MHz Crystal/Resonator