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INTEGRATED CIRCUITS

Philips

Semiconductors

PHILIPS

2003 Dec 8

P89LPC901/902/903

8-bit microcontrollers with accelerated two-clock 80C51 core

1KB 3V Low-Power byte-eraseable Flash with 128 Byte RAM

USER

MANUAL

Summary of content (114 pages)

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INTEGRATED CIRCUITS USER MANUAL P89LPC901/902/903 8-bit microcontrollers with accelerated two-clock 80C51 core 1KB 3V Low-Power byte-eraseable Flash with 128 Byte RAM 2003 Dec 8 Philips Semiconductors PHILIPS
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User’s Manual - Preliminary - Philips Semiconductors Table of Contents P89LPC901/902/903 Table of Contents 1. General Description................................................................................ 7 Pin Configurations ..................................................................................... 7 Product comparison................................................................................... 8 Pin Descriptions - P89LPC901 ........................................................
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User’s Manual - Preliminary - Philips Semiconductors Table of Contents P89LPC901/902/903 Mode 6 - P89LPC901 .............................................................................. 47 Timer Overflow toggle output - P89LPC901 ............................................ 49 6. Real-Time Clock/System Timer............................................................ 51 Real-time Clock Source ........................................................................... Changing RTCS1-0 .................
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User’s Manual - Preliminary - Philips Semiconductors Table of Contents P89LPC901/902/903 Feed Sequence ....................................................................................... Watchdog Timer in Timer Mode .............................................................. Power down operation ............................................................................. Watchdog Clock Source ..........................................................................
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User’s Manual - Preliminary - Philips Semiconductors List of Figures P89LPC901/902/903 List of Figures P89LPC901/902/903 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Crystal Oscillator - P89LPC901 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip RC Oscillator TRIM Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram of Oscillator Control - P89LPC901 . . . . . . . .
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User’s Manual - Preliminary - Philips Semiconductors List of Figures P89LPC901/902/903 Serial Port Status Register (SSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Port Mode 0 (Double Buffering Must Be Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . Serial Port Mode 1 (Only Single Transmit Buffering Case Is Shown) . . . . . . . . . . . . . . . . Serial Port Mode 2 or 3 (Only Single Transmit Buffering Case Is Shown) . . . . . . . . . . . .
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION 1. GENERAL DESCRIPTION The P89LPC901/902/903 is a single-chip microcontroller designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC901/902/903 is based on a high performance processor architecture that executes instructions six times the rate of standard 80C51 devices.
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION Logic Symbols XTAL1 VDD KBI4 KBI5 KBI6 KBI2 KBI0 RST PORT0 VDD CIN1A CMPREF CIN2A RST RxD TxD VSS P89 LPC902 PORT0 CIN1A CMPREF CMP1 CIN2A CMP2 KBI4 KBI5 KBI2 PORT1 XTAL2 RST T0 PORT1 CLKOUT P89 LPC901 PORT0 CIN1A CMPREF PORT3 KBI4 KBI5 VSS PORT1 VDD VSS P89 LPC903 Product comparison The following table highlights differences between these three devices.
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION Block Diagram - P89LPC901 High Performance Accelerated 2-clock 80C51 CPU 1KB Code Flash Internal Bus Port 3 Configurable I/Os 128 byte Data RAM Timer0 Timer1 Port 1 Configurable I/Os Real-Time Clock/ System Timer Port 0 Configurable I/Os Analog Comparator Keypad Interrupt Watchdog Timer and Oscillator Programmable Oscillator Divider Crystal or Resonator 2003 Dec 8 Configurable Oscillator Power Monitor
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION Block Diagram - P89LPC902 High Performance Accelerated 2-clock 80C51 CPU 1KB Code Flash Internal Bus 128 byte Data RAM Port 1 Input Timer0 Timer1 Port 0 Configurable I/Os Real-Time Clock/ System Timer Keypad Interrupt Analog Comparators Watchdog Timer and Oscillator Programmable Oscillator Divider CPU Clock On-Chip RC Oscillator 2003 Dec 8 Power Monitor (Power-On Reset, Brownout Reset) 10
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION Block Diagram - P89LPC903 High Performance Accelerated 2-clock 80C51 CPU 1KB Code Flash 128 byte Data RAM Internal Bus UART Port 1 Input Timer0 Timer1 Port 0 Configurable I/Os Real-Time Clock/ System Timer Keypad Interrupt Analog Comparators Watchdog Timer and Oscillator Programmable Oscillator Divider CPU Clock On-Chip RC Oscillator 2003 Dec 8 Power Monitor (Power-On Reset, Brownout Reset) 11
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION PIN DESCRIPTIONS - P89LPC901 MNEMONIC PIN NO. TYPE NAME AND FUNCTION P0.0 - P0.6 6, 7 I/O Port 0: Port 0 is an I/O port with a user-configurable output types. During reset Port 0 latches are configured in the input only mode with the internal pullup disabled. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently.
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION MNEMONIC PIN NO. TYPE NAME AND FUNCTION O XTAL2 Output from the oscillator amplifier (when a crystal oscillator option is selected via the FLASH configuration). O CLKOUTCPU clock divided by 2 when enabled via SFR bit (ENCLK TRIM.6).
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION PIN DESCRIPTIONS - P89LPC902 MNEMONIC PIN NO. TYPE NAME AND FUNCTION P0.0 - P0.6 2,3,5,6,7 I/O Port 0: Port 0 is an I/O port with a user-configurable output types. During reset Port 0 latches are configured in the input only mode with the internal pullup disabled. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently.
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION PIN DESCRIPTIONS - P89LPC903 MNEMONIC PIN NO. TYPE NAME AND FUNCTION P0.0 - P0.6 2,6,7 I/O Port 0: Port 0 is an I/O port with a user-configurable output types. During reset Port 0 latches are configured in the input only mode with the internal pullup disabled. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently.
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION SPECIAL FUNCTION REGISTERS Note: Special Function Registers (SFRs) accesses are restricted in the following ways: 1. User must NOT attempt to access any SFR locations not defined. 2. Accesses to any defined SFR locations must be strictly for the functions for the SFRs. 3.
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION Name Description Bit Functions and Addresses SFR Address MSB - PWDRT H PBOH - PT1H - Reset Value LSB Hex Binary PT0H - 00H1 x0000000 IP0H# Interrupt Priority 0 High B7H FF FE FD FC FB FA F9 F8 IP1*# Interrupt Priority 1 F8H - - - - - PC PKBI - 00H1 00x00000 IP1H# Interrupt Priority 1 High F7H - - - - - PCH PKBIH - 00H1 00x00000 KBCON# Keypad Control Register
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION Name Description Bit Functions and Addresses Reset Value SFR Address MSB 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 - - - - LSB Hex Binary 00H 00000000 TCON* Timer 0 and 1 Control 88H TH0 Timer 0 High 8CH 00H 00000000 TH1 Timer 1 High 8DH 00H 00000000 TL0 Timer 0 Low 8AH 00H 00000000 TL1 Timer 1 Low 8BH 00H 00000000 TMOD Timer 0 and 1 Mode 89H - - T1M1 T1M0 - T
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION Special Function Registers Table - P89LPC902 Name Description SFR Address Bit Functions and Addresses MSB E7 ACC* Accumulator E0H AUXR1# Auxiliary Function Register A2H Reset Value LSB E6 E5 E4 E3 E2 E1 Hex Binary 00H 00000000 00H1 000000x0 00H 00000000 E0 - - - - SRST 0 - DPS F7 F6 F5 F4 F3 F2 F1 F0 B* B Register F0H CMP1# Comparator 1 Control Register ACH - - CE1
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION Name Description KBPATN# Keypad Pattern Register SFR Address Bit Functions and Addresses Reset Value LSB MSB 93H P0* Port 0 80H P1* Port 1 90H 87 86 85 84 83 82 81 80 - CMP1/ KB6 CMPREF/ KB5 CIN1A/ KB4 - KB2 - KB0 97 96 95 94 93 92 91 90 - - RST - - - - - B7 B6 B5 B4 B3 B2 B1 B0 Hex Binary FFH 11111111 Note 1 P0M1# Port 0 Output Mode 1 84H - (P0M1.
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION Bit Functions and Addresses SFR Address MSB WDCON# Watchdog Control Register A7H PRE2 WDL# C1H Name Description Watchdog Load WFEED1# Watchdog Feed 1 C2H WFEED2# Watchdog Feed 2 C3H 2003 Dec 8 Reset Value LSB PRE1 PRE0 - - WDRUN WDTOF WDCLK Hex Notes 3,5 FFH 21 Binary 11111111
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION Special Function Registers Table - P89LPC903 Name Description SFR Address Bit Functions and Addresses Reset Value LSB MSB Hex Binary 00H 00000000 00H1 000000x0 F0H 00H 00000000 BRGR0#§ Baud Rate Generator Rate Low BEH 00H 00000000 BRGR1#§ Baud Rate Generator Rate High BFH 00H 00000000 BRGCON# Baud Rate Generator Control BDH - - - - - - SBRGS CMP1# ACH - - CE1 - CN1 - CO1 E7
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION Name Description Bit Functions and Addresses SFR Address MSB Reset Value LSB Hex Binary IP1H# Interrupt Priority 1 High F7H - PSTH - - - PCH PKBIH - 00H1 00x00000 KBCON# Keypad Control Register 94H - - - - - - PATN_S EL KBIF 00H1 xxxxxx00 KBMASK# Keypad Interrupt Mask Register 86H 00H 00000000 KBPATN# Keypad Pattern Register 93H FFH 11111111 87 86 85 84 83 82 81 80
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION Name Description SFR Address Bit Functions and Addresses Reset Value LSB MSB Hex Binary TH0 Timer 0 High 8CH 00H 00000000 TH1 Timer 1 High 8DH 00H 00000000 TL0 Timer 0 Low 8AH 00H 00000000 TL1 Timer 1 Low 8BH 00H 00000000 TMOD Timer 0 and 1 Mode 89H - - T1M1 T1M0 - - T0M1 T0M0 00H 00000000 TRIM# Internal Oscillator Trim Register 96H - - TRIM.5 TRIM.4 TRIM.3 TRIM.
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION Memory Organization The P89LPC901/902/903 memory map is shown in Figure 1-1. 03FFh 0300h 02FFh 0200h 01FFh 0100h 00FFh Sector 3 Special Function Registers (directly addressable) Sector 2 DATA 128 Bytes On-Chip Data Memory (stack, direct and indir. addr.) 4 Reg.
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User’s Manual - Preliminary - Philips Semiconductors P89LPC901/902/903 GENERAL DESCRIPTION 2003 Dec 8 26
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User’s Manual - Preliminary - Philips Semiconductors CLOCKS P89LPC901/902/903 2. CLOCKS Enhanced CPU The P89LPC901/902/903 uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. Clock Definitions The P89LPC901/902/903 device has several internal clocks as defined below: • OSCCLK - Input to the DIVM clock divider.
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User’s Manual - Preliminary - Philips Semiconductors CLOCKS P89LPC901/902/903 Quartz crystal or ceramic resonator P89LPC901 The oscillator must be configured in one of the following modes: - Low Frequency Crystal - Medium Frequency Crystal - High Frequency Crystal XTAL1 * * A series resistor may be required to limit crystal drive levels. This is especially important for low frequency crystals.
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User’s Manual - Preliminary - Philips Semiconductors CLOCKS P89LPC901/902/903 If CCLK is 8MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ’1’ to reduce power consumption. On reset, CLKLP is ’0’ allowing highest performance access. This bit can then be set in software if CCLK is running at 8MHz or slower. TRIM Address: 96h 7 6 5 4 3 2 1 0 - ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.
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User’s Manual - Preliminary - Philips Semiconductors CLOCKS P89LPC901/902/903 . RTCS1:0 XTAL1 XTAL2 High freq. Med freq. RTC Low freq. FOSC2:0 OSC CLK RC Oscillator DIVM Oscillator Clock CPU Clock CCLK /2 PCLK (7.
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User’s Manual - Preliminary - Philips Semiconductors CLOCKS P89LPC901/902/903 RTCS1:0 RTC FOSC2:0 OSC CLK RC Oscillator DIVM Oscillator Clock CPU Clock CCLK /2 PCLK (7.
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User’s Manual - Preliminary - Philips Semiconductors CLOCKS P89LPC901/902/903 R T C S 1 :0 RTC CPU C lo ck F O S C 2 :0 OSC CLK D IV M CCLK CPU R C O scillato r /2 (7.3728M H z) W DT W atchd o g O scillator (400K H z) PCLK B au d rate G en erato r T im er 0 & 1 U AR T Figure 2-5: Block Diagram of Oscillator Control- P89LPC903 CPU Clock (CCLK) Wakeup Delay The P89LPC901/902/903 has an internal wakeup timer that delays the clock until it stabilizes depending to the clock source used.
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User’s Manual - Preliminary - Philips Semiconductors CLOCKS P89LPC901/902/903 Low Power Select (P89LPC901) The P89LPC901 is designed to run at 12MHz (CCLK) maximum. However, if CCLK is 8MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a ’1’ to lower the power consumption further. On any reset, CLKLP is ’0’ allowing highest performance. This bit can then be set in software if CCLK is running at 8MHz or slower.
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User’s Manual - Preliminary - Philips Semiconductors CLOCKS 2003 Dec 8 P89LPC901/902/903 34
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User’s Manual - Preliminary - Philips Semiconductors INTERRUPTS P89LPC901/902/903 3. INTERRUPTS The P89LPC901/902/903 use a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P89LPC901 supports 6 interrupt sources: timers 0 and 1, brownout detect, watchdog/ realtime clock, keyboard, and the comparator.
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User’s Manual - Preliminary - Philips Semiconductors INTERRUPTS P89LPC901/902/903 Table 3-2: Summary of Interrupts - P89LPC901 Interrupt Flag Bit(s) Vector Address Interrupt Enable Bit(s) Interrupt Priority Arbitration Ranking Power down Wakeup Timer 0 Interrupt TF0 000Bh ET0 (IEN0.1) IP0H.1, IP0.1 3 No Timer 1 Interrupt TF1 001Bh ET1 (IEN0.3) IP0H.3, IP0.3 5 No BOF Description Brownout Detect 002Bh EBO (IEN0.5) IP0H.5, IP0.5 1 Yes WDOVF/ RTCF 0053h EWDRT (IEN0.6) IP0H.
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User’s Manual - Preliminary - Philips Semiconductors INTERRUPTS P89LPC901/902/903 External Interrupt Inputs The P89LPC901/902/903 have a Keypad Interrupt function (see Keypad Interrupt (KBI) on page 79). This can be used as an external interrupt input. If enabled when the P89LPC901/902/903 is put into Power down or Idle mode, the keypad interrupt will cause the processor to wake up and resume operation. Refer to the section on Power Reduction Modes for details.
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User’s Manual - Preliminary - Philips Semiconductors INTERRUPTS P89LPC901/902/903 BOPD EBO RTCF ERTC (RTCCON.1) WDOVF Wakeup (if in Power down) KBIF EKBI EWDRT CMF EC EA (IE0.7) TF1 ET1 Interrupt to CPU TF0 ET0 Figure 3-2: Interrupt sources, enables, and Power down Wake-up sources - P89LPC902 BOPD EBO RTCF ERTC (RTCCON.1) WDOVF Wakeup (if in Power down) KBIF EKBI EWDRT CMF EC EA (IE0.
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User’s Manual - Preliminary - Philips Semiconductors I/O PORTS P89LPC901/902/903 4. I/O PORTS The P89LPC901/902/903 has between 3 and 6 I/O pins.
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User’s Manual - Preliminary - Philips Semiconductors I/O PORTS P89LPC901/902/903 The third pullup is referred to as the "strong" pullup. This pullup is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong pullup turns on for two CPU clocks quickly pulling the port pin high . The quasi-bidirectional port configuration is shown in Figure 4-1.
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User’s Manual - Preliminary - Philips Semiconductors I/O PORTS P89LPC901/902/903 Input-Only Configuration The input port configuration is shown in Figure 4-3. It is a Schmitt-triggered input that also has a glitch suppression circuit.
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User’s Manual - Preliminary - Philips Semiconductors I/O PORTS P89LPC901/902/903 Table 4-3: Port Output Configuration - P89LPC901 Port Pin Configuration SFR Bits Alternate Usage Notes P0M2.4 KBI4,CIN1A P0M2.5 KBI5,CMPREF Refer to section "Port 0 Analog Functions" for usage as analog inputs CINxA and CMPREF. P1M2.2 T0 PxM1.y PxM2.y P0.4 P0M1.4 P0.5 P0M1.5 P1.2 P1M1.2 P1.5 not configurable RST P3.0 P3M1.0 P3M2.0 XTAL2,CLKOUT P3.1 P3M1.1 P3M2.1 XTAL1 Input only.
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User’s Manual - Preliminary - Philips Semiconductors I/O PORTS P89LPC901/902/903 All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.
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User’s Manual - Preliminary - Philips Semiconductors I/O PORTS 2003 Dec 8 P89LPC901/902/903 44
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User’s Manual - Preliminary - Philips Semiconductors TIMERS 0 AND 1 P89LPC901/902/903 5. TIMERS 0 AND 1 The P89LPC901/902/903 has two general-purpose counter/timers which are similar to the 80C51 Timer 0 and Timer 1. Timer 0 of the P89LPC901 can be configured to operate either as a timer or event counter (see Figure 5-1). An option to automatically toggle the T0 pin upon timer overflow has been added.
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User’s Manual - Preliminary - Philips Semiconductors TIMERS 0 AND 1 P89LPC901/902/903 TAMOD - P89LPC901 7 6 5 4 3 2 1 0 Address: 8Fh - - - - - - - T0M2 Not bit addressable Reset Source(s): Any reset Reset Value: xxx0xxx0B BIT SYMBOL TAMOD.7-1 TAMOD.0 - FUNCTION Reserved for future use. Should not be set to 1 by user programs. T0M2 TnM2-TnM0 Mode Select bit 2 for Timer 0. Used with T0M1 and T0M0 in the TMOD register to determine Timer 0 mode (P89LPC901).
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User’s Manual - Preliminary - Philips Semiconductors TIMERS 0 AND 1 P89LPC901/902/903 Mode 3 When Timer 1 is in Mode 3 it is stopped. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for Mode 3 on Timer 0 is shown in Figure 5-7. TL0 uses the Timer 0 control bits: TR0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1.
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User’s Manual - Preliminary - Philips Semiconductors TIMERS 0 AND 1 P89LPC901/902/903 Overflow T0C/T = 0 PCLK T0 Pin* T0C/T = 1 Control TLn (5-bits) THn (8-bits) TFn Interrupt Toggle TRn T0 Pin* ENT0 (AUXR1.4) * T0 Pin functions available on P89LPC901 Figure 5-4: Timer/Counter 0 or 1 in Mode 0 (13-bit counter) Overflow T0C/T = 0 PCLK T0 Pin* T0C/T = 1 Control TLn (8-bits) THn (8-bits) TFn Interrupt Toggle TRn T0 Pin* ENT0 (AUXR1.
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User’s Manual - Preliminary - Philips Semiconductors TIMERS 0 AND 1 P89LPC901/902/903 C/T = 0 PCLK T0 Pin* C/T = 1 Control TL0 (8-bits) Overflow TF0 Interrupt Toggle T0 Pin* TR0 ENT0 PCLK Control TH0 (8-bits) TR1 Overflow TF1 Interrupt * T0 Pin functions available on P89LPC901 Figure 5-7: Timer/Counter 0 Mode 3 (two 8-bit counters) T0C/T = 0 PCLK Control TL0 (8-bits) Overflow TF0 Interrupt Reload TH0 on falling transition and (256-TH0) on rising transition Toggle TR0 T0 Pin T
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User’s Manual - Preliminary - Philips Semiconductors TIMERS 0 AND 1 2003 Dec 8 P89LPC901/902/903 50
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User’s Manual - Preliminary - Philips Semiconductors REAL-TIME CLOCK/SYSTEM TIMER P89LPC901/902/903 6. REAL-TIME CLOCK/SYSTEM TIMER The P89LPC901/902/903 has a simple Real-time clock/system timer that allows a user to continue running an accurate timer while the rest of the device is powered down. The Real-time clock can be an interrupt or a wake-up source (see Figure 6-1). The Real-time clock is a 23-bit down counter.
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User’s Manual - Preliminary - Philips Semiconductors REAL-TIME CLOCK/SYSTEM TIMER P89LPC901/902/903 Table 6-1: Real-time Clock/System Timer Clock Source - P89LPC901 FOSC2 FOSC1 FOSC0 RTCS1:0 (UCFG1.2) (UCFG1.1) (UCFG1.
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User’s Manual - Preliminary - Philips Semiconductors REAL-TIME CLOCK/SYSTEM TIMER P89LPC901/902/903 Table 6-2: :Real-time Clock/System Timer Clock Source - P89LPC902/903 FOSC2 FOSC1 FOSC0 RTCS1:0 (UCFG1.2) (UCFG1.1) (UCFG1.
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User’s Manual - Preliminary - Philips Semiconductors REAL-TIME CLOCK/SYSTEM TIMER P89LPC901/902/903 RTCCON Address: D1h Not bit addressable 7 6 5 4 3 2 1 0 RTCF RTCS1 RTCS0 - - - ERTC RTCEN Reset Source(s): Power-up only Reset Value: 011xxx00B BIT RTCCON.7 SYMBOL RTCF RTCCON.6-5 RTCS1-0 RTCCON.4-2 - FUNCTION Real-time Clock Flag. This bit is set to ’1’ when the 23-bit Real-time clock reaches a count of ’0’. It can be cleared in software.
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User’s Manual - Preliminary - Philips Semiconductors POWER MONITORING FUNCTIONS P89LPC901/902/903 7. POWER MONITORING FUNCTIONS The P89LPC901/902/903 incorporates power monitoring functions designed to prevent incorrect operation during initial poweron and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout Detect. Brownout Detection The Brownout Detect function determines if the power supply voltage drops below a certain level.
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User’s Manual - Preliminary - Philips Semiconductors POWER MONITORING FUNCTIONS BOE (UCFG1.5) 0 (erased) 1 (programmed) P89LPC901/902/903 PMOD1-0 (PCON.1-0) BOPD (PCON.5) BOI (PCON.4) EBO (IEN0.5) EA (IEN0.7) XX X X X X 11 (total power down) X X X X 1 (brownout detect powered down) X X X Brownout disabled. VDD operating range is 2.4V-3.6V. However, BOPD is default to ’0’ upon power-up. X X Brownout reset enabled. VDD operating range is 2.7V3.6V. Upon a brownout reset, BOF (RSTSRC.
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User’s Manual - Preliminary - Philips Semiconductors POWER MONITORING FUNCTIONS P89LPC901/902/903 Power Reduction Modes The P89LPC901/902/903 supports three different power reduction modes as determined by SFR bits PCON.1-0 (see Table 7-2): PMOD1 (PCON.1) PMOD0 (PCON.0) 0 0 Normal Mode (Default) - no power reduction. 0 1 Idle Mode. The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated.
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User’s Manual - Preliminary - Philips Semiconductors POWER MONITORING FUNCTIONS 7 PCON 6 SMOD1 SMOD0 Address: 87h P89LPC901/902/903 5 4 3 2 BOPD BOI GF1 GF0 1 0 PMOD1 PMOD0 Not bit addressable Reset Source(s): Any reset Reset Value: BIT 00000000B SYMBOL FUNCTION PCON.7 SMOD1 Double Baud Rate bit for the serial port (UART) when Timer 1 is used as the baud rate source. When 1, the Timer 1 overflow rate is supplied to the UART.
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User’s Manual - Preliminary - Philips Semiconductors POWER MONITORING FUNCTIONS P89LPC901/902/903 PCONA Address: B5H Not bit addressable 7 6 5 4 3 2 1 0 RTCPD - VCPD - - - SPD - Reset Source(s): Any reset Reset Value: 00000000B BIT SYMBOL FUNCTION PCONA.7 RTCPD Real-time Clock Power down: When ’1’, the internal clock to the Real-time Clock is disabled. PCONA.6 - PCONA.5 VCPD PCONA.4 - Not used. Reserved for future use. PCONA.3 - Not used. Reserved for future use. PCONA.
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User’s Manual - Preliminary - Philips Semiconductors POWER MONITORING FUNCTIONS 2003 Dec 8 60 P89LPC901/902/903
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User’s Manual - Preliminary - Philips Semiconductors UART (P89LPC903) P89LPC901/902/903 8. UART (P89LPC903) The P89LPC903 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC903 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator.
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User’s Manual - Preliminary - Philips Semiconductors UART (P89LPC903) P89LPC901/902/903 SFR Space The UART SFRs are at the following locations: Table 8-1: SFR Locations for UARTs Register Description SFR Location PCON Power Control 87H SCON Serial Port (UART) Control 98H SBUF Serial Port (UART) Data Buffer 99H SADDR Serial Port (UART) Address A9H SADEN Serial Port (UART) Address Enable B9H SSTAT Serial Port (UART) Status BAH BRGR1 Baud Rate Generator Rate High Byte BFH BRGR0 Baud
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User’s Manual - Preliminary - Philips Semiconductors UART (P89LPC903) P89LPC901/902/903 BRGCON Address: BDh 7 6 5 4 3 2 Not bit addressable - - - - - - 1 0 SBRGS BRGEN Reset Source(s): Any reset Reset Value: xxxxxx00B BIT SYMBOL BRGCON.7-2 - FUNCTION Reserved for future use. Should not be set to 1 by user programs. BRGCON.1 SBRGS Select Baud Rate Generator as the source for baud rates to UART in modes 1 & 3 (see Table for details) BRGCON.0 BRGEN Baud Rate Generator Enable.
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User’s Manual - Preliminary - Philips Semiconductors UART (P89LPC903) P89LPC901/902/903 . SCON Address: 98h Bit addressable 7 6 5 4 3 2 1 0 SM0/FE SM1 SM2 REN TB8 RB8 TI RI Reset Source(s): Any reset Reset Value: 00000000B BIT SCON.7 SCON. 6 SYMBOL SM0/FE SM1 FUNCTION The use of this bit is determined by SMOD0 in the PCON register. If SMOD0 = 0, this bit is read and written as SM0, which with SM1, defines the serial port mode.
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User’s Manual - Preliminary - Philips Semiconductors UART (P89LPC903) P89LPC901/902/903 SSTAT Address: BAh Not bit addressable Reset Source(s): Any reset 7 6 5 4 3 2 1 0 DBMOD INTLO CIDIS DBISEL FE BR OE STINT Reset Value: 00000000B BIT SYMBOL FUNCTION SSTAT.7 DBMOD Double buffering mode. When set = 1 enables double buffering. Must be ’0’ for UART mode 0. In order to be compatible with existing 80C51 devices, this bit is reset to ’0’ to disable double buffering. SSTAT.
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User’s Manual - Preliminary - Philips Semiconductors UART (P89LPC903) P89LPC901/902/903 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...
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User’s Manual - Preliminary - Philips Semiconductors UART (P89LPC903) P89LPC901/902/903 More About UART Modes 2 and 3 Reception is the same as in Mode 1. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. (a) RI = 0, and (b) Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is lost, and RI is not set.
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User’s Manual - Preliminary - Philips Semiconductors UART (P89LPC903) P89LPC901/902/903 Double Buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, provided the next character is written between the start bit and the stop bit of the previous character.
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User’s Manual - Preliminary - Philips Semiconductors UART (P89LPC903) P89LPC901/902/903 TxD Write to SBUF Tx Interrupt Single Buffering (DBMOD/SSTAT.7 = 0), Early Interrupt (INTLO/SSTAT.6 = 0) is Shown TxD Write to SBUF Tx Interrupt Double Buffering (DBMOD/SSTAT.7 = 1), Early Interrupt (INTLO/SSTAT.6 = 0) is Shown, No Ending Tx Interrupt (DBISEL/SnSTAT.4 = 0) TxD Write to SBUF Tx Interrupt Double Buffering (DBMOD/SSTAT.7 = 1), Early Interrupt (INTLO/SSTAT.
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User’s Manual - Preliminary - Philips Semiconductors UART (P89LPC903) P89LPC901/902/903 - If DBISEL is ’1’ and INTLO is ’1’, a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter (which is also the last data). 7. If there is more data, the CPU writes to TB8 again. 8. The CPU writes to SBUF again. Then: - If INTLO is ’0’, the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter.
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User’s Manual - Preliminary - Philips Semiconductors UART (P89LPC903) P89LPC901/902/903 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.
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User’s Manual - Preliminary - Philips Semiconductors UART (P89LPC903) 2003 Dec 8 P89LPC901/902/903 72
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User’s Manual - Preliminary - Philips Semiconductors RESET P89LPC901/902/903 9. RESET The P1.5/RST pin can function as either an active low reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. NOTE: During a power-on sequence, The RPE selection is overriden and this pin will always functions as a reset input.
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User’s Manual - Preliminary - Philips Semiconductors RESET P89LPC901/902/903 RSTSRC Address: DFH 7 6 5 4 3 2 1 0 Not bit addressable - - BOF POF R_BK R_WD R_SF R_EX Reset Sources: Power-on only Reset Value: xx110000B (This is the power-on reset value. Other reset sources will set corresponding bits.) BIT RSTSRC.7-6 SYMBOL - FUNCTION Reserved for future use. Should not be set to 1 by user programs. RSTSRC.5 BOF Brownout Detect Flag.
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User’s Manual - Preliminary - Philips Semiconductors ANALOG COMPARATORS P89LPC901/902/903 10. ANALOG COMPARATORS One analog comparator is provided on the P89LPC901 and two analog comparators are provided on both the P89LPC902 and P89LPC903 . Comparator operation is such that the output is a logical one when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. The output may be read in a register.
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User’s Manual - Preliminary - Philips Semiconductors ANALOG COMPARATORS P89LPC901/902/903 Comparator + CIN1A CO1 Change Detect Interrupt CMF1 (P0.5) CMPREF - Vref EC CN1 Figure 10-2: Comparator Input and Output Connections - P89LPC901 Comparator 1 OE1 + (P0.4) CIN1A CO1 (P0.5) CMPREF CMP1 (P0.6) - Vref Change Detect CN1 CMF1 Interrupt Change Detect EC CMF2 Comparator 2 + (P0.2) CIN2A CMP2 (P0.
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User’s Manual - Preliminary - Philips Semiconductors ANALOG COMPARATORS P89LPC901/902/903 Comparator 1 + (P0.4) CIN1A CO1 (P0.5) CMPREF - Vref Change Detect CN1 CMF1 Interrupt Change Detect EC CMF2 Comparator 2 + (P0.2) CIN2A CO2 CN2 Figure 10-4: Comparator Input and Output Connections - P89LPC903 CN, OE = 0 0 CINnA + CMPREF - CN, OE = 0 1 COn CINnA + CMPREF - + Vref (1.23V) - CMPn CN, OE = 1 1 CN, OE = 1 0 CINnA COn COn CINnA + Vref (1.
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User’s Manual - Preliminary - Philips Semiconductors ANALOG COMPARATORS P89LPC901/902/903 an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator flag, CMFx, after disabling the comparator.
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User’s Manual - Preliminary - Philips Semiconductors KEYPAD INTERRUPT (KBI) P89LPC901/902/903 11. KEYPAD INTERRUPT (KBI) The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when the Port 0 bits are equal to or not equal to a certain pattern. This function can be used for keypad recognition. The user can configure the port via SFRs for different tasks. There are three SFRs used for this function.
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User’s Manual - Preliminary - Philips Semiconductors KEYPAD INTERRUPT (KBI) KBPATN 7 6 Address: 93h - - P89LPC901/902/903 5 4 KBPATN.5 KBPATN.4 3 2 1 0 - KBPATN.2 - - Not bit addressable Reset Source(s): Any reset Reset Value: 11111111B BIT SYMBOL KBPATN.
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User’s Manual - Preliminary - Philips Semiconductors KEYPAD INTERRUPT (KBI) KBMASK 7 Address: 86h - 6 P89LPC901/902/903 5 4 KBMASK.6 KBMASK.5 KBMASK.4 3 2 1 0 - KBMASK.2 - KBMASK.0 Not bit addressable Reset Source(s): Any reset Reset Value: 00000000B BIT SYMBOL FUNCTION KBMASK.7 - Reserved. KBMASK.6 - When set, enables P0.6 as a cause of a Keypad Interrupt. KBMASK.5 - When set, enables P0.5 as a cause of a Keypad Interrupt. KBMASK.4 - When set, enables P0.
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User’s Manual - Preliminary - Philips Semiconductors KEYPAD INTERRUPT (KBI) 2003 Dec 8 P89LPC901/902/903 82
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User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER P89LPC901/902/903 12. WATCHDOG TIMER The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count. The watchdog timer can only be reset by a power-on reset.
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User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER Watchdog Oscillator PCLK P89LPC901/902/903 ÷32 ÷2 ÷32 ÷64 ÷2 ÷128 ÷2 ÷256 ÷2 ÷512 ÷2 ÷1024 ÷2 ÷2048 ÷2 ÷4096 WDCLK after a watchdog feed sequence PRE2 DECODE PRE1 PRE0 TO WATCHDOG DOWN COUNTER (after one prescaler count delay 000 001 010 011 100 101 110 111 Figure 12-1: Watchdog Prescaler Feed Sequence The watchdog timer control register and the 8-bit down counter (Figure 12-3) are not directly loaded by the user.
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User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER P89LPC901/902/903 MOV WFEED1,#0A5h ; do watchdog feed part 1 MOV WFEED2,#05Ah ; do watchdog feed part 2 SETB EA ; enable interrupt In timer mode (WDTE = 0), WDCON is loaded to the control register every CCLK cycle (no feed sequence is required to load the control register), but a feed sequence is required to load from the WDL SFR to the 8-bit down counter before a time-out occurs.
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User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER P89LPC901/902/903 Table 12-2: P89LPC901/902/903 Watchdog Timeout Values PRE2-PRE0 Watchdog Clock Source WDL in decimal) Timeout Period (in watchdog clock cycles) 400KHz Watchdog Oscillator Clock (Nominal) 12MHz CCLK (6MHz CCLK/2 Watchdog Clock) 0 33 82.5µs 5.50µs 255 8,193 20.5ms 1.37ms 0 65 162.5µs 10.8µs 255 16,385 41.0ms 2.73ms 0 129 322.5µs 21.5µs 255 32,769 81.9ms 5.46ms 0 257 642.5µs 42.
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User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER P89LPC901/902/903 Watchdog Timer in Timer Mode Figure 12-4 shows the Watchdog Timer in Timer Mode. In this mode, any changes to WDCON are written to the shadow register after one watchdog clock cycle. A watchdog underflow will set the WDTOF bit. If IEN0.6 is set, the watchdog underflow is enabled to cause an interrupt. WDTOF is cleared by writing a '0' to this bit in software.
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User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER P89LPC901/902/903 Note: When switching clocks, it is important that the old clock source is left enabled for 2 clock cycles after the feed completes. Otherwise, the watchdog may become disabled when the old clock source is disabled. For example, suppose PCLK (WCLK=0) is the current clock source.
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User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER P89LPC901/902/903 Periodic wakeup from Power down without an external oscillator Without using an external oscillator source, the power consumption required in order to have a periodic wakeup is determined by the power consumption of the internal oscillator source used to produce the wakeup.The Real-time clock running from the internal RC oscillator can be used. The power consumption of this oscillator is approximately 300uA.
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User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER 2003 Dec 8 P89LPC901/902/903 90
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User’s Manual - Preliminary - Philips Semiconductors ADDITIONAL FEATURES P89LPC901/902/903 13. ADDITIONAL FEATURES The AUXR1 register contains several special purpose control bits that relate to several chip features. AUXR1 is described in Figure 13-1. AUXR1 Address: A2h 7 6 5 4 3 2 1 0 CLKLP EBRR - - SRST 0 - DPS Not bit addressable Reset Source(s): Any reset Reset Value: 000000x0B BIT SYMBOL FUNCTION AUXR1.7 CLKLP Clock Low Power Select.
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User’s Manual - Preliminary - Philips Semiconductors ADDITIONAL FEATURES P89LPC901/902/903 • MOV DPTR, #data16 Load the Data Pointer with a 16-bit constant. • MOVCA, @A+DPTR Move code byte relative to DPTR to the accumulator. • MOVXA, @DPTR Move data byte the accumulator to data memory relative to DPTR. • MOVX@DPTR, A Move data byte from data memory relative to DPTR to the accumulator.
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User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC901/902/903 14. FLASH PROGRAM MEMORY General description The P89LPC901/902/903 Flash memory provides in-circuit electrical erasure and programming. The Flash can be read and written as bytes. On-chip erase and write timing generation contribute to a user-friendly programming interface. The cell is designed to optimize the erase and programming mechanisms.
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User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC901/902/903 ing to FMDATA. However, each location in the page register can only be written once following each LOAD command. Attempts to write to a page register location more than once should be avoided. FMADRH and FMADRL[7:4] are used to select a page of code memory for the erase-program function.
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User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY FMCON Address: E4h P89LPC901/902/903 7 6 5 4 3 2 1 0 - - - - HVA HVE SV OI Not bit addressable Reset Source(s): Any reset Reset Value: BIT SYMBOL FMCON.7-4 - FUNCTION Reserved. FMCON.3 HVA Set if either an interrupt or a brown-out is detected during a program or erase cycle. Also set if the brown-out detector is disabled at the start of a program or erase cycle. FMCON.2 HVE High voltage error.
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User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY unsigned char idata dbytes[16]; unsigned char Fm_stat; P89LPC901/902/903 // data buffer // status result bit PGM_USER (unsigned char, unsigned char); bit prog_fail; void main () { prog_fail=PGM_USER(0x1F,0xC0); } bit PGM_USER (unsigned char page_hi, unsigned char page_lo) { #define LOAD 0x00 // clear page register, enable loading #define EP 0x68 // erase & program page unsigned char i; // loop count FMCON = LOAD; FMADRH = page_hi
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User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC901/902/903 Table 14-1: Flash elements accesable through IAP-Lite Element Address Description UCFG1 00h User Configuration byte 1.
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User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC901/902/903 r ;* Inputs: ;* R5 = data to write(byte) ;* R7 = element address(byte) ;* Outputs: ;* None CONF EQU * * * * * 6CH WR_ELEM: MOV MOV MOV MOV MOV ANL JNZ CLR RET BAD: SETB RET FMADRL,R7 FMCON,#CONF FMDAT,R5 R7,FMCON A,R7 A,#0FH BAD C ;write the address ;load CONF command ;write the data ;copy status for return ;read status ;save only four lower bits ;see if good or bad ;clear error flag if good ;and return C
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User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC901/902/903 #include
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User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY UCFG1 Address: xxxxh P89LPC901/902/903 7 6 5 4 3 2 1 0 WDTE RPE BOE WDSE - FOSC2 FOSC1 FOSC0 Default: 63h BIT SYMBOL FUNCTION UCFG1.7 WDTE Watchdog timer reset enable. When set =1, enables the watchdog timer reset. When cleared = 0 , disables the watchdog timer reset. The timer may still be used to generate an interrupt. Refer to Table 12-1 for details. UCFG1.6 RPE Reset pin enable.
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User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC901/902/903 USER SECURITY BYTES There are four User Sector Security Bytes (SEC0, ..., SEC3), each corresponding to one sector and having the following bit assignments: SECx Address: xxxxh 7 6 5 4 3 2 - - - - - EDISx 1 0 SPEDISx MOVCDISx Unprogrammed value: 00h BIT SYMBOL SECx.7-3 - FUNCTION Reserved (should remain unprogrammed at zero). SECx.2 EDISx Erase Disable x.
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User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC901/902/903 Boot Vector BOOTVEC 7 6 5 Address: xxxxh - - - 4 3 2 1 0 BOOTV4 BOOTV3 BOOTV2 BOOTV1 BOOTV0 Factory default value: 00h BIT SYMBOL FUNCTION BOOTVEC.7-5 - Reserved (should remain unprogrammed at zero). BOOTVEC.4-0 - Boot Vector.
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User’s Manual - Preliminary - Philips Semiconductors INSTRUCTION SET P89LPC901/902/903 15.
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User’s Manual - Preliminary - Philips Semiconductors INSTRUCTION SET P89LPC901/902/903 Mnemonic Hex code Bytes Cycles AND A to direct byte 2 1 52 AND immediate to direct byte 3 2 53 ORL A,Rn OR register to A 1 1 48-4F ORL A,dir OR direct byte to A 2 1 45 ORL A,@Ri OR indirect memory to A 1 1 46-47 ORL A,#data OR immediate to A 2 1 44 ORL dir,A OR A to direct byte 2 1 42 OR immediate to direct byte 3 2 43 XRL A,Rn Exclusive-OR register to A 1 1 68-6F XRL A,di
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User’s Manual - Preliminary - Philips Semiconductors INSTRUCTION SET P89LPC901/902/903 Mnemonic Hex code Bytes Cycles Move immediate to direct byte 3 2 75 MOV @Ri,A Move A to indirect memory 1 1 F6-F7 MOV @Ri,dir Move direct byte to indirect memory 2 2 A6-A7 MOV @Ri,#data Move immediate to indirect memory 2 1 76-77 Move immediate to data pointer 3 2 90 Move code byte relative DPTR to A 1 2 93 Move code byte relative PC to A 1 2 94 MOVX A,@Ri Move external data(A8) to
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User’s Manual - Preliminary - Philips Semiconductors INSTRUCTION SET P89LPC901/902/903 Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 2 2 116F1 LCALL addr 16 Long jump to subroutine 3 2 12 RET Return from subroutine 1 2 22 RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 016E1 LJMP addr 16 Long jump unconditional 3 2 02 Short jump (relative address) 2 2 80 JC rel Jump on carry = 1 2 2 40 JNC r
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User’s Manual - Preliminary - Philips Semiconductors REVISION HISTORY P89LPC901/902/903 16. REVISION HISTORY 2003 Dec 8 Removed ENCLK bit from P89LPC902 and P89LPC903 TRIM SFRs. Modified Fig 2-1 to reflect ENCLK only on the P89LPC901. Removed RCCLK from TRIM SFR description (Fig2-1). Changed comparator SFR and bit names to match 89LPC9xx product line terminology. Added Revision History chapter. Added instruction set chapter.
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User’s Manual - Preliminary - Philips Semiconductors REVISION HISTORY 2003 Dec 8 P89LPC901/902/903 108
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Philips Semiconductors User’s Manual - Preliminary - INDEX P89LPC901/902/903 17.
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Philips Semiconductors User’s Manual - Preliminary - INDEX P89LPC901/902/903 block fill 7, 27, 35, 39, 45, 51, 55, 61, 73, 75, 79, 83, 91, 93, 103, 107 hardware reset 7, 27, 35, 39, 45, 51, 55, 61, 73, 75, 79, 83, 91, 93, 103, 107 Dual Data Pointers 91 F FLASH 7, 27, 35, 39, 45, 51, 55, 61, 73, 75, 79, 83, 91, 93, 103, 107 Boot Status 102 Boot Vector 102 features 93 hardware activation of the boot loader 73 power-on reset code execution 73 I IAP programming 93 Interrupts 39 arbitration ranking 35 extern
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Philips Semiconductors User’s Manual - Preliminary - INDEX P89LPC901/902/903 FLASH code 93 organization 25 O Oscillator high speed crystal option 27, 28 low speed crystal option 27 medium speed crystal option 27 R-C option 28 watchdog (WDT) option 29 P Pin configuration 7, 8 Port 0 12, 14, 15 Port 3 12 Ports additional features 42 I/O 39 input only configuration 41 open drain output configuration 40 Port 0 analog functions 41 Port 2 in 20-pin package 41 push-pull output configuration 41 quasi-bidirectio
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Philips Semiconductors User’s Manual - Preliminary - INDEX P89LPC901/902/903 S SFR AUXR1 91 BRGCON 63 CMPn 75 KBCON 80 KBMASK 80, 81 KBPATN 79, 80 PCON 58 PCONA 59 RSTSRC 74 RTCCON 54 SCON 64 SSTAT 65 TAMOD 46 TCON 47 TMOD 45 TRIM 28, 29, 95 UCFG1 100 WDCON 85 SFRs undefined locations, use of 16 Special Function Registers (SFR) table 16, 19, 22 T Timer/counters 45 mode 0 46 mode 1 46 mode 2 (8-bit auto reload) 46 mode 3 (seperates TL0 & TH0) 47 mode 6 (8-bit PWM) 47 toggle output 49 TRIM (SFR) power-on
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Philips Semiconductors User’s Manual - Preliminary - INDEX P89LPC901/902/903 double buffering in 9-bit mode 69 double buffering in different modes 68 framing error 63, 67 mode 0 65 mode 0 (shift register) 61 mode 1 66 mode 1 (8-bit variable baud rate) 61 mode 2 67 mode 2 (9-bit fixed baud rate) 61 mode 3 67 mode 3 (9-bit variable baud rate) 61 multiprocessor communications 70 SFR locations.
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Philips Semiconductors User’s manual – Preliminary – P89LPC901/902/903 Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device.