INTEGRATED CIRCUITS SAA7785 ThunderBird Avenger PCI Audio Accelerator Preliminary specification 1999 Nov 12
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 IEEE 1394 devices via 14 Channel Virtual Write Master • Superior hardware acceleration for minimum CPU consumption • Broadest API compatibility including DirectSound3DTM , EAXTM , and A3DTM • 64 hardware wavetable polyphony • Professional soft-synth with 256 voice polyphony and XG support GENERAL DESCRIPTION The SAA7785 ThunderBird AvengerTM is a high-performance PCI audio accelerator offering the ultim
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION SAA7785 TQFP128 Thin quad flat pack; 128 leads (lead length 1.00 mm); body 14 x 14 x 1.00 mm 25-90040 SAA7785 TQFP100 Thin quad flat pack; 100 leads (lead length 1.00 mm); body 14 x 14 x 1.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator BLOCK DIAGRAM AC Link Interface I 2S Interface AC LINK PCI Bus Test Port INTA# PCI Master/Slave Interface Serial Interrupt Controller GPIO General Purpose I/O GamePort Game Port Interface PLL Test Logic AC97 Xtal_out S/P DIF Output PCI Configuration Headers Legacy DMA Interface SoundBlaster Registers OPL3 Registers INTRs DSP Core DSP Code ROM DSP Code RAM DSP Memory Controller Virtual Registe
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 PINNING Signal and Pin Names for 128 pin SAA7785 ThunderBird AvengerTM TABLE 1 PIN # PIN NAME 1 BIT_CLK 33 GNT# 65 AD22 97 AD12 2 SDATA_OUT 34 PME# 66 VDD 98 AD11 3 SDATA_IN0 35 RST# 67 AD21 99 AD10 4 SDATA_IN1 36 VSS 68 AD20 100 NWELL1 5 AC_RST# 37 PCLK 69 AD19 101 PGPIO4 6 VSS 38 PCGNT# 70 VSS 102 AD9 7 JAB1 39 PCREQ# 71 AD18 103 VDD 8 JBB1
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator FIGURE 2 SAA7785 PIN CONFIGURATION Notes: 1. Package body size is 14 mm. 2. Scale is approx 1” = 5.08 mm (5X actual size). 3. Use package bond form nuber 23-xxxxx.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 PINNING PIN DEFINITIONS FOR THE 100 Pin SAA7785 ThunderBird AvengerTM TABLE 2 PIN # PIN NAME 1 BIT_CLK 30 PCLK 59 VSS 87 AD5 2 SDATA_OUT 31 PCGNT# 60 C/BE2# 88 VSS 3 SDATA_IN 32 PCREQ# 61 FRAME# 89 AD4 4 AC_RST# 33 GNT# 62 IRDY# 90 AD3 5 VSS 34 VDDIC 63 VDDIC 91 AD2 6 JAB1 35 REQ# 64 TRDY# 92 VSSIC 7 JBB1 36 AD31 65 DEVSEL# 93 AD1 8 JACX 37 AD
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 Notes: 1. Package body size is 14 mm. 2. Scale is approx 1” = 5.08 mm (5X actual size). 3. Use package bond form nuber 23-61269.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 FUNCTIONAL OVERVIEW AC3 data from a DVD directly to an AC3 decoder. The S/PDIF stereo output capability allows users to connect to a variety of consumer audio equipment, such as a stereo receiver, minidisk, or digital speakers. S/PDIF IN support through the I 2S port enables digital connection from a CD player or other audio equipment that utilizes the S/PDIF format.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 total simultaneous voices. ActiMediaTM DSP Architecture ActiMediaTM DSP architecture combines the strengths of programmable and fixed function DSP architectures. Programmability enables custom features, field upgrades, and simple application development, while an array of gate-efficient fixed function DSP processors (accelerators) operate in parallel to provide an excellent price/performance ratio.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 Architectural Overview The SAA7785 ThunderBird AvengerTM is a multi-functional device that provides sound processing producing SoundBlaster-compatible emulation, DirectSound acceleration, 3D sound, spatialization, special effects, and 64-voice wavetable synthesis through the use of a Pine Digital Signal Processor (DSP) as the primary engine.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 The SAA7785 ThunderBird AvengerTM chip is designed to operate on any PCI system with the proper software support. Software support is required for non-DOS applications, such as Windows(tm) drivers. Non Pentium(tm) based system can also be supported with the additional software.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 timer data can be accessed as an I/O device. This timer can be used by game developers to keep track of time elapsed to synchronize the video to the audio stream. The timer can be polled or interrupt driven and is selectable by the user application. DMA DMA is for the Sound Blaster registers, the DSP Mastering Device (DMD), and the S/P DIF output.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 the addresses and fetch the audio samples from system memory. The Address Generator is also capable of looping without intervention from the DSP code. The DSP kills voices by instructing the Address Generator to stop fetching data. Once the samples are fetched, they are stored in the Virtual Register’s input sample buffer for processing by the Sample Fetch Accelerator.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 SERIAL PORT INTERFACES OVERVIEW The SAA7785 chip will contain an S/PDIF Consumer Grade transmit port and an I2S transmit/receive pair. These serial ports are designed to exchange digital audio data but can be used for any type of data transfer assuming the bandwidth is adequate. Currently, these ports are connected to the DSP data bus.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator FIGURE 4 SAA7785 I2S SERIAL PORTS BLOCK DIAGRAM Right Data Transmit Shift Register Left Data Transmit Control Logic CCLK XSCLK XWS I2S Ports Clock Divider RWS RSCLK Receive Control Logic Left Data Receive Shift Register Right Data DSP DATA BUS 1999 Nov 12 XDATA 16 RDATA
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator FIGURE 5 SAA7785 S/PDIF TRANSMIT PORT BLOCK DIAGRAM DSP DATA BUS Audio Data Holding Registers Audio Data Shift Registers Validity Bit Generation Aux Data Holding Registers Aux Data Shift Registers Ctl/Channel Stat Holding Registers Ctl/Channel Stat Shift Registers User Data Holding Register User Data Shift Register MUX Bi-Phase Mark Encoder Line Driver SPDO S/PDIF XMT Port Status Register CCLK DC
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 Game Port The SAA7785 ThunderBird AvengerTM Game Port interface is designed to emulate the PC-AT based legacy joystick operation as well as support of a digital joystick mode. The legacy or analog, type of operation is designed to support all legacy software that uses the original joystick address and the method for resolving the joystick axes positions.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 SAA7785 SIGNAL DEFINITIONS PCI LOCAL BUS INTERFACE SIGNALS AD[31:0] PCI Address/Data AD[31:0] contains a physical byte address during the first clock of a PCI transaction, and data during subsequent clocks. When the SAA7785 is a PCI master, AD[31:0] are outputs during the address phase of a transaction.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator STOP# SAA7785 PCI Bus Stop (Target Initiated Termination) When the SAA7785 is a PCI master, STOP# is an input which causes the SAA7785 to complete, abort or retry the transfer, depending on the state of TRDY# and DEVSEL#. When the SAA7785 is a PCI slave, it drives STOP# as active (LOW) to terminate or retry a transaction.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator GNT# SAA7785 PCI Bus Grant An asserted GNT# pin indicates that the PCI master arbiter has granted bus ownership to the SAA7785 chip. INTA# PCI Bus Interrupt A The interrupt output is a PCI compatible active low level sensitive interrupt. It is only used if the SAA7785 is used in a non Common Architecture system. Otherwise it is tri-stated. It is driven low when any of the internal interrupts are asserted.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 PCI GENERAL PURPOSE I/O PGPIO[7:0] PCI General Purpose Input/Outputs These eight pins are used as controls or data to devices external to the SAA7785 chip. Each are independently controlled.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator JAB1 SAA7785 Joystick A Button 1 Interface This pin functions as an input for the joystick A button 1. JBB2 Joystick B Button 2 Interface This pin functions as an input for the joystick B button 2. JBB1 Joystick B Button 1 Interface This pin functions as an input for the joystick B button 1. MIDI INTERFACE MIDIIN MIDI Serial Data Input This signal is part of the standard 2 wire MIDI interface.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator AC_RST_N# SAA7785 AC’97 Master Reset The external AC’97 codec has a master reset line which is has a separate control. The codec status must report a ready before any audio or modem data is transmitted to the codec. DSP SERIAL PORTS/GENERAL PURPOSE I/O SPDO Sony/Philips Digital Interface Format Output Port Consumer format S/PDIF Output Port.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 PLL/DSPCLK SUBSYSTEM INTERFACE CCLK CODEC Clock Input This pin is the raw 24.576MHz clock from the AC’97 crystal. The CCLK clock is used to provide a fixed time base for many functions within the SAA7785 device. DSPCLK DSP Clock Input This pin can be used as the clock input for the SAA7785 for the DSP subsystem in place of the PLL driving the clock.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 DSP EXTERNAL MEMORY INTERFACE MA[14:0] External Memory Address Address lines for the external SRAM devices. The external memory interface can be used for DSP code space if the EXT_SRAM_EN (in HDCFG, bit 5) is set. Otherwise, the DSP will use internal ROM as the code source. MD[15:0] External Memory Data Bus Word wide data bus for the external SRAM. Use 6ns memory for maximum DSP performance.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 SAA7785 ThunderBird Avenger™ Functional Block Descriptions Register Table Document Description and Example The next table gives an example of how registers are documented in this specification.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 The PCI datapath block contains the multiplexors and registers to steer the data to and from the PCI interfaces. The data is de-multiplexed from the external PCI interface to the internal master and slave busses. Control logic from the master and slave devices control the datapath.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 master cycles. Note that the SSA7785 ThunderBird Avenger™ cannot initiate a master cycle to itself. SSA7785 ThunderBird Avenger™ summarizes the access rules for configuration and I/O cycles. TABLE 6 BIT Width Device Access Rules Cycle Types Data Width PCI Configuration Registers Config Read Any Follow PCI addressing rules, otherwise assert a target abort.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 PCI Master State Machine This block will performs the handshaking between the PCI interface and the PM internal bus. The PCI master will perform bursting in a linear incrementing type fashion. The PCI master state machine may also wish to provide a target lockout signal. This signal prevents the PCI target interface from responding to any master signals.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 FIGURE 6 In each of the three SSA7785 ThunderBird Avenger™ functions PCI configuration space there is a Subsystem Vendor ID register at an offset of 2Ch and a Subsystem ID register at an offset of 2Eh. Each register is 16 bits in length and is write-only by the serial EEPROM and read-only from the PCI interface. The data from the EEPROM is loaded into the registers immediately after PCI reset.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Function 0 - Audio Subsystem Subsystem Vendor ID - Offset 2Ch SAA7785 Function 1 - Joystick Subsystem ID Offset 2Eh Subsystem Vendor ID - Offset 2Ch Function 2 - 16650 Modem UART Subsystem ID Offset 2Eh Subsystem Vendor ID - Offset 2Ch Subsystem ID Offset 2Eh EEPROM Bit # Reg Bit # EEPROM Bit # Reg Bit # EEPROM Bit # Reg Bit # EEPROM Bit # Reg Bit # EEPROM Bit # Reg Bit # EEPROM Bit # Reg Bit
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 SUBSYSTEM ID SUBSYSTEM VENDOR ID 2Ch Reserved Max_Lat 30-3Bh Min_Gnt Interrupt Pin DMABBASE Interrupt Line DMAABASE 3Ch 40h Reserved 44-57h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MSCCFG ACLCFG0 VRCFG 58h 5Ch 60h Reserved TIMRCFG0 HDCFG 64h 68h Reserved 6Ch DMACFG 70h
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator D7 D6 D5 SAA7785 D4 D3 D2 D1 D0 1 0 0 VENDOR_ID[7:0] 0 POR Value Bit 15:0 Name PCI CFG 0 0 0 R/W VENDOR_ID TABLE 11 0 0 Function RO The PCI Vendor ID for Philips Semiconductors (VLSI) is 1004h.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit Name SAA7785 R/W Function 9 FBACK_ENB RO Fast Back-to-Back Enable: the SSA7785 ThunderBird Avenger™, function 0 does not support fast back to back master cycles therefore this bit always returns a zero. 8 SERR_RESP RW System Error Response: When set to 1, the SSA7785 ThunderBird Avenger™, function 0 responds to detected PCI bus address parity errors by asserting SERR#.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit Name SAA7785 R/W Function 15 R_PERR RC Received Parity Error: When set to 1, this bit indicates that the SSA7785 ThunderBird Avenger™, function 0 has detected a PCI bus parity error at least once since this bit was last reset.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit 7:0 Name R/W REVISION_ID TABLE 15 PCI CFG 0 SAA7785 Function RO The current revision ID for the SSA7785 ThunderBird Avenger™, function 0, the audio subsystem.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator TABLE 17 Master Latency Timer Register - LATIME (RW) PCI CFG 0 D7 D6 D5 0 POR Value 7:0 Name 0 0 0 R/W LATIME TABLE 18 D4 D1 D0 0 0 0 0 The primary bus latency timer specifies the number of primary clocks that the primary master may consume. The timer is reloaded at each assertion of FRAME# by the primary master.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit Name SAA7785 R/W Function 6 START RO If BIST capable, this bit will start the BIST. Writing a 1 will start the test and the BIST should write this bit to a zero when complete. Software should fail the device if the BIST is not complete after 2 seconds. 5:4 R RO Reserved. These bits always return zero. 3:0 CODE RO Completion Code. A value of zero means the device has passed its test.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator D23 D22 D21 SAA7785 D20 D19 D18 D17 D16 SONGBASE[23:16] 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 POR Value SONGBASE[15:8] 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 SONG R R R R R R IO 0 0 0 0 0 0 1 POR Value BASE[7] 0 POR Value Bit Name R/W Function 31:7 SONGBASE RW Thunderbird non-legacy device base address register.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator D15 D14 D13 SAA7785 D12 D11 D10 D9 D8 SBBASE[15:8] POR Value 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 R R R IO 0 0 0 1 SBBASE[7:4] 0 POR Value Bit Name 31:4 0 0 0 R/W Function SBBASE RW Sound Blaster programmable base address. The address should be on a 16 byte boundary. For reference, the Sound Blaster legacy base addresses are 220h and 240h.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit Name SAA7785 R/W Function 31:2 MDBASE RW MIDI port programmable base address. The address should be on a double word boundary. For reference the MIDI port legacy base addresses are 220h, 230h, 240h, 250h, 300h, 320h, 330h, 332h, 334h, 336h, 340h, and 360h. 1 R RO Reserved. This bit is reserved a must always return a zero for plug and play. 0 IO RO I/O flag.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator POR Value SAA7785 0 0 0 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 SUBVEN_ID[7:0] 0 POR Value Bit 15:0 Name PCI CFG 0 0 0 R/W SUBVEN_ID TABLE 25 0 0 Function RO Subsystem Vendor ID. The Subsystem Vendor ID register allows the manufacturer to uniquely identify their board since more than one board OEM may use the SSA7785 ThunderBird Avenger™ chip.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator TABLE 26 Interrupt Line Register - INTLINE (RW) PCI CFG 0 D7 D6 D5 0 POR Value 7:0 Name 0 0 RW D7 D5 0 0 0 0 0 0 D3 D2 D1 D0 0 0 0 0 1 Function RO Interrupt Pin. The interrupt pin register tells which interrupt the SSA7785 ThunderBird Avenger™ device uses.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit 7:0 Name R/W MINGNT TABLE 29 Function RO Minimum grant specifies how long of a burst period the device needs assuming a clock speed of 33MHz. Since the SSA7785 ThunderBird Avenger™, function 0, will burst a maximum of 64 double words, therefore requiring about 75 33MHz clocks or 2.25 microseconds. The time units specified are in 0.25 microsecond increments.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit Name SAA7785 R/W Function 5:4 DMAABASE RW DMA channel A programmable base address, bits 5:4. These bits select a channel number for this channel. In LAM DMAABASE[5:4] select the channel number that this DMA represents, it should be different than DMABBASE[5:4]. 3 R RO Reserved. This bit must always be zero. 2:1 XFRSIZ RW DMA transfer size.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator TABLE 32 SAA7785 Miscellaneous Configuration Register - MSCCFG (RO/RW) PCI CFG 0 D7 D6 ASYMCLK[1:0] D5 D4 D3 D2 RDY_EN CFGCLK BHEN D1 PCCH[1:0] PCPCI Offset 58h _EN 0 POR Value Bit D0 0 Name 0 0 0 R/W 0 0 0 Function 7:6 ASYMCLK RW Asymmetrical Clock Select. These bits program the duty cycle for the input for the two phase DSP clock generator.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Reserved SAA7785 Reserved Reserved GAMECFG0 Reserved TABLE 34 PCI CFG 1 6Ch 70-FFh Vendor ID Register - VENDOR_ID (RO) D15 D14 D13 D12 D11 D10 D9 D8 VENDOR_ID[15:8] Offset 00h POR Value 0 0 0 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 VENDOR_ID[7:0] 0 POR Value Bit 15:0 Name PCI CFG 1 0 0 R/W VENDOR_ID TABLE 35 0 0 Function RO The PCI Vendor ID for Philips Semiconduc
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator D7 D6 D5 D4 D3 D2 D1 D0 STEPPING PERR_ MEM_ SPEC_ MAST_ MEM_ IO_ RESP SNOOP_ ENB INV_EN CNTL CNTL CNTL CNTL 0 0 0 0 0 0 0 0 POR Value Bit SAA7785 Name R/W Function 15:10 R RO Reserved. These bits always return zero.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 D7 D6 D5 D4 D3 D2 D1 D0 F_ UDF MHz66 R R R R R 0 0 0 0 0 0 0 BK2BK 1 POR Value Bit Name R/W Function 15 R_PERR RC Received Parity Error: When set to 1, this bit indicates that the SSA7785 ThunderBird Avenger™, function 1 has detected a PCI bus parity error at least once since this bit was last reset.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit 7:0 Name R/W REVISION_ID TABLE 39 PCI CFG 1 SAA7785 Function RO The current revision ID for the SSA7785 ThunderBird Avenger™ joystick.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 PCI CFG 1 D7 D6 D5 D4 D3 D2 D1 D0 POR Value 0 0 0 0 0 0 0 0 Bit 7:0 Name R/W LATIME TABLE 42 Function RO The primary bus latency timer specifies the number of primary clocks that the primary master may consume. It is set to zero since the joystick is a target only.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 The SSA7785 ThunderBird Avenger™, contains one legacy I/O base registers in configuration space 1. The joystick is the sole legacy I/O base address register and is documented here.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit 15:0 Name R/W SUBVEN_ID TABLE 46 PCI CFG 1 SAA7785 Function RO Subsystem Vendor ID. The Subsystem Vendor ID register allows the manufacturer to uniquely identify their board since more than one board OEM may use the SSA7785 ThunderBird Avenger™ chip.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit 7:0 Name R/W INTLINE TABLE 48 Function RO Interrupt Line. The Interrupt Line register is an eight bit register used to communicate interrupt line routing information. The value in this register tells which input of the system interrupt controller(s) the SSA7785 ThunderBird Avenger™ Device's interrupt pin is connected to. It is set to 00h to use function 0’s interrupt line.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit 7:0 Name SAA7785 R/W MAXLAT Function RO Maximum latency specifies how often a device needs to gain access to the PCI bus. The SSA7785 ThunderBird Avenger™, function 1, is a target only, this register is read only and set to zero. PCI Configuration Space 2 The following table is a summary of all the PCI configuration space registers.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator TABLE 53 PCI CFG 2 SAA7785 Device ID Register - DEVICE_ID (RO) D15 D14 D13 D12 D11 D10 D9 D8 DEVICE_ID[15:8] Offset 02h 0 0 0 0 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 POR Value DEVICE_ID[7:0] 0 POR Value Bit 15:0 Name PCI CFG 2 0 0 R/W DEVICE_ID TABLE 54 0 0 Function RO The Device ID for the SSA7785 ThunderBird Avenger™, function 2 is 0306h.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit Name SAA7785 R/W Function 5 SNOOP_ENB RO VGA Snoop Enable. The SSA7785 ThunderBird Avenger™, function 2 does not support VGA snoop enable, therefor this bit always returns a zero. 4 MEM_INV_EN RO Memory Write and Invalidate Enable: Always returns 0. 3 SPEC_CNTL RO Special Cycle Control: Controls the devices ability to respond to Special Cycle Operations.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit Name SAA7785 R/W Function 11 ST_ABORT RC Signalled Target Abort: When set to 1, this bit indicates that the SSA7785 ThunderBird Avenger™, function 2 has signalled a target abort at least once since this bit was last reset. 10:9 DEVSEL_TM G RO DEVSEL Timing: This field indicates the timing of the DEVSEL output (when a PCI master is accessing a SSA7785 ThunderBird Avenger™ resource).
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator PCI CFG 2 SAA7785 D23 D22 D21 D20 D19 D18 D17 D16 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 PGM_IFACE[7:0] 0 POR Value 0 0 0 Bit Name 23:16 BASE_CLASS RO The base class of 07h describes simple communication devices. 15:8 SUB_CLASS RO The sub class of 00h describes serial controllers. 7:0 PGM_IFACE RO The interface of 02h details a 16550 compatible serial controller.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit Name SAA7785 R/W Function 7 MULTI_FN RO For the SSA7785 ThunderBird Avenger™, function 2, this bit has no meaning. 6:0 HEADER RO Header Type. A 00h indicates this device is not a PCI-to-PCI bridge.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 UARTBASE[15:8] POR Value 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 R R IO 0 0 1 UARTBASE[7:3] 0 POR Value Bit 0 Name 0 0 0 R/W Function 31:3 UARTBASE RW 16650 UART base address. The address should be on a 8 byte boundary. For reference, 550 compatible UART legacy base addresses are 3E8h, 338h, 2E8h, 220h, 238h, 2E0h, 228h, 3F8h, and 2F8h. 2:1 R RO Reserved.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator SAA7785 SUBSYS_ID[15:8] Offset 2Eh POR Value 0 0 0 0 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 SUBSYS_ID[7:0] 0 POR Value Bit 15:0 Name 0 Function RO Subsystem ID. The Subsystem ID register allows the manufacturer to uniquely identify their board since more than one board OEM may use the SSA7785 ThunderBird Avenger™ chip.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit 7:0 Name R/W INTPIN TABLE 67 Function RO Interrupt Pin. The interrupt pin register tells which interrupt the SSA7785 ThunderBird Avenger™ device uses. The read only value of 00h implies that the SSA7785 ThunderBird Avenger™ device shares the INT A interrupt pin with function 0. There is no legacy interrupt support for function 2.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator FIGURE 7 SAA7785 MULTIMEDIA TIMER BLOCK DIAGRAM CLOCK DIVIDE LOGIC CCLK COUNTER CLOCK CTL CTL INTERNAL PS BUS INTERFACE PS BUS COUNT 20 BIT - 1uS RESOLUTION UP COUNTER INTR INTERRUPT GENERATION LOGIC MULTIMEDIA TIMER REGISTER DEFINITION There are five registers that control the multimedia timer. These registers are the timer control register, timer status, and timer count registers.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit Name SAA7785 R/W Function 2 FSTCLK RW Fast Clock Enable. When set, the timer counter will use the CCLK clock instead of the 570 ns clock. This function will reduce the simulation and test time of the device. 1 TMRRST RW Timer Reset. When set, this bit holds the multimedia timer in reset. The multimedia timer is also reset by the system reset. 0 R RO Reserved. This bit returns a zero.
Philips Semiconductors Preliminary Specification ThunderBird AvengerTM PCI Audio Accelerator Bit 3:0 Name R/W TMCOUNT2 TABLE 72 Function RW High Nibble Timer Count. This nibble is the most significant digits of the timer value. TMCOUNT1 (RW) - MULTIMEDIA TIMER COUNT REGISTER 1 SONGBASE D7 D6 D5 Offset 02h 7:0 0 Name 0 0 D1 D0 0 0 0 0 Function RW Middle Byte Timer Count. This byte is the middle significant digits of the timer value.
Philips Semiconductors Preliminary specification ThunderBird Avenger PCI Audio Accelerator SAA7785 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date.
