Datasheet

DRV8830
www.ti.com SLVSAB2G –MAY 2010–REVISED DECEMBER 2015
7.3.4.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled, the FAULTn
signal will be driven low, and the FAULT and OCP bits in the FAULT register will be set. The device will remain
disabled until the CLEAR bit in the FAULT register is written to 1, or VCC is removed and re-applied.
Overcurrent conditions are sensed independently on both high and low side devices. A short to ground, supply,
or across the motor winding will all result in an overcurrent shutdown. Note that OCP is independent of the
current limit function, which is typically set to engage at a lower current level; the OCP function is intended to
prevent damage to the device under abnormal (for example, short circuit) conditions.
7.3.4.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled, the FAULTn signal will be
driven low, and the FAULT and OTS bits in the serial interface register will be set. Once the die temperature has
fallen to a safe level operation will automatically resume.
7.3.4.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VCC pins falls below the undervoltage lockout threshold voltage, all FETs in the
H-bridge will be disabled, the FAULTn signal will be driven low, and the FAULT and UVLO bits in the FAULT
register will be set. Operation will resume when VCC rises above the UVLO threshold.
Table 2. Device Protection
FAULT CONDITION ERROR REPORT H-BRIDGE INTERNAL CIRCUITS RECOVERY
VCC undervoltage
VCC < V
UVLO
FAULTn Disabled Disabled VCC > V
UVLO
(UVLO)
Overcurret (OCP) I
OUT
> I
OCP
FAULT n Disabled Operating Power cycle VCC
Thermal shutdown
T
J
> T
TSD
FAULTn Disabled Operating T
J
> T
TSD
– T
HYS
(TSD)
7.4 Device Functional Modes
The DRV8830 is active when either IN1 or IN2 are set to a logic high. Sleep mode is entered when both IN1 and
IN2 are set to a logic low. When in sleep mode, the H-bridge FETs are disabled (Hi-Z).
Table 3. Modes of Operation
FAULT CONDITION H-BRIDGE INTERNAL CIRCUITS
Operating IN1 or IN2 high Operating Operating
Sleep mode IN1 or IN2 low Disabled Diabled
Fault encountered Any fault condition met Disabled See Table 2
7.4.1 Bridge Control
The IN1 and IN2 control bits in the serial interface register enable the H-bridge outputs. Table 4 shows the logic:
Table 4. H-Bridge Logic
IN1 IN2 OUT1 OUT2 FUNCTION
0 0 Z Z Standby / coast
0 1 L H Reverse
1 0 H L Forward
1 1 H H Brake
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