Datasheet

DRV8830
SLVSAB2G –MAY 2010–REVISED DECEMBER 2015 www.ti.com
When both bits are zero, the output drivers are disabled and the device is placed into a low-power shutdown
state. The current limit fault condition (if present) is also cleared.
At initial power up, the device will enter the low-power shutdown state. Note that when transitioning from either
brake or standby mode to forward or reverse, the voltage control PWM starts at zero duty cycle. The duty cycle
slowly ramps up to the commanded voltage. This can take up to 12 ms to go from standby to 100% duty cycle.
7.5 Programming
7.5.1 I
2
C-Compatible Serial Interface
The I
2
C interface allows control and monitoring of the DRV8830 by a microcontroller. I
2
C is a two-wire serial
interface developed by Philips Semiconductor (see I
2
C – Bus Specification, Version 2.1, January 2000). The bus
consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both
SDA and SCL lines are pulled high.
A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer.
A slave device receives and/or transmits data on the bus under control of the master device. This device
operates only as a slave device.
I
2
C communication is initiated by a master sending a start condition, a high-to-low transition on the SDA I/O while
SCL is held high. After the start condition, the device address byte is sent, most-significant bit (MSB) first,
including the data direction bit (R/W). After receiving a valid address byte, this device responds with an
acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse.
The lower three bits of the device address are input from pins A0 - A1, which can be tied to VCC (logic high),
GND (logic low), or left open. These three address bits are latched into the device at power up, so cannot be
changed dynamically.
The upper address bits of the device address are fixed at 0xC0h, so the device address is as follows:
Table 5. Device Addresses
A3..A0 BITS
A1 PIN A0 PIN ADDRESS (WRITE) ADDRESS (READ)
(as below)
0 0 0000 0xC0h 0xC1h
0 open 0001 0xC2h 0xC3h
0 1 0010 0xC4h 0xC5h
open 0 0011 0xC6h 0xC7h
open open 0100 0xC8h 0xC9h
open 1 0101 0xCAh 0xCBh
1 0 0110 0xCCh 0xCDh
1 open 0111 0xCEh 0xCFh
1 1 1000 0xD0h 0xD1h
The DRV8830 does not respond to the general call address.
A data byte follows the address acknowledge. If the R/W bit is low, the data is written from the master. If the R/W
bit is high, the data from this device are the values read from the register previously selected by a write to the
subaddress register. The data byte is followed by an acknowledge sent from this device. Data is output only if
complete bytes are received and acknowledged. A stop condition, which is a low-to-high transition on the SDA
I/O while the SCL input is high, is sent by the master to terminate the transfer.
A master bus device must wait at least 60 μs after power is applied to VCC to generate a START condition.
I
2
C transactions are shown in the timing diagrams Figure 9 and Figure 10:
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