Datasheet

S
1 1
0
(As)
(An)
W
START
Slave
Address
ACK
Sub
Address
ACK
(Dn) (Dn+1)
Data
ACK
Data
ACK
STOP
S
1 1
0
(As)
(An)
W
S
1 1
0
(As)
(Dn)
R
(Dn+1)
START
Slave
Address
ACK
Sub
Address
ACK
START
Slave
Address
ACK
Data
ACK
Data
ACK
STOP
DRV8830
www.ti.com SLVSAB2G –MAY 2010–REVISED DECEMBER 2015
Figure 9. I
2
C Read Mode
Figure 10. I
2
C Write Mode
7.6 Register Maps
7.6.1 I
2
C Register Map
Table 6. I
2
C Register Map
REGISTER SUB ADDRESS (HEX) REGISTER NAME DEFAULT VALUE DESCRIPTION
Sets state of outputs and output
0 0x00 CONTROL 0x00h
voltage
Allows reading and clearing of fault
1 0x01 FAULT 0x00h
conditions
7.6.1.1 REGISTER 0 – CONTROL
The CONTROL register is used to set the state of the outputs as well as the DAC setting for the output voltage.
The register is defined as follows:
Table 7. Register 0 – Control
D7 - D2 D1 D0
VSET[5..0] IN2 IN1
VSET[5..0]: Sets DAC output voltage. Refer to Voltage Setting above.
IN2: Along with IN1, sets state of outputs. Refer to Bridge Control above.
IN1: Along with IN2, sets state of outputs. Refer to Bridge Control above.
7.6.1.2 REGISTER 1 – FAULT
The FAULT register is used to read the source of a fault condition, and to clear the status bits that indicated the
fault. The register is defined as follows:
Table 8. Register 1 – Fault
D7 D6 - D5 D4 D3 D2 D1 D0
CLEAR Unused ILIMIT OTS UVLO OCP FAULT
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