Datasheet
Table Of Contents
- 1 Features
- 2 Applications
- 3 Description
- Table of Contents
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10 Layout
- 11 Device and Documentation Support
- 12 Mechanical, Packaging, and Orderable Information
OUT1
OUT2
2
1
2
PWM on
PWM off
VCC
1
Shown with
IN1=1, IN2=0
DRV8830
www.ti.com
SLVSAB2G –MAY 2010–REVISED DECEMBER 2015
Feature Description (continued)
Note that if the programmed output voltage is greater than the supply voltage, the device will operate at 100%
duty cycle and the voltage regulation feature will be disabled. In this mode the device behaves as a conventional
H-bridge driver.
During the PWM off time, winding current is recirculated by enabling both of the high-side FETs in the bridge.
This is shown in Figure 8.
Figure 8. Voltage Regulation
7.3.2 Voltage Setting (VSET DAC)
The DRV8830 includes an internal reference voltage that is connected to a DAC. This DAC generates a voltage
which is used to set the PWM regulated output voltage as described in Voltage Regulation.
The DAC is controlled by the VSET bits from the serial interface. The commanded output voltage is shown in
Table 1.
Table 1. Commanded Output Voltage
VSET[5..0] OUTPUT VOLTAGE VSET[5..0] OUTPUT VOLTAGE
0x00h Reserved 0x20h 2.57
0x01h Reserved 0x21h 2.65
0x02h Reserved 0x22h 2.73
0x03h Reserved 0x23h 2.81
0x04h Reserved 0x24h 2.89
0x05h Reserved 0x25h 2.97
0x06h 0.48 0x26h 3.05
0x07h 0.56 0x27h 3.13
0x08h 0.64 0x28h 3.21
0x09h 0.72 0x29h 3.29
0x0Ah 0.80 0x2Ah 3.37
0x0Bh 0.88 0x2Bh 3.45
0x0Ch 0.96 0x2Ch 3.53
0x0Dh 1.04 0x2Dh 3.61
0x0Eh 1.12 0x2Eh 3.69
0x0Fh 1.20 0x2Fh 3.77
Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: DRV8830